![]() |
|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
HV853 High Voltage, Low Noise, Inductorless EL Lamp Driver Features No external components required when using an external EL clock frequency Audible noise reduction with improved EMI EL frequency can be set by an external resistor DC to AC converter Drives up to 5.3nF (approx. 1.5in2 lamp) load Output voltage regulation Enable function Available in 8-Lead DFN and MSOP packages General Description The Supertex HV853 is a high voltage, low noise EL (electroluminescent) lamp driver. It is the low noise version of the HV852 with improved EMI performance, operating over an input voltage range of 3.2V to 5.0V. It is designed to drive EL lamps of up to 1.5in2, with capacitive values up to 5.3nF. The HV853 converts a low voltage DC input to a high voltage AC output across an EL lamp. A nominal regulated output voltage of 80V is applied to the EL lamp. It uses a charge pump scheme to boost the input voltage eliminating the need for an external inductor, diode, and high voltage capacitor commonly found in conventional topologies. The charge pump circuit discharges its energy into an EL lamp through a high voltage H-bridge. Once the voltage reaches its regulated limit, it is turned off to conserve power. The EL lamp is then discharged to ground and the H-bridge changes state to allow the charge pump to charge the EL lamp in the opposite direction. The EL lamp frequency can be set either by an external resistor REL or by applying an external clock where the clock frequency is divided by 128 to set the EL lamp frequency. Applications Cellular phone keypad Watches Small handheld wireless devices MP3 Players Typical Application Circuits VDD = ON GND = OFF 1 + VDD = ON GND = OFF REL 2 3 4 VDD REL EN CLKIN VA VB GND CLKEN 8 7 6 5 VDD GND 1 VDD - CDD EL LAMP + VDD REL EN CLKIN VA VB GND CLKEN 8 7 6 5 VDD VDD - CDD 2 3 4 EL LAMP HV853 EL Lamp Frequency set by REL HV853 EL Lamp Frequency set by External Clock HV853 Ordering Information Package Options DEVICE 8-Lead DFN 3x3mm body, 0.80mm height (max), 0.65mm pitch Product Marking 8-Lead MSOP 3x3mm body, 1.10mm height (max), 0.65mm pitch H853 YWLL Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number = "Green" Packaging HV853 HV853K7-G HV853MG-G 8-Lead DFN Package (K7) Top Marking -G indicates package is RoHS compliant (`Green') H853 LLLL Bottom Marking L = Lot Number YY = Year Sealed WW = Week Sealed = "Green" Packaging Absolute Maximum Ratings Parameter VDD, supply voltage Storage temperature Power dissipation (8-Lead DFN) Power dissipation (8-Lead MSOP) Value -0.5V to 6.5V -65C to +150C 1.6W 300mW VDD REL EN CLKIN 1 2 3 4 YYWW 8-Lead MSOP Package (MG) Pin Configuration VDD 8 7 6 5 1 2 8 VA 7 VB 6 VA VB GND CLKEN CLKIN 4 5 CLKEN REL Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. EN 3 GND 8-Lead DFN (top view) 8-Lead MSOP (top view) Note: Pads are at the bottom of the package. Center heat slug is at ground potential. Electrical Characteristics (Over recommended operating conditions unless otherwise specified, TA = 25C) Symbol IDDQ VA or VB VA-VB IDD VA or VB VA-VB fEL trout tfout VIL VIH IIL IIH Parameter Quiescent current Peak output voltage Peak to peak output voltage Operating current Peak output voltage Peak to peak output voltage EL lamp frequency Output voltage rise time Output voltage fall time Min 68 136 68 136 240 150 Typ 80 160 15 80 160 280 450 - Max 150 92 184 30 92 184 320 - Units nA V V mA V V Hz s s Conditions EN = 0V No load See Figure 1 VDD = 3.5V REL = 1.5M Load = 3.3nF + 1.0k 1.0in2 lamp 0V to 90% of final value 90% to 10% of final value Logic Inputs Input logic low voltage Input logic high voltage Input logic low current Input logic high current 0 2.0 0.5 VDD 1.0 1.0 V V A A --------- 2 HV853 Symbol ENrise ENfall Cin Parameter Enable input rise time (for delay turn off) Enable input fall time (for delay turn off) Logic input capacitance Min 0.01 10 Typ Max 10 5.0 10 Units ms s pF Conditions Using external R-C circuit, see Figure 2 --- Recommended Operating Conditions Symbol VDD fEL Cload TA Parameter Input voltage EL lamp frequency EL lamp capacitance Operating temperature Min 3.2 50 0 -25 Typ Max 5.0 500 5.3 +85 Units V Hz nF O Conditions --------- C Typical Output Waveform Functional Block Diagram VDD EN VDD Capacitor Charge Pump Circuit VA VSENSE Feedback CLKIN CLKEN REL VDD High Voltage Level Translators VB EL Oscillator MOSFET Full Bridge GND 3 HV853 Typical Performance (The following was the observed performance when driving a 1.0in2 green lamp) Load REL VDD 3.2 3.5 IDD 13.1 12.9 12.7 12.5 12.3 VA-VB 158 158 158 158 158 fEL 3.3nF + 1.0k 1.5M 3.8 4.2 5.0 294 Figure 1: Typical Application + VDD - CDD VDD = ON GND = OFF 1 VDD REL 2 REL 3 EN 4 CLKIN VA VB GND CLKEN 8 7 6 5 EL Lamp HV853 Figure 2: Push Button Turn on with Delay Turn off 1 + VDD Push Button Turn On CDD REL VDD REL EN CLKIN VA VB GND CLKEN 8 7 6 5 EL Lamp 2 3 4 - C R HV853 RC time constant will set Turn OFF Delay time Figure 3: Independent Programmable Output Frequency (fEL) + VDD VDD = ON GND = OFF VDD GND fCLK Note: fEL = fCLK/128 CDD 1 2 3 4 VDD REL EN CLKIN VA VB GND CLKEN 8 7 6 5 VDD EL Lamp HV853 4 HV853 Pin Description Pin # 1 Name VDD Description Input supply voltage pin. An external resistor to VDD will set the EL lamp frequency. The EL frequency is inversely proportional to the REL resistor value. A 1.5M resistor would provide a nominal lamp frequency of 294Hz fEL = (1.5M)(294) REL When using an external clock to set the EL lamp frequency, the REL pin should be connected to ground. 3 EN Enable input pin. Logic high will turn the device on. An external R-C circuit can be added for a delayed turn off. Logic input pin. An external logic clock applied to this pin can be used to set the EL lamp frequency (see Figure 3). The EL lamp frequency is the external clock frequency divided by 128. This is useful for applications requiring the EL lamp to be synchronized to a system clock. Connect to ground when not in use. Logic input pin. Logic high will cause the EL lamp frequency to be set by the CLKIN input. Logic low will cause the EL lamp frequency to be set by the external REL resistor. IC ground pin. EL lamp driver output pin. The EL lamp is connected across VA and VB terminals. EL lamp driver output pin. The EL lamp is connected across VA and VB terminals. 2 REL 4 CLKIN 5 6 7 8 CLKEN GND VB VA 5 HV853 8-Lead DFN Package Outline (K7) 3x3mm body, 0.80mm height (max), 0.65mm pitch D 8 D2 8 E Note 1 (Index Area D/2 x E/2) E2 1 1 Note 1 (Index Area D/2 x E/2) Top View View B Bottom View Note 3 A A3 b e Seating Plane Note 2 L L1 A1 Side View View B Notes: 1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol MIN Dimension (mm) NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 0.20 REF b 0.25 0.30 0.35 D 2.85 3.00 3.15 D2 1.60 2.50 E 2.85 3.00 3.15 E2 1.35 1.75 e 0.65 BSC L 0.30 0.40 0.50 L1 0.15 0O 14O JEDEC Registration MO-229, Variation WEEC-2, Issue C, Aug. 2003. Drawings not to scale 6 HV853 8-Lead MSOP Package Outline (MG) 3x3mm body, 1.10mm height (max), 0.65mm pitch D 8 1 (x4) E E1 Note 1 (Index Area D1/2 x E1/2) L L2 Gauge Plane 1 L1 Seating Plane Top View A View B View B A A2 Seating Plane A1 e b A Side View View A-A Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol Dimension (mm) MIN NOM MAX A 0.75 1.10 A1 0.00 0.15 A2 0.75 0.85 0.95 b 0.22 0.38 D 2.80 3.00 3.20 E 4.65 4.90 5.15 E1 2.80 3.00 3.20 e 0.65 BSC L 0.40 0.60 0.80 L1 0.95 REF L2 0.25 BSC 0O 8 O 1 5O 15O JEDEC Registration MO-187, Variation AA, Issue E, Dec. 2004. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV853 NR051607 7 |
Price & Availability of HV853K7-G
![]() |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |