View ADP3196_4849517.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

6-Bit Programmable 2- to 4-Phase Synchronous Buck Controller ADP3196
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase 10 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable 0.3750 V to 1.55 V output Programmable short-circuit protection with programmable latch-off delay
FUNCTIONAL BLOCK DIAGRAM
VCC 31 SHUNT REGULATOR OSCILLATOR SET RESET EN 30 PWM1 19 OD RT 12 RAMPADJ 13
UVLO SHUTDOWN GND 18
+ CMP - 800mV - + - + + DAC - 250mV - CURRENT BALANCING CIRCUIT + CMP - + CMP -
RESET
29 PWM2
EN
1
1.8V CSREF
RESET 2-/3-/4-PHASE DRIVER LOGIC
28 PWM3
+ CMP -
27 PWM4
RESET
CURRENT LIMIT PWRGD 2 DELAY CROWBAR 25 SW1 TTSENSE 10 24 SW2 THERMAL THROTTLING CONTROL 23 SW3 22 SW4
APPLICATIONS
Desktop PC power supplies for next generation AMD processors VRM modules
VRMHOT VRM_OFF
9 8
17 CSCOMP ILIMIT 11 DELAY 7 CURRENT MEASUREMENT AND LIMIT + - 15 CSREF 16 CSSUM 21 IMON IREF 20 COMP 5 PRECISION REFERENCE FBRTN 3 SOFT START CONTROL 6 SS - + + - 14 LLSET 4 FB
GENERAL DESCRIPTION
The ADP3196 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Advanced Micro Devices, Inc. (AMD) processors. It uses an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.3750 V and 1.55 V. This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. The ADP3196 supports a programmable slope function to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. This can be disabled by connecting Pin LLSET to Pin CSREF.
1
1
VID DAC
34
35
36 VID3
37 VID2
38 VID1
39 VID0
ADP3196
VID5 VID4
Figure 1. Functional Block Diagram
The ADP3196 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU. The ADP3196 has a built-in shunt regulator that allows the part to be connected to the 12 V system supply through a series resistor. The ADP3196 is specified over the extended commercial temperature range of 0C to +85C and is available in a 40-lead LFCSP.
Protected by U.S. Patent Number 6,683,441; others patents pending.
(c)2008 SCILLC. All rights reserved. January 2008 - Rev. 1
Publication Order Number: ADP3196/D
06371-001
ADP3196 TABLE OF CONTENTS
Features...............................................................................................1 Applications .......................................................................................1 General Description..........................................................................1 Functional Block Diagram...............................................................1 Table of Contents...............................................................................2 Revision History................................................................................2 Specifications .....................................................................................3 Test Circuits .......................................................................................5 Absolute Maximum Ratings ............................................................6 ESD Caution ..................................................................................6 Pin Configuration and Function Description...............................7 Typical Performance Characteristics..............................................9 Theory of Operation.......................................................................10 Start-Up Sequence ......................................................................10 Phase Detection Sequence .........................................................10 Master Clock Frequency ............................................................11 Output Voltage Differential Sensing ........................................11 Output Current Sensing.............................................................11 Active Impedance Control Mode .............................................11 Current Control Mode and Thermal Balance.........................11 Voltage Control Mode ................................................................12 Current Reference.......................................................................12 Enhanced PWM Mode...............................................................12 Delay Timer .................................................................................12 Soft Start.......................................................................................12 Current Limit, Short-Circuit, and Latch-Off Protection.......13 Dynamic VID ..............................................................................14 Power-Good Monitoring ...........................................................14 Output Crowbar..........................................................................14 Output Enable and UVLO.........................................................14 Thermal Monitoring...................................................................14 Layout and Component Placement..........................................17 Outline Dimensions........................................................................18 Ordering Guide ...........................................................................18
REVISION HISTORY
01/08 - Rev 1: Conversion to ON Semiconductor 10/06--Revision 0: Initial Version
Rev. 1 | Page 2 of 18 | www.onsemi.com
ADP3196 SPECIFICATIONS
VCC = 5 V, FBRTN = GND, TA = 0C to 85C, unless otherwise noted.1 Table 1.
Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range2 Accuracy Load Line Positioning Accuracy Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate LLSET Input Voltage Range LLSET Input Bias Current VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation Symbol VIREF IIREF VCOMP VFB Conditions Min Typ 1.5 15 Max Unit V A V mV mV LSB A A A MHz V/s mV nA V V A ns 4 220 MHz kHz kHz kHz V mV A mV nA MHz V/s V V A ms +6 +200 26 20 +4 11 1.33 125 % mV k A % A V V mV mV/V
RIREF = 100 k
14.25 0.05 -10 -78 -1 -9
15.75 4.4 10
Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF (see Figure 2) CSREF - LLSET = 80 mV IFB = 0.5 x IIREF FB forced to VOUT - 3% COMP = FB COMP = FB Relative to CSREF
-80 -7.5 65 500 20 25
IFB IFBRTN ICOMP GBW(ERR) VLLSET ILLSET VIL(VID) VIH(VID) IIN(VID)
-82 +1 -6 200
-250 -10
+250 +10 0.6
VID(X), VIDSEL VID(X), VIDSEL VID code change to FB change
1.4 -10 400 0.25 180
fOSC fPHASE
TA = 25C, RT = 205 k, 4 phase TA = 25C, RT = 118 k, 4 phase TA = 25C, RT = 55 k, 4 phase RT = 243 k to GND RAMPADJ - FB, DAC = 1.55 V
Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Current Limit Latch-Off Delay Time IMON Output CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR ILIMIT Bias Current ILIMIT Voltage Maximum Output Voltage Current Limit Threshold Voltage Current Limit Setting Ratio
VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSSUM) GBW(CSA)
1.9 -50 1 -1.0 -10
200 400 800 2.0
2.1 +50 50 +1.0 +10
CSSUM - CSREF (see Figure 3) CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF
10 10 0 0.05 500 8 -6 -600 10 8 -4 9 1.09 3 80 3.5 3.5
ICSCOMP tOC(DELAY) IMON VSW(X)CM RSW(X) ISW(X) ISW(X) IILIMIT VILIMIT VCL CDELAY = 10 nF 10 x (CSREF - CSCOMP) > 50mV
SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V IILIMIT = 2/3 x IIREF RILIMIT = 121k (VILIMIT = IILIMIT x RILIMIT) VCSREF - VCSCOMP, RILIMIT = 121 k VCL/IILIMIT
Rev. 1 | Page 3 of 18 | www.onsemi.com
17 12
10 1.21 100 82.6
ADP3196
Parameter DELAY TIMER Normal Mode Output Current Output Current in Current Limit Threshold Voltage SOFT START Output Current (Startup) Output Current (DAC Code Change) ENABLE INPUT Threshold Voltage Hysteresis Input Current Delay Time OD OUTPUT Output Low Voltage Output High Voltage OD Pull-Down Resistor THERMAL THROTTLING CONTROL TTSENSE Voltage Range TTSENSE Bias Current TTSENSE VRM_OFF Threshold Voltage TTSENSE VRMHOT Threshold Voltage TTSENSE Hysteresis VRM_OFF Output Low Voltage VRMHOT Output Low Voltage POWER-GOOD COMPARATOR Overvoltage Threshold Undervoltage Threshold Output Low Voltage Power-Good Delay Time During Soft Start2 VID Code Changing VID Code Static Crowbar Trip Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage POWER SUPPLY VCC DC Supply Current UVLO Turn On Current UVLO Threshold Voltage UVLO Threshold Voltage
1
Symbol IDELAY IDELAY(CL) VDELAY(TH) ISS(STARTUP) ISS(DAC)
Conditions IDELAY = IIREF IDELAY(CL) = 0.25 x IIREF
Min 12 3.0 1.6 3 15
Typ 15 3.75 1.7 3.75 18.75
Max 18 4.5 1.8 4.5 22.5
Unit A A V A A
During startup, ISS(STARTUP) = 0.25 x IIREF DAC code change, ISS(DAC) = 1.25 x IIREF
VTH(EN) VHYS(EN) IIN(EN) tDELAY(EN) VOL(OD) VOH(OD) EN > 950 mV, CDELAY = 10 nF
750 80
800 100 -1 2 160
850 125
mV mV A ms
500
mV V k
4
5 60
Internally limited
0 -135 1.06 765
-123 1.105 810 50 150 150
5 -111 1.15 855
V A V mV mV mV mV mV mV mV mV mV ms s ns V s ns
VOL(VRFAN) VOL(VRHOT) VPWRGD(OV) VPWRGD(UV) VOL(PWRGD)
I VRFAN (SINK) = -4 mA I VRHOT (SINK) = -4 mA Relative to nominal DAC output; DAC = 0.5 V to 1.55 V Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V Relative to nominal DAC output; DAC = 0.5 V to 1.55 V Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V IPWRGD(SINK) = -4 mA CDELAY = 10 nF 100 200 190 -300 -310
300 300 300 310 -200 -190 300
250 250 -250 -250 150 2 250 200 1.8 250 400 160 5 5 6.5
VCROWBAR tCROWBAR
Relative to FBRTN Overvoltage to PWM going low
1.75 100
1.85
VOL(PWM) VOH(PWM) VCC IVCC VUVLO VUVLO
IPWM(SINK) = -400 A IPWM(SOURCE) = 400 A VSYSTEM = 12 V, RSHUNT = 340 (see Figure 2)
500
4.0 4.65
mV V V mA mA V
5.55 25 11
VCC rising VCC falling
9 4.1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design or bench characterization, not tested in production.
Rev. 1 | Page 4 of 18 | www.onsemi.com
ADP3196 TEST CIRCUITS
12V 6-BIT CODE + 40 NC VID0 VID1 VID2 VID3 VID4 VID5 NC NC VCC 1F 680 100nF 680
12V
ADP3196
680
31
1.25V
1
680
1k 10nF 10nF
ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF
EN PWRGD FBRTN FB COMP SS DELAY VRM_OFF VRMHOT TTSENSE
ADP3196
PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 IMON
VCC FB
4
10k
3
FBRTN LLSET
14
-
V
15
100k 250k
CSREF + GND
18
1V
20k
VID DAC
100nF NC = NO CONNECT.
06371-002
VFB = FBV = 80mV - FBV = 0mV
Figure 2. Closed-Loop Output Voltage Accuracy
Figure 4. Positioning Voltage
12V
ADP3196
680 680
31
VCC CSCOMP
17
39k
100nF
16
CSSUM
1k
15
CSREF CSCOMP - 1V 40
1V
18
Figure 3. Current Sense Amplifier VOS
Rev. 1 | Page 5 of 18 | www.onsemi.com
06371-003
GND
VOS =
06371-004
ADP3196 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC FBRTN PWM3 - PWM4, RAMPADJ SW1 - SW4 <200 ns All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (JA) Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating -0.3 V to +6 V -0.3 V to +0.3 V -0.3 V to VCC + 0.3 V -5 V to +25 V -10 V to +25 V -0.3 V to VCC + 0.3 V -65C to +150C 0C to 85C 125C 100C/W 300C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages referenced to GND.
ESD CAUTION
Rev. 1 | Page 6 of 18 | www.onsemi.com
ADP3196 PIN CONFIGURATION AND FUNCTION DESCRIPTION
40 39 38 37 36 35 34 33 32 31
EN 1 PWRGD 2 FBRTN 3 FB 4 COMP 5 SS 6 DELAY 7 VRM_OFF 8 VRMHOT 9 TTSENSE 10
NC VID0 VID1 VID2 VID3 VID4 VID5 NC NC VCC
PIN 1 INDICATOR
ADP3196
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 IMON
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic EN PWRGD FBRTN FB COMP SS DELAY VRM_OFF VRMHOT Description Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no load offset point. Error Amplifier Output and Compensation Point. Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start ramp-up time and the VID on-the-fly slew rate. Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent latch-off delay time, EN delay time, and PWRGD delay time. VRM_OFF Signal. Open-drain output that asserts when the temperature at the monitoring point connected to TTSENSE exceeds the VRM_OFF threshold. Open-drain output that signals when the temperature at the monitoring point connected to TTSENSE exceeds the maximum operating temperature. For example, this can be connected to the PROCHOT# (a PC system signal) output from the CPU. VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the temperature at the desired thermal monitoring point. Current Limit Setpoint. An external resistor from this pin to GND sets the current limit threshold of the converter. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected to the center point of a resistor divider between CSCOMP and CSREF. Connecting LLSET to CSREF disables positioning. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the current sense amplifier and the positioning loop response time.
Rev. 1 | Page 7 of 18 | www.onsemi.com
10 11 12 13 14
TTSENSE ILIMIT RT RAMPADJ LLSET
15
CSREF
16 17
CSSUM CSCOMP
06371-005
NOTES 1. NC = NO CONNECT. 2. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND.
ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF
11 12 13 14 15 16 17 18 19 20
ADP3196
Pin No. 18 19 20 21 22 to 25 26, 32, 33, 40 27 to 30 Mnemonic GND OD IREF IMON SW4 to SW1 NC PWM4 to PMW1 VCC VID5 to VID0 Description Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Output Disable Logic Output. This pin is actively pulled low when the ADP3196 EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IDELAY, ISS, IILIMIT and ITTSENSE. Analog Output. Represents total load current. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. No Connection. Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3120A. Connecting the PWM3 and/or PWM4 outputs to the ADP3196 VCC pin causes that phase to turn off, allowing the ADP3196 to operate as a 2-, 3-, or 4-phase controller. A 340 resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5 V. Voltage Code DAC Inputs. These six pins are pulled down to GND, providing a logic zero if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.3750 V and 1.55 V (see Table 4).
31 34 to 39
Rev. 1 | Page 8 of 18 | www.onsemi.com
ADP3196 TYPICAL PERFORMANCE CHARACTERISTICS
7200 6400 5600
FREQUENCY (kHz)
4800 4000 3200 2400 1600 800
06371-015
0
0
100
200
300
400
500
600
700
800
900
RT (k)
Figure 6. Master Clock Frequency vs. RT
Rev. 1 | Page 9 of 18 | www.onsemi.com
ADP3196 THEORY OF OPERATION
The ADP3196 combines a multimode, fixed frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the AMD 6-bit CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today's microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. The multimode control of the ADP3196 ensures a stable, high performance topology for the following: * * * * * * * * * Balancing currents and thermals between phases High speed response at the lowest possible switching frequency and output decoupling Minimizing thermal switching losses by utilizing lower frequency operation Tight load line regulation and accuracy High current output due to 4-phase operation Reduced output ripple due to multiphase cancellation PC board layout noise immunity Ease of use and design due to independent component selection Flexibility in operation for tailoring design to low cost or high performance
5V SUPPLY UVLO THRESHOLD
0.8V ADP3196 EN VDELAY(TH) (1.7V)
DELAY
VVID SS
VCC_CORE
TD1
VVID
TD2 VR READY (ADP3196 PWRGD) TD3
CPU VID INPUTS
VID INVALID
VID VALID
Figure 7. System Start-Up Sequence
PHASE DETECTION SEQUENCE
During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3196 operates as a 4-phase PWM controller. Connecting the PWM4 pin to the VCC pin programs 3-phase operation while connecting the PWM4 pin and the PWM3 pin to the VCC pin programs 2-phase operation. While EN is low and prior to soft start, Pins PWM3 and PWM4 sink approximately 100 A. An internal comparator checks the voltage of each pin vs. a threshold of 3 V. If the pin is tied to VCC, it is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold. PWM1 and PWM2 are low during the phase detection interval, which occurs during the first four clock cycles of TD2. After this time, if the remaining PWM outputs are not pulled to VCC, the 100 A current sink is removed and they function as normal PWM outputs. If they are pulled to VCC, the 100 A current source is removed and the outputs are put into a high impedance state. The PWM outputs are logic-level devices intended for driving external gate drivers, such as the ADP3120A. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be on at the same time to allow overlapping phases.
START-UP SEQUENCE
The ADP3196 follows the start-up sequence shown in Figure 7. After both the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1). The first four clock cycles of TD2 are blanked from the PWM outputs and used for phase detection as explained in the Phase Detection Sequence section. Then, the soft start ramp is enabled (TD2) and the output comes up to the programmed DAC Voltage. After TD2 has been completed and the PWRGD masking time (equal to VID on-the-fly masking) is finished, a second ramp on the DELAY pin sets the PWRGD blanking (TD3).
Rev. 1 | Page 10 of 18 | www.onsemi.com
06371-006
ADP3196
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3196 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 4. If PWM4 is tied to VCC, then divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are tied to VCC, then divide by 2. An additional resistor divider connected between CSREF and CSCOMP, with the midpoint connected to LLSET, can be used to set the load line required by the microprocessor. The current information is then given as CSREF - LLSET. This difference signal is used internally to offset the VID DAC for voltage positioning. The difference between CSREF and CSCOMP is then used as a differential input for the current-limit comparator. This allows the load line to be set independent of the current-limit threshold. In the event that the current-limit threshold and load line are not independent, the resistor divider between CSREF and CSCOMP can be removed and the CSCOMP pin can be directly connected to the LLSET pin. To disable voltage positioning entirely (that is, no load line), connect LLSET to CSREF. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. In addition, the sensing gain is determined by external resistors to make it extremely accurate.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3196 combines differential sensing with a high accuracy VID DAC and reference and a low offset error amplifier. This maintains a worst-case specification of 10 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and the FBRTN pin. Pin FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. Pin FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 65 A to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the LLSET pin can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This allows enhanced feed forward response.
OUTPUT CURRENT SENSING
The ADP3196 provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured several ways depending on the objectives of the system as follows: * * * Output inductor DCR sensing without a thermistor for lowest cost Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature Sense resistors for highest accuracy measurements
CURRENT CONTROL MODE AND THERMAL BALANCE
The ADP3196 has individual inputs (SW1 to SW4) for each phase that are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning described previously in the Output Current Sensing section. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. External resistors can be placed in series with individual phases to create an intentional current imbalance, if desired, such as when one phase has better cooling and can support higher currents. Resistors RSW1 through RSW4 (see Figure 11) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, therefore, ensure that placeholders are provided in the layout.
The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor.
Rev. 1 | Page 11 of 18 | www.onsemi.com
ADP3196
To increase the current in any given phase, make RSW for that phase larger (make RSW = 0 for the hottest phase and do not change during balancing). Increasing RSW to only 500 makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first.
DELAY TIMER
The delay times for the start-up timing sequence are set with a capacitor from the DELAY pin to ground. In UVLO or when EN is logic low, the DELAY pin is held at ground. After the UVLO and EN signals are asserted, the first delay time (TD1 in Figure 7) is initiated. A current flows out of the DELAY pin to charge CDLY. This current is equal to IREF, which is normally 15 A. A comparator monitors the DELAY voltage with a threshold of 1.7 V. The delay time is therefore set by the IREF current charging a capacitor from 0 V to 1.7 V. This DELAY pin is used for two delay timings (TD1 and TD3) during the start-up sequence. In addition, DELAY is used for timing the current limit latch off as explained in the Current Limit, Short-Circuit, and Latch-Off Protection section.
VOLTAGE CONTROL MODE
A high gain, high bandwidth voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 4. The voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with Resistor RB and is used for sensing and controlling the output voltage at this point. A current source (equal to IREF/2) flows through RB into the FB pin and is used for setting the no load offset voltage from the VID voltage. The no load offset is positive with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP.
SOFT START
The soft start ramp rates for the output voltage are set up with a capacitor from the soft start (SS) pin to ground. During startup, the SS pin sources a current of 3.75 A. After startup, when a DAC code change occurs, the SS pin sinks or sources an 18.75 A current to control the rate at which the output voltage can transition up or down. During startup (after TD1 and the phase detection cycle are complete), the SS time (TD2 in Figure 7) starts. The SS pin is disconnected from GND and the capacitor is charged up to the programmed DAC voltage by the SS amplifier, which has an output current equal to one quarter IREF (normally 3.75 A). The voltage at the FB pin follows the ramping voltage on the SS pin, limiting the inrush current during startup. The soft start time depends on the value of the initial DAC voltage and CSS. Note that the DAC code must be set before the ADP3196 is enabled. Once the SS voltage is within 50 mV of the programmed DAC voltage, the power-good delay time (TD3) starts. Once TD2 has completed, the soft start current changes to 18.75 A. If the programmed DAC code changes after startup, then the SS pin sources or sinks a current of 18.75 A to or from the SS capacitor. This occurs until the SS voltage is within 50 mV of the newly programmed DAC voltage. If EN is taken low or VCC drops below UVLO, DELAY and SS are reset to ground in preparation for another soft start cycle.
CURRENT REFERENCE
The IREF pin is used to set an internal current reference. This reference current sets IFB, IDELAY, ISS, ILIMIT, and ITTSENSE. A resistor to ground programs the current based on the 1.5 V output.
IREF =
1.5 V RIREF
Typically, RIREF is set to 100 k to program IREF = 15 A. The following currents are then equal to: IFB = 1/2 (IREF) = 7.5 A IDELAY = IREF = 15 A ISS(STARTUP) = 1/4 (IREF) = 3.75 A ISS(DAC) = 5/4 (IREF) = 18.75 A ILIMIT = 2/3 (IREF) = 10 A ITTSENSE = 8 (IREF) = 120 A
ENHANCED PWM MODE
Enhanced PWM mode is intended to improve the transient response of the ADP3196 to a load stepup. In previous generations of controllers, when a load stepup occurred, the controller had to wait until the next turn on of the PWM signal to respond to the load change. Enhanced PWM mode allows the controller to respond immediately when a load stepup occurs. This allows the phases to respond when the load increase transition takes place.
Rev. 1 | Page 12 of 18 | www.onsemi.com
ADP3196
Figure 8 shows typical start-up waveforms for the ADP3196, while Figure 9 shows a typical DAC code change waveform. A comparator monitors the DELAY voltage and shuts off the controller when the voltage reaches 1.7 V. The current limit latch-off delay time is therefore set by the current of IREF/4 charging the delay capacitor from 0 V to 1.7 V. This delay is four times longer then the delay time during the start-up sequence. The current limit delay time only starts after the TD3 has completed. If there is a current limit during startup, the ADP3196 goes through TD1 to TD3, and then starts the latch-off time. Because the controller continues to cycle the phases during the latch-off delay time, if the short is removed before the 1.7 V threshold is reached, the controller returns to normal operation and the DELAY capacitor is reset to GND.
CH1 1V CH3 2V CH2 1V CH4 10V M 2ms A CH3 600mV
1
2
3
Figure 8. Typical Start-Up Waveforms Channel 1: CSREF, Channel 2: SS, Channel 3: DELAY, Channel 4: Phase 1 Switch Node
06371-007
4
The latch-off function can be reset by either removing and reapplying the supply voltage to the ADP3196, or by toggling the EN pin low for a short time. To disable the short-circuit latch-off function, an external resistor should be placed in parallel with CDLY. This prevents the DELAY capacitor from charging up to the 1.7 V threshold. The addition of this resistor causes a slight increase in the delay times. During startup when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. An inherent per phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage. Typical overcurrent latch-off waveforms are shown in Figure 10.
1 2
CH1 500mV CH2 500mV CH3 5V
M 2ms
A CH1
980mV
Figure 9. Typical DAC Code Change Waveforms Channel 1: CSREF, Channel 2: SS, Channel 3: Phase 1 Switch Node
CURRENT LIMIT, SHORT-CIRCUIT, AND LATCHOFF PROTECTION
The ADP3196 compares a programmable current limit setpoint to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During operation, the current from ILIMIT is equal to 2/3 of IREF, giving 10 A normally. This current, through the external resistor, sets the ILIMIT voltage, which is internally scaled to give a current limit threshold of 82.6 mV/V. If the difference in voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. If the limit is reached and TD3 has completed, a latch-off delay time starts, and the controller shuts down if the fault is not removed. The current limit delay time shares the DELAY pin timing capacitor with the start-up sequence timing. However, during current limit, the DELAY pin current is reduced to IREF/4.
1
06371-008
3
2 3
CH1 1V CH3 2V
CH2 2V CH4 10V
M 2ms
A CH1
600mV
Figure 10. Overcurrent Latch-Off Waveforms Channel 1: CSREF, Channel 2: COMP, Channel 3: DELAY, Channel 4: Phase 1 Switch Node
Rev. 1 | Page 13 of 18 | www.onsemi.com
06371-009
4
ADP3196
DYNAMIC VID
The ADP3196 has the ability to respond to dynamically changing VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the ADP3196 detects the change and ignores the DAC inputs for a minimum of 400 ns. This time prevents a false code due to logic skew while the six VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 100 s to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current limits the input supply or blows its fuse, protecting the microprocessor from being destroyed.
OUTPUT ENABLE AND UVLO
For the ADP3196 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, the EN pin must be higher than its 0.8 V threshold, and the DAC code must be valid. This initiates a system start-up sequence. If either UVLO or EN is less than their respective thresholds, the ADP3196 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and forces PWRGD, and OD signals low. In the application circuit, the OD pin should be connected to the OD inputs of the ADP3120A drivers. Grounding OD disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level, when connected to a pull-up resistor, indicates that the output voltage is within the nominal limits specified based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if the VID DAC inputs are in no CPU mode, or if the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of 200 s to prevent false signals during the time the output is changing. The PWRGD circuitry also incorporates an initial turn-on delay time (TD3) based on the DELAY timer. Prior to the SS voltage reaching the programmed VID DAC voltage and the PWRGD masking time finishing, the PWRGD pin is held low. Once the SS pin is within 50 mV of the programmed DAC voltage, the capacitor on the DELAY pin begins to charge. A comparator monitors the DELAY voltage and enables PWRGD when the voltage reaches 1.7 V. The PWRGD delay time is set, therefore, by a current of IREF charging a capacitor from 0 V to 1.7 V.
THERMAL MONITORING
The ADP3196 includes a thermal monitoring circuit to detect when a point on the VR has exceeded two different userdefined temperatures. The thermal monitoring circuit requires an NTC thermistor to be placed between TTSENSE and GND. A fixed current of 8 x IREF (normally giving 123 A) is sourced out of the TTSENSE pin and into the thermistor. The current source is internally limited to 5 V. An internal circuit compares the TTSENSE voltage to a 1.105 V and a 0.81 V threshold and outputs an open-drain signal at the VRM_OFF and VRMHOT outputs, respectively. The VRM_HOT open-drain output goes high once the voltage on the TTSENSE pin goes below the VRM_HOT thresholds and signals the system that an overtemperature event has occurred. The VRM_OFF output asserts when the voltage on the TTSENSE pin exceeds the VRM_OFF threshold. Because the TTSENSE voltage changes slowly with respect to time, 50 mV of hysteresis is built into these comparators. The thermal monitoring circuitry does not depend on EN and is active when UVLO is above its threshold. When UVLO is below its threshold, VRFAN and VRHOT are forced low.
OUTPUT CROWBAR
To protect the load and output components of the supply, the PWM outputs are driven low which turns on the low-side MOSFETs when the output voltage exceeds the upper crowbar threshold.
Rev. 1 | Page 14 of 18 | www.onsemi.com
ADP3196
Table 4. VID Codes
OUTPUT 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 0.775 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Rev. 1 | Page 15 of 18 | www.onsemi.com
ADP3196
L1 370nH 18A VIN 12V + C11 U2 ADP3120A 10nF D2 1N4148
1 2 3
2700F/16V/3.3Ax2 SANYO MV-WX SERIES + C12 4.7F Q1 IPD09N03L 560F/4V x 7 L2 280nH/1.4m SANYO SEPC SERIES 5m EACH
R4 2.2
C9 18nF
VIN RTN C1
BST DRVH
8 7 6
C2
IN SW PGND OD
102 + +
C25 C32
VCC(CORE) 0.375V TO 1.55V 100A TDC VCC(CORE) RTN 10F x 8 MLCC
4
C10 4.7F R5 2.2 Q2 IPD09N03L C13 18nF Q3 IPD09N03L
VCC DRVL
5
12V 1k
2
U3 C15 ADP3120A 10nF
C16 4.7F Q4 IPD09N03L
VCC(SENSE) VSS(SENSE)
D3 1N4148
1
BST
8 7 6 5
DRVH SW PGND DRVL
IN
L3 280nH/1.4m 102
680
3 4
680
OD
VCC
1F C3 100F (C3 OPTIONAL) C14 4.7F R6 2.2 C17 18nF Q5 IPD09N03L + C4 1F
R2 169k 1%
Q6 IPD09N03L
FROM CPU
C5 1nF
40 1
VTT I/O
NC VID0 VID1 VID2 VID3 VID4 VID5 NC NC VCC
C19 U4 ADP3120A 10nF D4 1N4148
1 2 3
C20 4.7F
8
POWER GOOD VRM_OFF VRMHOT
BST IN U1
DRVH SW PGND
Q7 IPD09N03L
7 6
L4 280nH/1.4m 102
CB 630pF
CFB 16pF
ADP3196
RSW1 1 RSW21 RSW3 1 RSW41 RPH4 140k 1% CCS2 1nF 5% NPO RPH3 RCS1 RCS2 35.7k 88.7k 140k 1% RPH1 140k 1% RPH2 140k 1% C18 4.7F
4
OD
VCC
RB 2k
CA 630pF
RA 18.7k
CSS 10nF
06371-010
Figure 11.Typical 4-Phase Application Circuit
ILIMIT RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD IREF
C6 0.1F RLIM 160k 1% CCS1 1nF 5% NPO RIREF 100k
EN PWRGD FBRTN FB COMP SS DELAY VRM_OFF VRMHOT TTSENSE PWM1 PWM2 PWM3 PWM4 NC SW1 SW2 SW3 SW4 IMON
DRVL
5
Rev. 1 | Page 16 of 18 | www.onsemi.com
R7 2.2 C21 18nF C23 U5 ADP3120A 10nF D5 1N4148
1 2
CDLY 18nF
Q8 IPD09N03L
Q9 IPD09N03L
RTH1 100k, 5% NTC
C24 4.7F
BST IN
3 4
RT 130k 1% C7 1nF
DRVH SW
8 7
Q10 IPD09N03L
L5 280nH/1.4m
102
OD
VCC
PGND DRVL
6 5
C22 4.7F
Q11 IPD09N03L
Q12 IPD09N03L
RTH2 100k, 5% NTC
C8 1nF
R3 1
1
FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION.
2
CONNECT NEAR EACH INDUCTOR.
ADP3196
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal performance of a switching regulator in a PC system. switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system and noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. When a power dissipating component, for example, a power MOSFET, is soldered to a PCB, it is recommended to liberally use the vias, both directly on the mounting pad and immediately surrounding it. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation in the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components.
General Recommendations
For good results, a PCB with at least four layers is recommended. This provides the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1-ounce copper trace has a resistance of ~0.53 m at room temperature. Whenever high currents must be routed between PCB layers, use vias liberally to create several parallel current paths, so the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3196) must cross through power circuitry, it is best to interpose a signal ground plane between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3196 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing into it. The components around the ADP3196 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB pin and CSSUM pin. The output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop (described in the Power Circuitry Recommendations section).
Signal Circuitry Recommendations
The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB trace and FBRTN trace should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller.
Power Circuitry Recommendations
The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated
Rev. 1 | Page 17 of 18 | www.onsemi.com
ADP3196 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX 0.60 MAX
31 30 40 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BCS SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOTTOM VIEW)
4.25 4.10 SQ 3.95
10 11
21 20
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 12. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40) Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP3196JCPZ-RL1
1
Temperature Range
0C to 85C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package Option
CP-40
Ordering Qty
2,500
Z= Pb-free part.
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any ON Semiconductor and products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
Rev. 1 | Page 18 of 18 | www.onsemi.com

▲Up To Search▲

Price & Availability of ADP3196

	To Download ADP3196 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .