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EL5411T
Data Sheet October 8, 2009 FN6837.1
60MHz Rail-to-Rail Input-Output Operational Amplifier
The EL5411T is a high voltage rail-to-rail input-output amplifier with low power consumption. The EL5411T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. The maximum operating voltage range is from 4.5V to 19V. It can be configured for single or dual supply operation, and typically consumes only 3mA per amplifier. The EL5411T has an output short circuit capability of 300mA and a continuous output current capability of 70mA. The EL5411T features a high slew rate of 100V/s, and fast settling time. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 60MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage. These features make the EL5411T an ideal amplifier solution for use in TFT-LCD panels as a VCOM driver or static gamma buffer, and in high speed filtering and signal conditioning applications. Other applications include battery power and portable devices, especially where low power consumption is important. The EL5411T is available in a 14 Ld HTSSOP and a space saving thermally enhanced 16 Ld 4mmx4mm TQFN package. The device operates over an ambient temperature range of -40C to +85C.
Features
* 60MHz (-3dB) Bandwidth * 4.5V to 19V Maximum Supply Voltage Range * 100V/s Slew Rate * 3mA Supply Current (per Amplifier) * 70mA Continuous Output Current * 300mA Output Short Circuit Current * Unity-gain Stable * Beyond the Rails Input Capability * Rail-to-rail Output Swing * Built-in Thermal Protection * -40C to +85C Ambient Temperature Range * Pb-Free (RoHS Compliant)
Applications
* TFT-LCD Panels * VCOM Amplifiers * Static Gamma Buffers * Drivers for A/D Converters * Data Acquisition * Video Processing * Audio Processing
Ordering Information
PART NUMBER (Note) EL5411TIREZ EL5411TIREZ-T7* EL5411TIREZ-T13* EL5411TILZ EL5411TILZ-T7* EL5411TILZ-T13* PART MARKING 5411TIRE Z 5411TIRE Z 5411TIRE Z 5411TIL Z 5411TIL Z 5411TIL Z PACKAGE (Pb-Free) PKG. DWG. #
* Active Filters * Test Equipment * Battery-powered Applications * Portable Equipment
14 Ld HTSSOP M14.173A 14 Ld HTSSOP M14.173A Tape and Reel 14 Ld HTSSOP M14.173A Tape and Reel 16 Ld TQFN L16.4x4F
16 Ld TQFN L16.4x4F Tape and Reel 16 Ld TQFN L16.4x4F Tape and Reel
*Please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5411T Pinouts
EL5411T (16 LD 4X4 TQFN) TOP VIEW
14 VOUTD 15 VOUTA 16 NC 13 NC
EL5411T (14 LD HTSSOP) TOP VIEW
VOUTA 1 VINA- 2 12 VINDVINA+ 3 VS+ 4 VINB+ 5 VINB- 6 VOUTB 7 + + + + 14 VOUTD 13 VIND12 VIND+ 11 VS10 VINC+ 9 VINC8 VOUTC
VINA- 1 VINA+ 2 VS+ 3 VINB+ 4 VINB- 5 VOUTB 6 VOUTC 7 VINC- 8 THERMAL PAD
11 VIND+ 10 VS9 VINC+
THERMAL PAD CONNECTS TO VS-
THERMAL PAD CONNECTS TO VS-
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FN6837.1 October 8, 2009
EL5411T
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . +19.8V Input Voltage Range (VINx+, VINx-) . . . . . . . . VS- - 0.5V, VS+ + 0.5V Input Differential Voltage (VINx+ - VINx-) . .(VS+ + 0.5V)-(VS- - 0.5V) Maximum Continuous Output Current . . . . . . . . . . . . . . . . . 70mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3000V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) 14 Ld HTSSOP . . . . . . . . . . . . . . . . 38 16 Ld TQFN . . . . . . . . . . . . . . . . . . . 40 JC (C/W) 8 9
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . .See Figures 32 and 33 Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS
VS+ = +5V, VS- = -5V, RL = 1k to 0V, TA = +25C, Unless Otherwise Specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift (Note 3)
VCM = 0V 14 LD HTSSOP package 16 LD TQFN package
3.5 26 4 2 1 2 -5.5
17
mV V/C V/C
IB RIN CIN CMIR CMRR AVOL
Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain
VCM = 0V
60
nA G pF
+5.5 73 78
V dB dB
For VIN from -5.5V to 5.5V -4.5V VOUTx 4.5V
50 62
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short-Circuit Current Output Current IL = -5mA IL = +5mA VCM = 0V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ 4.85 -4.94 4.94 300 70 -4.85 V V mA mA
POWER SUPPLY PERFORMANCE (VS+) - (VS-) IS PSRR Supply Voltage Range Supply Current Power Supply Rejection Ratio VCM = 0V, No load Supply is moved from 2.25V to 9.5V 60 4.5 11 75 19 15 V mA dB
DYNAMIC PERFORMANCE SR tS BW GBWP Slew Rate (Note 4) Settling to +0.1% (Note 5) -3dB Bandwidth Gain-Bandwidth Product -4.0V VOUTx 4.0V, 20% to 80% AV = +1, VOUTx = 2V step, RL = 1k || 1k (probe), CL = 1.5pF RF = 1k, CL = 1.5pF AV = -10, RF = 1k, RG = 100 RL = 1k || 1k (probe), CL = 1.5pF 100 85 60 32 V/s ns MHz MHz
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FN6837.1 October 8, 2009
EL5411T
Electrical Specifications
PARAMETER PM CS Phase Margin Channel Separation VS+ = +5V, VS- = -5V, RL = 1k to 0V, TA = +25C, Unless Otherwise Specified. (Continued) CONDITIONS AV = -10, RF = 1k, RG = 100 RL = 1k || 1k (probe), CL = 1.5pF f = 5MHz MIN TYP 50 90 MAX UNIT dB
DESCRIPTION
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS
VS+ = +5V, VS- = 0V, RL = 1k to 2.5V, TA = +25C, Unless Otherwise Specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift (Note 3)
VCM = 2.5V 14 LD HTSSOP package 16 LD TQFN package
3.5 23 3 2 1 2 -0.5
17
mV V/C V/C
IB RIN CIN CMIR CMRR AVOL
Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain
VCM = 2.5V
60
nA G pF
+5.5 68 82
V dB dB
For VIN from -0.5V to 5.5V 0.5V VOUTx 4.5V
45 62
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short-circuit Current Output Current IL = -4.2mA IL = +4.2mA VCM = 2.5V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ 4.85 60 4.94 110 70 150 mV V mA mA
POWER SUPPLY PERFORMANCE (VS+) - (VS-) IS PSRR Supply Voltage Range Supply Current Power Supply Rejection Ratio VCM = 2.5V, No load Supply is moved from 4.5V to 19V 60 4.5 12 75 19 15 V mA dB
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS Slew Rate (Note 4) Settling to +0.1% (Note 5) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation 1V VOUTx 4V, 20% to 80% AV = +1, VOUTx = 2V step, RL = 1k || 1k (probe), CL = 1.5pF RF = 1k, CL = 1.5pF AV = -10, RF = 1k, RG = 100 RL = 1k || 1k (probe), CL = 1.5pF AV = -10, RF = 1k, RG = 100 RL = 1k || 1k (probe), CL = 1.5pF f = 5MHz 75 90 60 32 50 90 V/s ns MHz MHz dB
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FN6837.1 October 8, 2009
EL5411T
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS Input Offset Voltage Average Offset Voltage Drift (Note 3) VCM = 9V 14 LD HTSSOP package 16 LD TQFN package IB RIN CIN CMIR CMRR AVOL Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain For VIN from -0.5V to 18.5V 0.5V VOUTx 17.5V -0.5 53 62 75 104 VCM = 9V 3.5 21 5 2 1 2 +18.5 60 17 mV V/C V/C nA G pF V dB dB VS+ = +18V, VS- = 0V, RL = 1k to 9V, TA = +25C, Unless Otherwise Specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short-circuit Current Output Current IL = -6mA IL = +6mA VCM = 9V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ 17.85 80 17.92 300 70 150 mV V mA mA
POWER SUPPLY PERFORMANCE (VS+) - (VS-) IS PSRR Supply Voltage Range Supply Current Power Supply Rejection Ratio VCM = 9V, No load Supply is moved from 4.5V to 19V 60 4.5 12.3 75 19 15 V mA dB
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS NOTES: 3. Measured over -40C to +85C ambient operating temperature range. See the typical TCVOS production distribution shown in the "Typical Performance Curves" on page 6. 4. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of the output signal. 5. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within a 0.1% error band. The range of the error band is determined by: Final Value(V)[Full Scale(V)*0.1%]. Slew Rate (Note 4) Settling to +0.1% (Note 5) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation 1V VOUTx 17V, 20% to 80% AV = +1, VOUTx = 2V step, RL = 1k || 1k (probe), CL = 1.5pF RF = 1k, CL = 1.5pF AV = -10, RF = 1k, RG = 100 RL = 1k || 1k (probe), CL = 1.5pF AV = -10, RF = 1k, RG = 100 RL = 1k || 1k (probe), CL = 1.5pF f = 5MHz 100 100 60 32 50 90 V/s ns MHz MHz dB
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FN6837.1 October 8, 2009
EL5411T Typical Performance Curves
900 800 QUANTITY (AMPLIFIERS) 700 600 500 400 300 200 100 0 -15 -13 -11 -9 -7 -5 -3 -1 1 3 5 7 9 11 13 15 VS = 5V TA = +25C 16 QUANTITY (AMPLIFIERS) TYPICAL PRODUCTION DISTRIBUTION 14 12 10 8 6 4 2 0 3 9 15 21 27 33 39 45 51 57 VS = 5V -40C to +85C TYPICAL PRODUCTION DISTRIBUTION
INPUT OFFSET VOLTAGE (mV)
INPUT OFFSET VOLTAGE DRIFT (V/C)
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT (HTSSOP)
0.0 25 INPUT OFFSET VOLTAGE (mV) VS = 5V -40C to +85C QUANTITY (AMPLIFIERS) 20 TYPICAL PRODUCTION DISTRIBUTION -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -50 VS = 5V
15
10
5
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INPUT OFFSET VOLTAGE DRIFT (V/C)
0
50 TEMPERATURE (C)
100
150
FIGURE 3. INPUT OFFSET VOLTAGE DRIFT (TQFN)
FIGURE 4. INPUT OFFSET VOLTAGE vs TEMPERATURE
8.0 VS = 5V OUTPUT HIGH VOLTAGE (V) INPUT BIAS CURRENT (nA) 7.5
4.96 VS = 5V IOUT = +5mA 4.94
7.0
4.92
6.5
4.90
6.0 -50
0
50 TEMPERATURE (C)
100
150
4.88 -50
0
50 TEMPERATURE (C)
100
150
FIGURE 5. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 6. OUTPUT HIGH VOLTAGE vs TEMPERATURE
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FN6837.1 October 8, 2009
EL5411T Typical Performance Curves (Continued)
-4.90 OUTPUT LOW VOLTAGE (V) -4.91 -4.92 -4.93 -4.94 -4.95 -4.96 -50 VS = 5V IOUT = -5mA OPEN LOOP GAIN (dB) 100 120 VS = 5V RL = 1k
80
60
40
0
50 TEMPERATURE (C)
100
150
20 -50
0
50 TEMPERATURE (C)
100
150
FIGURE 7. OUTPUT LOW VOLTAGE vs TEMPERATURE
FIGURE 8. OPEN-LOOP GAIN vs TEMPERATURE
130 120 SLEW RATE (V/s) 110 100 90 80 70 60 -50 VS = 5V RL = 1k SUPPLY CURRENT (mA)
2.85 VS = 5V NO LOAD INPUTS AT GND 2.80
2.75
2.70
0
50 TEMPERATURE (C)
100
150
2.65 -50
0
50 TEMPERATURE (C)
100
150
FIGURE 9. SLEW RATE vs TEMPERATURE
FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE
4.0 TA = +25C NO LOAD INPUTS AT GND SLEW RATE (V/s) 3.5
140 TA = +25C AV = 1 RL = 1k CL = 8pF
SUPPLY CURRENT (mA)
120
100
3.0
80
2.5
60
2.0 2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
40
2
4
6 SUPPLY VOLTAGE (V)
8
10
SUPPLY VOLTAGE (V)
FIGURE 11. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE
FIGURE 12. SLEW RATE vs SUPPLY VOLTAGE
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FN6837.1 October 8, 2009
EL5411T Typical Performance Curves (Continued)
140 TA = +25C RL = 1k OPEN LOOP GAIN (dB) 120 OPEN LOOP GAIN (dB) 100 80 60 40 20 0 -20 10 VS = 5V RF = 5k, RG = 100 RL = 1k CL = 8pF 100 1k 10k 100k 1M 10M GAIN PHASE () PHASE 120 80 40 0 -40 100M 200 160
100
80
60
40 2 4 6 SUPPLY VOLTAGE (V) 8 10
FREQUENCY (Hz)
FIGURE 13. OPEN LOOP GAIN vs SUPPLY VOLTAGE
FIGURE 14. OPEN LOOP GAIN AND PHASE vs FREQUENCY
10 100 PHASE OPEN LOOP GAIN (dB) 80 60 40 20 0 -20 10 VS = 5V RF = 1k, RG = 100 RL = 1k || 1k (PROBE) CL = 1.5pF 100 1k 10k 100k 1M 10M GAIN 160 120 PHASE () 80 40 0 -40 100M 200 8 6 4 GAIN (dB) 1k 2 0 -2 -4 -6 -8 -10 100k 1M 150 560 VS = 5V AV = 1 CL = 1.5pF RL || 1k (probe)
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS RL
20 15 10 GAIN (dB) 5 0 -5 -10 -15 -20 100k VS = 5V AV = 1 RL = 1k
450 OUTPUT IMPEDANCE () 1000pF 400 100pF 47pF 10pF 350 300 250 200 150 100 50 0 10k 100k 1M FREQUENCY (Hz) 10M 100M VS = 5V AV = 1 RL = OPEN VOUTx = +15dBm
1M 10M FREQUENCY (Hz)
100M
FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 18. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY
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FN6837.1 October 8, 2009
EL5411T Typical Performance Curves (Continued)
12 MAXIMUM OUTPUT SWING (VP-P) 10 8 6 4 2 VS = 5V AV = 1 RL = 1k DISTORTION <1% 100k 1M FREQUENCY (Hz) 10M 100M DISTORTION (dBc) -30 -40 -50 -60 -70 -80 -90 0 2 4 6 8 10 OUTPUT VOLTAGE (VOP-P)
2nd HD
3rd HD VS = 5V AV = 2 RL = 1k fIN= 1MHz
0 10k
FIGURE 19. MAXIMUM OUTPUT SWING vs FREQUENCY
FIGURE 20. HARMONIC DISTORTION vs VOP-P
0 -10 -20 CMRR (dB) -30 -40 -50 -60 -70 -80 -90 1k 10k 100k 1M 10M 100M PSRR (dB) VS = 5V TA = +25C VINx = -10dBm
0 -10 -20 -30 -40 -50 -60 PSRR+ -70 -80 -90 1k PSRR10k 100k 1M 10M 100M VS = 5V TA = +25C
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 21. CMRR vs FREQUENCY
FIGURE 22. PSRR vs FREQUENCY
1000 TA = +25C VOLTAGE NOISE (nV/Hz)
-20 -40 MEASURED CH A TO D, OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION
100 XTALK(dB)
-60 -80 -100 -120 VS = 5V AV = 1 VINx = 0dBm 100k 1M FREQUENCY (Hz) 10M 100M
10
1 100
1k
10k
100k
1M
10M
100M
-140 10k
FREQUENCY (Hz)
FIGURE 23. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY
FIGURE 24. CHANNEL SEPARATION vs FREQUENCY
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FN6837.1 October 8, 2009
EL5411T Typical Performance Curves (Continued)
100 VS = 5V TA = +25C AV = 1 RL = 1k VINx = 50mV 5 4 3 STEP SIZE (V) 2 1 0 -1 -2 -3 -4 0 10 100 LOAD CAPACITANCE (pF) 1k -5 70 80 SETTLING TIME (ns) 90 VS = 5V TA = +25C AV = 1 RL= 1k || 1k (PROBE) CL =1.5pF
80 OVERSHOOT (%)
60
40
20
FIGURE 25. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
FIGURE 26. STEP SIZE vs SETTLING TIME
6V STEP
VS = 5V TA = +25C AV = 1 RL= 1k || 1k (PROBE) CL = 1.5pF 50ns/DIV
50mV/DIV
VS = 5V TA = +25C AV = 1 RL= 1k || 1k (PROBE) CL = 1.5pF
1V/DIV
100mV STEP
50ns/DIV
FIGURE 27. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 28. SMALL SIGNAL TRANSIENT RESPONSE
EL5411T (14 LD HTSSOP shown)
VOUTA CLA
1 RLA 0 2 3 49.9 VS+ 4.7F + 4 0.1F 5 49.9 0 6
VOUTA
VOUTD
14 0 RLD CLD
VOUTD
VINA-
VIND-
13 12 49.9
VINA+
VINA+
VIND+
VIND+ VS+ 4.7F VINC+ 49.9 0
Vs+
Vs-
11 0.1F 10 9 8
VINB+
VINC+
VINB+
VINB-
VINC-
VOUTB CLB RLB
7
VOUTB
VOUTC
RLC
VOUTC CLC
THERMAL PAD CONNECTED TO VS-
FIGURE 29. BASIC TEST CIRCUIT
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FN6837.1 October 8, 2009
EL5411T Pin Descriptions
EL5411T EL5411T (14 LD HTSSOP) (16 LD TQFN) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 14 13, 16 pad pad PIN NAME VOUTA VINAVINA+ VS+ VINB+ VINBVOUTB VOUTC VINCVINC+ VSVIND+ VINDVOUTD NC Thermal Pad FUNCTION Amplifier A output Amplifier A inverting input Amplifier A non-inverting input Positive power supply Amplifier B non-inverting input Amplifier B inverting input Amplifier B output Amplifier C output Amplifier C inverting input Amplifier C non-inverting input Negative power supply (connects to GND for single supply operation) Amplifier D non-inverting input Amplifier D inverting input Amplifier D output Not connected Functions as a heat sink. Connects to most negative potential, VS(Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1) (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1) (Reference Circuit 1) (Reference Circuit 2) (Reference Circuit 2) EQUIVALENT CIRCUIT (Reference Circuit 1) (Reference Circuit 2) (Reference Circuit 2)
VS+
VS+
VOUTx VINx VSVS-
GND
CIRCUIT 1
CIRCUIT 2
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FN6837.1 October 8, 2009
EL5411T Applications Information
Product Description
The EL5411T is a high voltage rail-to-rail input-output amplifier with low power consumption. The EL5411T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. The EL5411T features a high slew rate of 100V/s, and fast settling time. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 60MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage.
1V/DIV VS = 2.5V, TA = +25C, AV = 1, VINx = 6VP-P, RL = 1k to GND
OUTPUT
INPUT 10s/DIV
FIGURE 30. OPERATION WITH BEYOND-THE-RAILS INPUT
Operating Voltage, Input and Output Capability
The EL5411T can operate on a single supply or dual supply configuration. The EL5411T operating voltage ranges from a minimum of 4.5V to a maximum of 19V. This range allows for a standard 5V (or 2.5V) supply voltage to dip to -10%, or a standard 18V (or 9V) to rise by +5.5% without affecting performance or reliability. The input common-mode voltage range of the EL5411T extends 500mV beyond the supply rails. Also, the EL5411T is immune to phase reversal. However, if the common mode input voltage exceeds the supply voltage by more than 0.5V, electrostatic protection diodes in the input stage of the device begin to conduct. Even though phase reversal will not occur, to maintain optimal reliability it is suggested to avoid input overvoltage conditions. Figure 30 shows the input voltage driven 500mV beyond the supply rails and the device output swinging between the supply rails. The EL5411T output typically swings to within 50mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 31 shows the input and output waveforms for the device in a unity-gain configuration. Operation is from 5V supply with a 1k load connected to GND. The input is a 10VP-P sinusoid and the output voltage is approximately 9.9VP-P. Refer to the "Electrical Specifications" Table beginning on page 3 for specific device parameters. Parameter variations with operating voltage, loading and/or temperature are shown in the "Typical Performance Curves" on page 6.
5V/DIV VS = 5V, TA = +25C, AV = 1, VINx = 10VP-P, RL = 1k to GND
10s/DIV
FIGURE 31. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT
Output Current
The EL5411T is capable of output short circuit currents of 300mA (source and sink), and the device has built-in protection circuitry which limits the short circuit current to 300mA (typical). To maintain maximum reliability, the continuous output current should never exceed 70mA. This 70mA limit is determined by the characteristics of the internal metal interconnects. Also, see "Power Dissipation" on page 13 for detailed information on ensuring proper device operation and reliability for temperature and load conditions.
Unused Amplifiers
It is recommended that any unused amplifiers be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground.
Driving Capacitive Loads
As load capacitance increases, the -3dB bandwidth will decrease and peaking can occur. Depending on the application, it may be necessary to reduce peaking and to improve device stability. To improve device stability a snubber circuit or a series resistor may be added to the output of the EL5411T.
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FN6837.1 October 8, 2009
OUTPUT
INPUT
EL5411T
A snubber is a shunt load consisting of a resistor in series with a capacitor. An optimized snubber can improve the phase margin and the stability of the EL5411T. The advantage of a snubber circuit is that it does not draw any DC load current or reduce the gain. Another method to reduce peaking is to add a series output resistor (typically between 1 to 10). Depending on the capacitive loading, a small value resistor may be the most appropriate choice to minimize any reduction in gain. Device overheating can be avoided by calculating the minimum resistive load condition, RLOAD, resulting in the highest power dissipation. To find RLOAD set the two PDMAX equations equal to each other and solve for VOUT/ILOAD. Reference the package power dissipation curves, Figures 32 and 33, for further information.
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 POWER DISSIPATION (W) 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 962mW TQFN16 JA = +130C/W
Power Dissipation
With the high-output drive capability of the EL5411T amplifiers, it is possible to exceed the +150C absolute maximum junction temperature under certain load current conditions. It is important to calculate the maximum power dissipation of the EL5411T in the application. Proper load conditions will ensure that the EL5411T junction temperature stays within a safe operating region. The maximum power dissipation allowed in a package is determined according to Equation 1:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA (EQ. 1)
893mW
HTSSOP14 JA = +140C/W
FIGURE 32. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package
POWER DISSIPATION (W) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 TQFN16 JA = +40C/W 3.29W HTSSOP14 JA = +38C/W JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD - EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
* PDMAX = Maximum power dissipation allowed The total power dissipation produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power dissipation in the IC due to the loads, or:
P DMAX = i [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ] (EQ. 2)
3.13W
when sourcing, and:
P DMAX = i [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ] (EQ. 3)
0.0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
when sinking, where: * i = 1 to 4 (1, 2, 3, 4 corresponds to Channel A, B, C, D respectively) * VS = Total supply voltage (VS+ - VS-) * VS+ = Positive supply voltage * VS- = Negative supply voltage * ISMAX = Maximum supply current per amplifier (ISMAX = EL5411T quiescent current / 4) * VOUT = Output voltage * ILOAD = Load current 13
FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Thermal Shutdown
The EL5411T has a built-in thermal protection which ensures safe operation and prevents internal damage to the device due to overheating. When the die temperature reaches +165C (typical) the device automatically shuts OFF the outputs by putting them in a high impedance state. When the die cools by +15C (typical) the device automatically turns ON the outputs by putting them in a low impedance (normal) operating state.
FN6837.1 October 8, 2009
EL5411T
Power Supply Bypassing and Printed Circuit Board Layout
The EL5411T can provide gain at high frequency, so good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, trace lengths should be as short as possible and the power supply pins must be well bypassed to reduce any risk of oscillation. For normal single supply operation (the VS- pin is connected to ground) a 4.7F capacitor should be placed from VS+ to ground, then a parallel 0.1F capacitor should be connected as close to the amplifier as possible. One 4.7F capacitor may be used for multiple devices. For dual supply operation the same capacitor combination should be placed at each supply pin to ground. It is highly recommended that EL5411T exposed thermal pad packages should always have the pad connected to the lowest potential, VS-, to optimize thermal and operating performance. PCB vias should be placed below the device's exposed thermal pad to transfer heat to the VS- plane and away from the device.
Revision History
DATE 10/8/09 REVISION FN6837.1 CHANGE Updated Ordering Information by removing "contact factory for availability". add "vs FREQUENCY" to the plot titles in Fig 14,15,18,21,22,23,24: Fig 21: changed y-axis label to read "CMRR (dB)" Fig 22: changed y-axis label to read "PSRR (dB)" Fig 26: changed label to read "STEP SIZE vs SETTLING TIME" Changed 1st sentence in pages 1 and 12 from "The EL5411T is a low power, high voltage railto-rail input-output amplifier" to "The EL5411T is a high voltage rail-to-rail input-output amplifier with low power consumption". Updated package outline drawing M14.173A to add land pattern and move dimensions from table onto drawing Initial Release.
8/21/09
FN6837.0
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6837.1 October 8, 2009
EL5411T
Package Outline Drawing
L16.4x4F
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 04/09
4X 1.95 4.00 A B 6 PIN 1 INDEX AREA 13 12X 0.65 16 6 PIN #1 INDEX AREA
12
1
4.00
2 . 70 0 . 05
9
4
(4X)
0.15 8 16X 0 . 4 0 . 05 TOP VIEW BOTTOM VIEW 5 0.10 M C A B 4 0.30 0 . 05
SEE DETAIL "X" 0.10 C 0 . 75 0 . 05 0.08 C SIDE VIEW ( 3 . 8 TYP ) ( 2 . 70 TYP ) ( 12X 0 . 65 ) C
C ( 16X 0 .30 ) ( 16 X 0 . 6 ) TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
2. 3. 4.
15
FN6837.1 October 8, 2009
EL5411T
Package Outline Drawing
M14.173A
14 LEAD HEAT-SINK THIN SHRINK SMALL OUTLINE PACKAGE (HTSSOP) Rev 1, 9/09
A 1 5.00 0.10 14 8 SEE DETAIL "X" 3 3.20 0.10
6.40 4.40 0.10 2 3 PIN #1 I.D. MARK 3.00 0.10
1 0.20 C B A TOP VIEW 0.65
7 B 0.09-0.20 END VIEW EXPOSED THERMAL PAD BOTTOM VIEW
1.00 REF H C 0.90 +0.15/-0.10 SEATING PLANE 0.25 +0.05/-0.06 0.10 C SIDE VIEW 0.10 CBA 1.20 MAX GAUGE PLANE 5 0.05 MIN 0.15 MAX 0- 8 0.60 0.15 0.25 0.05
DETAIL "X"
NOTES: (1.45) 1. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead (5.65) flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation ABT-1. (0.65 TYP) (0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
16
FN6837.1 October 8, 2009

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