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LVDS Interface ICs
56bit LVDS Receiver 8:56 DeSerializer
BU7985KVT
Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI.
Features Wide dot clock range : Single(112MHz)/Dual(180MHz)(NTSC, VGA, SVGA, WXGA UXGA) Support clock frequency from 20MHz up to 112MHz. User programmable LVCMOS data output triggering timing by using either rising or falling edge of clock. User programmable LVCMOS data and clock output driving ability. Support Fail-Safe Hi-z Operation. 56bit LVDS transmitter is recommended to use BU7988KVT.
Applications Flat Panel Display
Precaution This chip is not designed to protect from radioactivity.
Jun.2008
Block Diagram
LVDS Input
SERIAL TO PARALLEL
LVCMOS Output
RA1+/RB1+/-
+ + + + + -
8 8 28 8
RED1 GREEN1 BLUE1 1st Data
1st Link
RC1+/RD1+/RCLK1+/20 to 112MHz)
HSYNC VSYNC
PLL MUX
DE
RECEIVER CLOCK OUT 20 to 90MHz) D to D 10 to 56MHz) S to D
8 8
RA2+/RB2+/-
SERIAL TO PARALLEL
+ + + + + -
RED2 GREEN2 BLUE2 2nd Data
28
8
2nd Link
RC2+/RD2+/RCLK2+/20 to 90MHz) R/F DRVSEL XRST
PLL
Figure-1
Block Diagram
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TQFP100V
Package Outline and Specification
Product No.
16.00.3 14.00.2 75 76 51 50
BU7985KVT
16.00.3 14.00.2
Lot No.
100 1
1PIN MARK
25
26
1.2MAX 1.00.1 0.10.1
0.20.1
0.5
0.1
Figure-2
TQFP100V Package Outline and Specification
3 / 20
0.5 0.1250.1
Pin configuration
HSYNC
DE VSYNC
B16 GND
GND VDD
VDD B15
G12 G11
G17
G16 G15
G14
G13
G10 R17 53 52
B14 B13
75
74 73
72
71
70
69
68
67
66 65
64
63
62
61
60
59
58 57
56
55
54
LVDS GND RA1RA1+ RB1RB1+ LVDS VDD RC1RC1+ RCLK1 RCLK1+ RD1RD1+ LVDS GND RA2RA2+ RB2RB2+ LVDS VDD RC2RC2+ RCLK2RCLK2+ RD2RD2+ LVDS GND
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
51
R16
B17
B12
B11 B10
100-Pin TQFP (Top View)
20
21
22
23
10
11
12
13
14
15
16 17
18
XRST MODE0
MODE1
R/F DRVSEL
PLL_GND
R25 R26
19
G24
G21
GND
VDD GND
G22
R20
GND
PLL_VDD
Figure-3 Pin Diagram (Top View)
R22 R23
R21
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G20
G23
R24
R27
G25
24 25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
R15 GND VDD R14 R13 R12 R11 R10 GND VDD CLKOUT B27 B26 B25 B24 B23 GND VDD B22 B21 B20 G27 GND VDD G26
1
2
3
4
5
6
7 8
9
Pin Description
Table 1 : Pin Description Pin Name
RA1+, RA1RB1+, RB1RC1+, RC1RD1+, RD1RCLK1+, RCLK1RA2+, RA2RB2+, RB2RC2+, RC2RD2+, RD2RCLK2+, RCLK2R17 R10 G17 G10 B17 B10 R27 R20 G27 G20 B27 B20
Pin No.
78, 77 80, 79 83, 82 87, 86 85, 84 90, 89 92, 91 95, 94 99, 98 97, 96 52, 51, 50, 47, 46, 45, 44, 43 62, 61, 60, 59, 58, 55, 54, 53 72, 71, 68, 67, 66, 65, 64, 63 19, 18, 17, 14, 13, 12, 11, 10 29, 26, 25, 24, 23, 22, 21, 20 39, 38, 37, 36, 35, 32, 31, 30
Type
LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN
Descriptions
LVDS Data Input for 1st Link. The 1st pixel input data when Dual Link. + : Positive input of LVDS data differential pair. - : Negative input of LVDS data differential pair.
LVDS Clock Input for 1st Link.
LVDS Data Input for 2nd Link. These pins are disabled when Single Link. + : Positive input of LVDS data differential pair. - : Negative input of LVDS data differential pair.
LVDS Clock Input for 2nd Link.
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN
Data Enable Output. Vsync Output. Hsync Output. Clock Output. Output Driverbility Select. L: Data output 2mA / Clock output 4mA H: Data output 4mA / Clock output 8mA Output Clock Triggering Edge Select. H: Rising edge, L: Falling edge. Pixel Data Mode. MODE1 MODE0 L L L H H L H H Mode Dual Link Single Link Dual Link With Fail-Safe Hiz Single Link With Fail-Safe Hiz The 2nd Pixel Data Outputs. The 1st Pixel Data Outputs.
DE
VSYNC HSYNC CLKOUT DRVSEL
75 74 73 40 9 8
R/F
MODE1,MODE0
6, 5
IN
5 / 20
Pin Name
XRST VDD
Pin No. 4
15, 27, 33, 41, 48, 56, 69 3, 7, 16, 28, 34, 42, 49, 57, 70 81,93 76, 88, 100
Type IN
Power Ground Power Ground
Descriptions
H: Normal operation, L: Power down (all outputs are pulled to ground) Power Supply Pins for LVCMOS outputs and digital circuitry. Ground Pins for LVCMOS outputs and digital circuitry. Power Supply Pins for LVDS inputs. Ground Pins for LVDS inputs. Power Supply Pin for PLL circuitry. Ground Pin for PLL circuitry.
GND LVDS VDD LVDS GND PLL VDD PLL GND
2 1
Power
Ground
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Electrical characteristics
Rating
Table 2 : Absolute maximum rating Item Supply voltage Input voltage Output voltage Storage temperature range Symbol VDD VIN VOUT Tstg Value Min. -0.3 -0.3 -0.3 -55 Max. 4.0 VDD+0.3 VDD+0.3 125 Unit V V V
Table 3 : Package Power PACKAGE TQFP100V Power Dissipation (mW) 900 1400*2 2550*2 De-rating (mW/) *1 9.0 14.0*2 25.5*2
*1:At temperature Ta >25 *2:Package power when mounting on the PCB board. The size of PCB board :70x70x1.6mm3 / 140x150x1.6mm3 The material of PCB board : The FR4 glass epoxy board.(3% or less copper foil area) (It is recommended to apply the above package power requirement to PCB board when the small swing input mode is used)
Table 4 : Recommended Operating Conditions Parameter Supply Voltage Operating Temperature Range Symbol Min VDD Topr 3.0 -20 Rating Typ 3.3 Max 3.6 85 V VDD,LVDSVDD,PLLVDD Units Conditions
7 / 20
DC characteristics
Table 5 : LVCMOS DC SpecificationsVDD=3.0V3.6V, Ta=-20+85 Rating Symbol Parameter Units Min Typ Max VIH VIL VOH VOL IINC IOZ
High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage
Conditions
VDDx0.8 GND 2.4 0.0 -10 -10
-
VDD VDDx0.2 VDD 0.4 +10 +10
V V V V A A IOH = -2mA, -4mA (data) IOH = -4mA, -8mA (clock) IOL = 2mA, 4mA (data) IOL = 4mA, 8mA (clock) 0VVINVDD Output=Hiz, 0VVOUTVDD
Input Leak Current Output Leak Current
Table 6 : LVDS Receiver DC SpecificationsVDD=3.0V3.6V, Ta=-20+85 Rating Symbol Parameter Units Min Typ Max VTH VTL IINL
Differential Input High Threshold Differential Input Low Threshold Input Current
Conditions VOC=1.2V VOC=1.2V VIN=2.4V/0V VDD=3.6
-100 -20
-
100 +20
mV mV A
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Supply Current
Table 7 : Supply CurrentVDD=3.3V, Ta=25 Rating Parameter Symbol Min Typ Receiver supply current (Gray scale pattern) 88 62
Max
Units
Conditions
-
mA mA
MODE[1:0]=L L, H L CL=8pF MODE[1:0]=L H, H H CL=8pF MODE[1:0]=L L, H L CL=8pF MODE[1:0]=L H, H H CL=8pF XRST=L
f=90MHz f=112MHz
IRCCG
IRCCW
Receiver supply current (Checker pattern)
Receiver Power Down Supply Current
-
137 89 -
10
mA mA A
f=90MHz f=112MHz
IRCCS
9 / 20
256 Gray Scale Pattern
CLKOUT Rx0/Gx0/Bx0 Rx1/Gx1/Bx1 Rx2/Gx2/Bx2 Rx3/Gx3/Bx3 Rx4/Gx4/Bx4 Rx5/Gx5/Bx5 Rx6/Gx6/Bx6 Rx7/Gx7/Bx7 =1,2 DE
Figure-4 Gray scale pattern
Double Checker Pattern
CLKOUT R1/G1/B1 R2/G2/B2 n =07 DE
Figure-5 Checker pattern
10 / 20
AC characteristics
Table 8 : Switching CharacteristicsVDD=3.0V3.6V, Ta=-20+85
Symbol Parameter
Dual-in / Dual-out CLK OUT Period
Min
Typ
Max
Units
11.11 17.85 0.3tRCP 0.3tRCP -0.25
tRCP tRCH RCL RS RH tTLH tTHL RIP1 RIP0 RIP6 RIP5 RIP4 tTOP3 RIP2 tRRLL
tRCIP
tRCIP 2tRCIP 0.5tRCP 0.5tRCP 3.0 3.0 0.0
50 100 5.0 5.0 +0.25
ns
Single-in / Dual-out
CLKOUT High Time CLKOUT Low Time LVCMOS Data Setup to CLKOUT LVCMOS data hold from CLKOUT LVCMOS Low to High Transition Time LVCMOS Low to Low Transition Time Input Data Position0 (TRCIP = 8.9ns) Input Data Position1 (TRCIP = 8.9ns) Input Data Position2 (TRCIP = 8.9ns) Input Data Position3 (TRCIP = 8.9ns) Input Data Position4 (TRCIP = 8.9ns) Input Data Position5 (TRCIP = 8.9ns) Input Data Position6 (TRCIP = 8.9ns) Phase Lock Loop Set CLKIN Period Skew Time between RCLK1 and RCLK2
ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns
tRCIP -0.25 7 tRCIP 2 -0.25 7 tRCIP 3 -0.25 7 tRCIP 4 -0.25 7 tRCIP 5 -0.25 7 tRCIP 6 -0.25 7
8.9 -
tRCIP 7 tRCIP 2 7 tRCIP 3 7 tRCIP 4 7 tRCIP 5 7 tRCIP 6 7
-
tRCIP +0.25 7 tTCOP 2 +0.25 7 tRCIP 3 +0.25 7 tRCIP 4 +0.25 7 tRCIP 5 +0.25 7 tRCIP 6 +0.25 7
2 10.0 50 0.3tRCIP
12
11 / 20
AC Timing
LVCMOS
80%
LVCMOS Output 8pF
80%
20%
20%
LVCMOS Output Load
t TLH
t THL
tRCH
tRCL VDD/2
R/F=L VDD/2 R/F=H
CLKOUT
VDD/2
VDD/2
tRCP
tRS
tRH VDD/2
Rxn
VDD/2
X=A,B,C,D n=0,1,2,3,4,5,6
Figure-6 LVCMOS output timing
Phase-locked loops set time
3.0V
VDD
RCLK +/-
PD
VDD/2
tRPLL
VDD/2
CLKOUT
Figure-7 Phase-locked loops set time
12 / 20
AC Timing Diagrams
Previous cycle Current cycle Next cycle
tRCIP RCLK1 + (Differential) Vdiff=0V Vdiff=0V
RA1+/-
RA3
RA2
RA1
RA0
RA6
RA5
RA4
RA3
RA2
RA1
RA0
RA6
RB1+/-
RB3
RB2
RB1
RB0
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RB6
RC1+/-
RC3
RC2
RC1
RC0
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RC6
RD1+/-
RD3
RD2
RD1
RD0
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RD6
tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 Figure-7 AC Timing Diagrams
Figure-8 LVDS data and clock input timing
RCLK1 + (Differential)
Vdiff = 0V CK12
RCLK2 + (Differential)
Vdiff = 0V
Note : Vdiff=(Ryx+)(Ryx), (RCLKx+)(RCLKx),
13 / 20
LVDS Data, Clock Input and Output Timing
LVDS Input
RA1+/ RB1+/ RC1+/ RD1+/
RA6
RA5
RA4
RA3
RA2
RA1
RA0
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RCLK1+/-
LVCMOS Output
CLKOUT (R/F=L) CLKOUT (R/F=H) RA06 VALID VALID VALID VALID VALID VALID VALID
RB06 RC06 RD06
,
VALID
Figure-9 LVDS Data, Clock Input and Output Timing
14 / 20
Pixel Map Table for Dual Link
Table 9: Pixel Map 1st Pixel Data TFT Panel Data BU7985KVT LVCMOS Output 24Bit 18Bit Pin R10 R10 R11 R11 R12 R10 R12 R13 R11 R13 R14 R12 R14 R15 R13 R15 R16 R14 R16 R17 R15 R17 G10 G10 G11 G11 G12 G10 G12 G13 G11 G13 G14 G12 G14 G15 G13 G15 G16 G14 G16 G17 G15 G17 B10 B10 B11 B11 B12 B10 B12 B13 B11 B13 B14 B12 B14 B15 B13 B15 B16 B14 B16 B17 B15 B17 HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC DE DE DE 2nd Pixel Data TFT Panel Data BU7985KVT LVCMOS Output 24Bit 18Bit Pin LSB R20 R20 R21 R21 R22 R20 R22 R23 R21 R23 R24 R22 R24 R25 R23 R25 R26 R24 R26 MSB R27 R25 R27 LSB G20 G20 G21 G21 G22 G20 G22 G23 G21 G23 G24 G22 G24 G25 G23 G25 G26 G24 G26 MSB G27 G25 G27 LSB B20 B20 B21 B21 B22 B20 B22 B23 B21 B23 B24 B22 B24 B25 B23 B25 B26 B24 B26 MSB B27 B25 B27 HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC DE DE DE
LSB
MSB LSB
MSB LSB
MSB
15 / 20
CMOS Data Output Timing for Dual Link
Example : SXGA+(1400x1050)
HSYNC
DE
CLKOUT
R1x/G1x/ B1x
#1
#3
#5
#7
1395
#1397
#1399
R2x/G2x/ B2x X=0~ 7
#2
#4
#6
#8
1396
#1398
#1400
#1
#2
#1399
#1400
TFT Panel ( 1400 x 1050 )
Figure-10 Data Output Timing for Dual Link
CMOS Data Output Timing for Single Link
Example : SXGA+(1400x1050)
HSYNC
DE
CLKO UT
R 1 x /G 1 x /B 1 x x=0~ 7
#1
#2
#3
#4
1398
#1399
#1400
#1
#2
#1399
#1400
TFT Panel (1 4 0 0 x 1 0 5 0 )
Figure-11 Data Output Timing for Dual Link
16 / 20
LVDS Data Inputs Timing Diagrams in Dual Link
(Dual-in / Dual-out Mode)
Previous Cycle Current Cycle
RCLK1+
RA1+/-
R16' R15 R14' R13' R12' G12
R17
R16
R15
R14
R13
R12
G12''
RB1+/-
G17' G16 G15' G14' G13' B13
B12
G17
G16
G15
G14
G13
B13''
RC1+/-
HSYNC'
B17' B16' B15' B14'
DE
VSYNC HSYNC
B17
B16
B15
B14
DE''
RD1+/-
B10' G11' G10' R11' R10'
X
B11
B10
G11
G10
R11
R10
X"
RCLK2+
RA2+/-
R26' R25 R24' R23' R22' G22
R27
R26
R25
R24
R23
R22
G22''
RB2+/-
G27' G26' G25' G24' G23' B23
B22
G27
G26
G25
G24
G23
B23''
RC2+/-
X'
B27' B26' B25' B24'
X
X
X
B27
B26
B25
B24
X''
RD2+/-
B20' G21' G20' R21' R20'
X
B21
B20
G21
G20
R21
R20
X''
Figure-12 Data Input Timing for Dual Link
17 / 20
LVDS Data Inputs Timing Diagrams in Single Link
(Single-in / Dual-out Mode)
Previous Cycle (2nd Pixel Data) Current Cycle (1st Pixel Data)
RCLK1+
RA1+/-
G22 R27 R26 R25 R24 R23 R22 G12 R17 R16 R15 R14 R13 R12 G22''
RB1+/-
B23 B22 G27 G26 G25 G24 G23 B13 B12 G17 G16 G15 G14 G13 B23''
RC1+/-
DE
VSYNC
HSYNC
B27 B26 B25 B24 DE
VSYNC
HSYNC
B17 B16 B15 B14 DE''
RD1+/-
X
B21 B20 G21 G20 R21 R20
X
B11 B10 G11 G10 R11 R10
X
Figure-13 Data Input Timing for Single Link
Fail-Sae Hi-Z Operation
Connector attached (Receive Signal)
All Output
Toggled
Connector released (No Signal)
All Output
Hiz
Figure-14 Fail-Sage Hi-Z Operation
18 / 20
About the Power On Reset
Power On Reset is not mandatory for this device. The PD pin should be set to high level when Power On Reset procedure is not used.
VDD
BU7985KVT
Figure-9 Terminal connection when Power On Reset is not used
However, Power On Reset procedure is strongly recommend for internal logic initialization by following two methods. The method of using CR circuit. The method of using external specific IC. It is recommend to do enough examination for target application.
V DD schottky barrier diode
V DD 10K
VDD
XRST
VT
+
220 Be careful of temperature of the capacitor especially over and again. B characteristic ceramics and polymer aluminum are recommended. 2.2F
XRST Internal Reset td td is approximately equal to 20ms when the left RC coleus are applied.
Figure-15 Power On Reset by external a CR circuit
V DD VDD power on IC (open drain output) VOUT
V DD 220K XRST XRST 0.1F Internal Reset td Detection voltage VDD
VT
+
GND
B Characteristic ceramics.
Figure-16 Power On Reset by specific IC
19 / 20
TQFP100V

16.0 0.3 14.0 0.2
75 76 51 50

Container Quantity Direction of feed
0.5
Tray(with dry pack) 500pcs Direction of product is fixed in a tray.
16.0 0.3 14.0 0.2
100 1 25
26
1.2Max. 1.0 0.1 0.1 0.1
0.125 0.1
0.5
0.2 0.1
0.1
Unit:mm)
1pin
When you order , please order in times the amount of package quantity.
Catalog No.08T242A '08.6 ROHM (c)

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