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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ICS853111B
GENERAL DESCRIPTION
The ICS853111B is a low skew, high perforIC S mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/ HiPerClockSTM E C L Fa n o u t B u f fe r a n d a m e m b e r o f t h e H i Pe r C l o ck S TM fa m i l y o f H i g h Pe r fo r m a n c e Clock Solutions from ICS. The ICS853111B is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS853111B ideal for those clock distribution applications demanding well defined performance and repeatability.
FEATURES
* Ten differential 2.5V/3.3V LVPECL / ECL outputs * Two selectable differential input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: >3GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input * Output skew: 20ps (typical) * Part-to-part skew: 85ps (typical) * Propagation delay: 495ps (typical) * Jitter, RMS: < 0.03ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
PCLK0 nPCLK0 PCLK1 nPCLK1 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 CLK_SEL VBB Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8 Q9 nQ9
PIN ASSIGNMENT
nQ3 nQ4 nQ5
24 23 22 21 20 19 18 17 VCCO nQ2 Q2 nQ1 Q1 nQ0 Q0 VCCO 25 26 27 28 29 30 31 32 1
VCC
nQ6
Q3
Q4
Q5
Q6
16 15 14 13 12 11 10 9 2
CLK_SEL
VCCO Q7 nQ7 Q8 nQ8 Q9 nQ9 VCCO
ICS853111B
3
PCLK0
4
nPCLK0
5
VBB
6
PCLK1
7
nPCLK1
8
VEE
32-Lead TQFP, E-PAD 7mm x 7mm x 1.0mm package body Y Package Top View
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 9, 16, 25, 32 10, 11 12, 13 14, 15 17, 18 19, 20 21, 22 23 , 2 4 26, 27 28, 29 30, 31 Name VCC CLK_SEL PCLK0 nPCLK0 V BB PCLK1 nPCLK1 V EE VCCO nQ9, Q9 nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Power Input Input Input Output Input Input Power Power Output Output Output Output Output Output Output Output Output Output Pulldown Pullup/Pulldown Pulldown Pulldown Pullup/Pulldown Type Description Positive supply pin. Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Bias voltage. Non-inver ting differential clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Negative supply pin. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units k k
TABLE 3A. CLOCK INPUT FUNCTION TABLE
Inputs PCLKx 0 1 0 1 nPCLKx 1 0 Biased; NOTE 1 Biased; NOTE 1 Outputs Q0:Q9 LOW HIGH LOW HIGH nQ0:Q9 HIGH LOW HIGH LOW Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting
TABLE 3B. CONTROL INPUT FUNCTION TABLE
Inputs CLK_SEL 0 1 Selected Source PCLK0, nPCLK0 PCLK1, nPCLK1
Biased; 0 HIGH LOW Single Ended to Differential Inver ting NOTE 1 Biased; 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1 NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB Storage Temperature, TSTG
(Junction-to-Ambient)
4.6V (LVPECL mode, VEE = 0) -4.6V (ECL mode, VCC = 0) -0.5V to VCC + 0.5 V 0.5V to VEE - 0.5V 50mA 100mA 0.5mA -65C to 150C
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Temperature Range, TA -40C to +85C Package Thermal Impedance, JA 49.5C/W (0 lfpm)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 120 Maximum 3.8 Units V mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 PCLK0, PCLK1 Input Low Current nPCLK0, nPCLK1 Min
2.175 1.405 2.075 1.43 1.86 150 1.2 800
-40C Typ
2.275 1.545
Max
2.38 1.68 2.36 1.765 1.98 1200 3.3 150
Min
2.225 1.425 2.075 1.43 1.86 150 1.2
25C Typ
2.295 1.52
Max
2.37 1.615 2.36 1.765 1.98
Min
2.295 1.44 2.075 1.43 1.86 150 1.2
85C Typ
2.33 1.535
Max
2.365 1.63 2.36 1.765 1.98
Units
V V V V V
800
1200 3.3 15 0
800
1200 3.3 150
mV
V A A A
-10
-1 0
-10
-150 -150 -150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 Input Low Current PCLK0, PCLK1 -40C Min
1.375 0.605 1.275 0.63 150 1.2 800
25C Max
1.58 0.88 1.56 0.965 1200 2.5 150
85C Max
1.57 0.815 1.56 0.965
Typ
1.475 0.745
Min
1.425 0.625 1.275 0.63 150 1.2
Typ
1.495 0.72
Min
1.495 0.64 1.275 0.63 150 1.2
Typ
1.53 0.735
Max
1.565 0.83 1.56 0.965
Units
V V V V
80 0
1200 2.5 150
800
1200 2.5 150
mV
V A A A
-10
-10
-10
-150 -150 -150 nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 Input Low Current PCLK0, PCLK1 -40C Min
-1.125 -1.895 -1.225 -1.87 -1.44 150 VEE+1.2V 800
25C Max
-0.92 -1.62 -0.94 -1.535 -1.32 1200 0 150
85C Max
-0.93 -1.685 -0.94 -1.535 -1.32
Typ
-1.025 -1.755
Min
-1.075 -1.875 -1.225 -1.87 -1.44 150 VEE+1.2V
Typ
-1.005 -1.78
Min
-1.005 -1.86 -1.225 -1.87 -1.44 150 VEE+1.2V
Typ
-0.97 -1.765
Max
-0.935 -1.67 -0.94 -1.535 -1.32
Units
V V V V V
800
1200 0 150
800
1200 0 150
mV
V A A A
-10
-10
-10
-150 -150 -150 nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V
Symbol fMAX t PD t sk(o) t sk(pp) t jit tR/tF Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time 20% to 80% 75 375 -40C Min Typ >3 475 20 85 0.03 150 220 80 575 32 150 395 Max Min 25C Typ >3 49 5 20 85 0.03 150 215 78 595 32 150 42 5 Max Min 85C Typ >3 53 0 20 85 0.03 150 215 63 5 32 150 Max Units GHz ps ps ps ps ps
All parameters are measured 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz
0 -10 -20 -30 -40 -50
band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter at 155.52MHz
= 0.03ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment.
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC, VCCO
Qx
SCOPE
VCC nPCLK0, nPCLK1
LVPECL
VEE
nQx
V PCLK0, PCLK1 VEE
PP
Cross Points
V
CMR
-1.8V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
PART 1 nQx Qx PART 2 nQy Qy
tsk(o)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
80% Clock Outputs 20% tR
80% VSW I N G 20% tF
nPCLK0, nPCLK1 PCLK0, PCLK1 nQ0:nQ9 Q0:Q9
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
Figure 2A shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input PCLKx
V_REF
nPCLKx
C1 0.1u
R2 1K
FIGURE 2A. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 2B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin.
VDD(or VCC)
CLK_IN
+ VBB -
C1 0.1uF
FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER 8 ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and V CMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V CML Zo = 50 Ohm 3.3V R1 50 R2 50 PCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
2.5V SSTL Zo = 60 Ohm
2.5V 3.3V R3 120 R4 120 PCLK Zo = 60 Ohm nPCLK R1 120 R2 120 HiPerClockS PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V Zo = 50 Ohm R3 125 R4 125
3.3V
3.3V
3.3V LVDS Zo = 50 Ohm C1 R5 100 R3 1K R4 1K
3.3V
PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
Zo = 50 Ohm R1 1K R2 1K C2
PCLK
nPCLK
HiPerClockS PCL K/n PC LK
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 3.3V R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK R5 100 - 200 R6 100 - 200 R1 125 R2 125 HiPerClockS PCLK/nPCLK
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS
PCLK/nPCLK INPUTS For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground.
OUTPUTS
LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
Zo = 50 FOUT Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT FIN
3.3V 125 Zo = 50 FOUT Zo = 50 84 84 FIN 125
RTT =
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C.
2.5V VCCO=2.5V Zo = 50 Ohm R1 250 R3 250 + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5
2.5V
VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
2.5V
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
2.5V
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
SCHEMATIC EXAMPLE
This application note provides general design guide using ICS853111B LVPECL buffer. Figure 6 shows a schematic example of the ICS853111B LVPECL clock buffer. In this example, the input is driven by an LVPECL driver. CLK_SEL is set at logic high to select PCLK0/nPCLK0 input.
Zo = 50 + Zo = 50
R2 50 R1 50
VCC
VCC
C6 (Option) 0.1u
R3 50
Zo = 50 Ohm
Zo = 50 Ohm 3.3V LVPECL R9 50 C8 (Option) 0.1u R10 50 R11 50 R4 1K
1 2 3 4 5 6 7 8
VCCO Q0 nQ0 Q1 nQ1 Q2 nQ2 VCCO
32 31 30 29 28 27 26 25
VCC CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VEE VCCO nQ9 Q9 nQ8 Q8 nQ7 Q7 VCCO
Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6
24 23 22 21 20 19 18 17
U1 ICS853111
VCC
9 10 11 12 13 14 15 16
Zo = 50 +
VCC=3.3V
Zo = 50 R8 50 R7 50
(U1-9)
VCC
(U1-16)
C2 0.1uF
(U1-25)
(U1-32)
(U1-1)
C5 0.1uF C7 (Option) 0.1u
C1 0.1uF
C3 0.1uF
C4 0.1uF
R13 50
FIGURE 6. EXAMPLE ICS853111B LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is contacted through
SOLDER M ASK SIGNAL TRACE
solder as shown in Figure 7. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor's Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology.
EXPOSED PAD SOLDER SIGNAL TRACE
GROUND PLANE
THERM AL VIA
Expose Metal Pad (GROUND PAD)
FIGURE 7. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
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ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853111B. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853111B is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 120mA = 456mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power_MAX (3.8V, with all outputs switching) = 456mW + 309.4mW = 765.4mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.8C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.765W * 43.8C/W = 118.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
32-PIN TQFP, E-PAD FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 69.3C/W 49.5C/W
200
57.8C/W 43.8C/W
500
52.1C/W 41.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
13
ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.935V (VCC_MAX - VOH_MAX) = 0.935V
*
For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.67V (VCCO_MAX - VOL_MAX) = 1.67V
Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (V
L
CCO_MAX
- VOH_MAX))/R ] * (VCCO _MAX- VOH_MAX) =
L
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (V
L
CCO_MAX
- VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
L
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
14
ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD TQFP, E-PAD
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 69.3C/W 49.5C/W
200
57.8C/W 43.8C/W
500
52.1C/W 41.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853111B is: 1340 Pin compatible with MC100EP111 and MC100LVEP111
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
15
ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD
-HD VERSION HEAT SLUG DOWN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D, E D1, E1 D2, E2 D3, E3 e L ccc 0.45 0 -3.0 -0.05 0.95 0.30 0.09 MINIMUM NOMINAL 32 --1.0 0.35 -9.00 BASIC 7.00 BASIC 5.60 Ref. 3.5 0.80 BASIC 0.60 --0.75 7 0.10 4.0 1.20 0.15 1.05 0.40 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
16
ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS853111BY ICS853111BYT ICS853111BYLF ICS853111BYLFT Marking ICS853111BY ICS853111BY ICS853111BYLF ICS853111BYLF Package 32 lead TQFP, E-PAD 32 lead TQFP, E-PAD "Lead Free" 32 lead TQFP, E-PAD "Lead Free" 32 lead TQFP, E-PAD Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
17
ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET Rev A T8 T9 T4C B T8 Table Page 9 17 1 16 17 4 10 16 Description of Change Corrected Figure 3C. Added "Lead Free" Par t/Order Number rows. Features Section - added Lead-Free bullet. Package Dimensions - corrected dimensions D2/E2 to read 3.5mm from 5.60. Ordering Information Table - corrected Lead-Free marking and added Lead-Free note. LVPECL DC Characteristics Table - corrected VIH max. (@ 85) 1.56V from -0.83V. Added Recommendations for Unused Input and Output Pins. Package Dimensions - added dimensions D3/E3. Date 11/13/03
A
6/16/05
9/5/07
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
18
ICS853111BY REV. B SEPTEMBER 5, 2007
ICS853111B LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo, ICS and HiPerClocks are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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