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January 2007
HYB18T512400AF(L) HYB18T512800AF(L) HYB18T512160AF(L)
512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products
Internet Data Sheet
Rev. 1.71
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
HYB18T512400AF(L), HYB18T512800AF(L), HYB18T512160AF(L) Revision History: 2007-01, Rev. 1.71 Page All All 108 57 57 Subjects (major changes since last revision) Qimonda update Adapted internet edition Modified AC Timing Parameters Changed "Read" to "Write" in condition 4. Removed text "Maximum power up interval for VDD / VDDQ is specified As 20.0 ms. The power interval is defined as the amount of time it takes for VDD / VDDQ to power-up From 0 V to 1.8 V 100 mV" from condition 1.
Previous Revision: 2006-05, Rev. 1.7
Previous Revision: 2005-08, Rev. 1.6
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 03062006-CPCN-4867
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Internet Data Sheet
HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
1
1.1
Overview
Features
* Data masks (DM) for write data * Posted CAS by programmable additive latency for better command and data bus efficiency * Off-Chip-Driver impedance adjustment (OCD) and OnDie-Termination (ODT) for better signal quality. * Auto-Precharge operation for read and write bursts * Auto-Refresh, Self-Refresh and power saving PowerDown modes * Average Refresh Period 7.8 s at a TCASE lower than 85 C, 3.9 s between 85 C and 95 C * High Temperature Self Refresh Mode is supported * Full and reduced Strength Data-Output Drivers * 1KByte page size for x 4 & x 8, 2 KByte page size for x 16 * Lead-free Packages: P-TFBGA-60 for x 4 & x 8 components, P-TFBGA-84 for x 16 components * RoHS Compliant Products1)
This chapter gives an overview of the 512-Mbit DDR2 SDRAM product family and describes its main characteristics.
The 512-Mbit DDR2 SDRAM offers the following key features: * 1.8 V 0.1 V Power Supply 1.8 V 0.1 V (SSTL_18) compatible I/O * DRAM organisations with 4, 8 and 16 data in/outputs * Double Data Rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation * CAS Latency: 3, 4 and 5 * Burst Length: 4 and 8 * Differential clock inputs (CK and CK) * Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data. * DLL aligns DQ and DQS transitions with clock * DQS can be disabled for single-ended data strobe operation * Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS
TABLE 1
Performance table for -3(S)
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -3 DDR2-667C 4-4-4 -3S DDR2-667D 5-5-5 333 266 200 15 15 45 60 Unit -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
333 333 200 12 12 45 57
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
TABLE 2
Performance table for -3
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -3 DDR2-667C 4-4-4 Unit -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
333 333 200 12 12 45 57
TABLE 3
Performance table for -3S
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -3S DDR2-667D 5-5-5 Unit -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
333 266 200 15 15 45 60
TABLE 4
High Performance for DDR2-400B and DDR2-533C
Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time -3.7 DDR2-533C 4-4-4 -5 DDR2-400B 3-3-3 200 200 200 15 15 40 55 Unit -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
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Internet Data Sheet
HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
1.2
Description
4. Off-Chip Driver (OCD) impedance adjustment 5. On-Die Termination (ODT) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 16-bit address bus for x 4 and x 8 organised components and a 15-bit address bus for x 16 components is used to convey row, column and bank address information . The DDR2 device operates with a 1.8 V 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The DDR2 SDRAM is available in P-TFBGA package.
The 512-Mbit DDR2 DRAM is a high-speed Double-DataRate-Two CMOS Synchronous DRAM device containing 536,870,912 bits and internally configured as a quad-bank DRAM. The 512-Mbit device is organized as either 32 Mbit x 4 I/O x 4 banks, 16 Mbit x 8 I/O x 4 banks or 8 Mbit x 16 I/O x 4 banksx chip. These synchronous devices achieve high speed transfer rates starting at 400 Mbit/sec/pin for general applications. See Table 1, Table 2 and Table 3 for performance figures. The device is designed to comply with all DDR2 DRAM key features. 1. Posted CAS with additive latency, 2. Write latency = read latency - 1, 3. Normal and weak strength data-output driver,
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Internet Data Sheet
HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
1.3
Ordering Information
This chapter contains the Ordering Information.
TABLE 5
Ordering Information for RoHS compliant products
Part Number HYB18T512400AF-5 HYB18T512800AF-5 HYB18T512160AF-5 HYB18T512400AF-3.7 HYB18T512800AF-3.7 HYB18T512160AF-3.7 HYB18T512400AFL-3.7 HYB18T512800ALF-3.7 HYB18T512160AFL-3.7 HYB18T512400AF-3 HYB18T512800AF-3 HYB18T512160AF-3 HYB18T512400AF-3S HYB18T512800AF-3S HYB18T512160AF-3S Org. Speed x4 x8 x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 P-TFBGA-84 5-5-5 333 4-4-4 266 P-TFBGA-84 P-TFBGA-60 DDR2-667 4-4-4 333 3-3-3 200 P-TFBGA-84 P-TFBGA-60 P-TFBGA-84 P-TFBGA-60 DDR2-533 4-4-4 266 3-3-3 200 P-TFBGA-84 P-TFBGA-60 DDR2-400 CAS RCD RP3) Latencies 3-3-3
1) 2)
Clock (MHz) 200
CAS1) RCD2) RP3) Latencies --
Clock (MHz) --
Package P-TFBGA-60
1) CAS: Column Adress Strobe 2) RCD: Row Column Delay 3) RP: Row Precharge
Note: For product nomenclature see Chapter 9 of this data sheet
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
2
2.1
Pin Configuration
Pin Configuration for TFBGA-60 TFBGA-84
This chapter contains the pin configuration.
The pin configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Pin# and Buffer Type columns are explained in Table 7 and Table 8 respectively. The pin numbering for the FBGA package is depicted in Figure 1 for x 4, Figure 2 for x 8 and Figure 3 for x 16.
TABLE 6
Pin Configuration of DDR2 SDRAM
Pin# Name Pin Type I I I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL Clock Enable Clock Signal CK, Complementary Clock Signal CK Note: See functional description in x4/x8 organization Clock Enable Note: See functional description in x4/x8 organization Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Chip Select Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Chip Select Bank Address Bus 1:0 Function
Clock Signals x4/x8 organization E8 F8 F2 J8 K8 K2 CK CK CKE CK CK CKE Clock Signal CK, Complementary Clock Signal CK
Clock Signals x16 organization
Control Signals x4/x8 organizations F7 G7 F3 G8 K7 L7 K3 L8 G2 G3 RAS CAS WE CS RAS CAS WE CS BA0 BA1 I I I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Control Signals x16 organization
Address Signals x4/x8 organizations
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Internet Data Sheet
HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
Pin# H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8
Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC
Pin Type I I I I I I I I I I I I I I I -- I I -- I I I I I I I I I I I I I I I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL SSTL -- SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Address Signal 12:0, Address Signal 10/Autoprecharge
Address Signal 13 Note: x4/x8 512 Mbit components Note: and x 16 512 Mbit components Bank Address Bus 1:0
Address Signals x16 organization L2 L3 L1 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 C8 C2 D7 D3 BA0 BA1 NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 DQ0 DQ1 DQ2 DQ3
Address Signal 12:0, Address Signal 10/Autoprecharge
Data Signals x4/x8 organization Data Signal 3:0
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
Pin# D1 D9 B1 B9 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 B3 A2 B7 A8 F7 E8 B3 B3 F3
Name DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DQS RDQS RDQS UDQS UDQS LDQS LDQS DM UDM LDM
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I I I PWR
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL --
Function Data Signal 7:4
Data Signals x16 organization Data Signal 15:0
Data Strobe x4/x8 organizations Data Strobe
Data Strobe x8 organisation Read Data Strobe
Data Strobe x16 organization Data Strobe Upper Byte Data Strobe Lower Byte
Data Mask x4/x8 organizations Data Mask Data Mask Upper/Lower Byte Data Mask x16 organization
Power Supplies x4x8x16 organization A9,C1,C3,C7,C VDDQ 9 I/O Driver Power Supply
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
Pin# A1 8
Name
Pin Type PWR PWR PWR AI PWR PWR PWR PWR AI PWR PWR PWR PWR PWR PWR
Buffer Type -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Function Power Supply I/O Driver Power Supply Power Supply I/O Reference Voltage Power Supply Power Supply Power Supply Power Supply I/O Reference Voltage I/O Driver Power Supply Power Supply Power Supply I/O Driver Power Supply Power Supply Power Supply
VDD A7,B2,B8,D2,D VSSQ
A3,E3 E2 E1 E9,H9,L1 E7 J1,K9 J2
VSS VREF VDDL VDD VSSDL VSS
Power Supplies x4/x8 organizations
Power Supplies x16 organization
VREF E9, G1, G3, G7, VDDQ
G9 J1
VDDL E1, J9, M9, R1 VDD E7, F2, F8, H2, VSSQ
H8 J7 A3, E3,J3,N1,P9 G1, L3,L7, L8
VSSDL VSS
Not Connected x4/x8 organization NC NC NC -- -- Not Connected Not Connected Not Connected x4 organization A2, B1, B9, D1, NC D9 A2, E2, L1, R3, NC R7, R8 F9 K9 ODT ODT
Not Connected x16 organization NC -- Not Connected
Other Pins x4/x8 organizations I I SSTL SSTL On-Die Termination Control On-Die Termination Control Other Pins x16 organization
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
TABLE 7
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
TABLE 8
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
2.1.1
TFBGA Ball Out Diagrams
FIGURE 1
This chapter contains the TFBGA Ball Out Diagrams.
Pin Configuration for x 4 components, PG-TFBGA-60 (top view)
Notes 1. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ are isolated on the device.
2. Ball position L8 is A13 for 512-Mbit and is Not Connected on 256-Mbit
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
Pin Configuration for x 8 components, PG-TFBGA-60-24
FIGURE 2
Notes 1. RDQS / RDQS are enabled by EMRS(1) command. 2. If RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used as strobe signals during reads.
4. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ are isolated on the device. 5. Ball position L8 is A13 for 512-Mbit and is Not Connected on 256-Mbit.
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
Pin Configuration for x 16 components, PG-TFBGA-84-8
FIGURE 3
Notes 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0]
2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8] 3. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ are isolated on the device.
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
2.2
512 Mbit DDR2 Addressing
TABLE 9
DDR2 Addressing for x 4 Organization
This chapter contents the table for the 512 Mbit DDR2 Addressing.
Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes]
1) Referred to as 'org' 2) Referred to as 'colbits' 3) PageSize = 2colbits x org/8 [Bytes]
128Mb x 4 BA[1:0] 4 A10 / AP A[13:0]
1)
Note -- -- -- -- --
2)
A11, A[9:0] 11 4 1024 (1K)
--
3)
TABLE 10
DDR2 Addressing for x 8 Organization
Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes]
1) Referred to as 'org' 2) Referred to as 'colbits' 3) PageSize = 2colbits x org/8 [Bytes]
64Mb x 8 BA[1:0] 4 A10 / AP A[13:0] A[9:0] 10 8
1)
Note -- -- -- -- --
2)
--
3)
1024 (1K)
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TABLE 11
DDR2 Addressing for x 16 Organization
Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes]
1) Referred to as 'org' 2) Referred to as 'colbits' 3) PageSize = 2colbits x org/8 [Bytes]
32Mb x 161) BA[1:0] 4 A10 / AP A[12:0] A[9:0] 10 16 2048 (2K)
Note -- -- -- -- --
2)
--
3)
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3
Functional Description
TABLE 12
Mode Register Definition (BA[2:0] = 000B)
Field BA2 Bits 16 Type1) reg. addr. Description Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0B BA1 BA0 A13 15 14 13 BA2 Bank Address Bank Address [1] BA1 Bank Address 0B Bank Address [0] 0B BA0 Bank Address Address Bus [13] Note: A13 is not available for 256 Mbit and x 16 512 Mbit configuration 0B PD 12 w A13 Address bit 13 Active Power-Down Mode Select 0B PD Fast exit 1B PD Slow exit Write Recovery 2) Note: All other bit combinations are illegal. 001B 010B 011B 100B 101B DLL 8 w WR 2 WR 3 WR 4 WR 5 WR 6
WR
[11:9]
w
DLL Reset 0B DLL No 1B DLL Yes Test Mode 0B TM Normal Mode 1B TM Vendor specific test mode
TM
7
w
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
Field CL
Bits [6:4]
Type1) w
Description CAS Latency Note: All other bit combinations are illegal. 011B 100B 101B 110B 111B CL 3 CL 4 CL 5 CL 6 CL 7
BT
3
w
Burst Type 0B BT Sequential BT Interleaved 1B Burst Length Note: All other bit combinations are illegal. 010B BL 4 011B BL 8
BL
[2:0]
w
1) w = write only register bits 2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR [cycles] tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN.
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
TABLE 13
Extended Mode Register Definition (BA[2:0] = 001B)
Field BA2 Bits 16 Type
1)
Description Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0B BA2 Bank Address Bank Address [1] BA1 Bank Address 0B Bank Address [0] 0B BA0 Bank Address
reg. addr.
BA1 BA0 A13
15 14 13 w
Address Bus [13] Note: A13 is not available for 256 Mbit and x 16 512 Mbit configuration 0B A13 Address bit 13 Output Disable 0B QOff Output buffers enabled 1B QOff Output buffers disabled Read Data Strobe Output (RDQS, RDQS) 0B RDQS Disable 1B RDQS Enable Complement Data Strobe (DQS Output) 0B DQS Enable 1B DQS Disable Off-Chip Driver Calibration Program 000B OCD OCD calibration mode exit, maintain setting 001B OCD Drive (1) 010B OCD Drive (0) 100B OCD Adjust mode 111B OCD OCD calibration default
Qoff
12
RDQS
11
DQS
10
OCD [9:7] Program
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
Field AL
Bits [5:3]
Type1) --
Description Additive Latency Note: All other bit combinations are illegal. 000B 001B 010B 011B 100B AL 0 AL 1 AL 2 AL 3 AL 4
RTT
6,2
Nominal Termination Resistance of ODT Note: See Table 24 "ODT DC Electrical Characteristics" on Page 28 00B 01B 10B 11B RTT (ODT disabled) RTT 75 Ohm RTT 150 Ohm RTT 50 Ohm
DIC
1
Off-chip Driver Impedance Control 0B DIC Full (Driver Size = 100%) 1B DIC Reduced DLL Enable 0B DLL Enable 1B DLL Disable
DLL
0
1) w = write only register bits
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TABLE 14
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B)
Field BA2 Bits 16 Type1) reg.addr Description Bank Address [2] Note: BA2 is not available on 256 Mbit and 512 Mbit components 0B BA1 BA0 A 15 14 [13:8] w BA2 Bank Address Bank Adress [1] 1B BA1 Bank Address Bank Adress [0] 0B BA0 Bank Address Address Bus [13:8] Note: A13 is not available for 256 Mbit and x 16 512 Mbit configuration 0B SRF [7] w A [13:8] Address bits Address Bus [7] Note: When DRAM is operated at 85 C TCASE < 95 C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self refresh mode can be entered. 0B 1B A [6:0] w A7 disable A7 enable, adapted self refresh rate for TCASE > 85 C
Address Bus [6:0] 0B A [6:0] Address bits
1) w = write only
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TABLE 15
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B)
Field BA2 Bits 16 Type
1)
Description Bank Address [2] Note: BA2 is not available on 256 Mbit and 512 Mbit components 0B BA2 Bank Address Bank Adress [1] 1B BA1 Bank Address Bank Adress [0] BA0 Bank Address 1B
reg.addr
BA1 BA0 A
15 14 [13:0] w
Address Bus [13:0] Note: A13 is not available for 256 Mbit and x 16 512 Mbit configuration 0B A [13:0] Address bits
1) w = write only
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
TABLE 16
ODT Truth Table
Input Pin x4 components DQ[3:0] DQS DQS DM x8 components DQ[7:0] DQS DQS RDQS RDQS DM x16 components DQ[7:0] DQ[15:8] LDQS LDQS UDQS UDQS LDM UDM X X X 0 X 0 X X X X X X 0 X 0 X X 1 1 0 X X 0 X X EMRS(1) Address Bit A10 EMRS(1) Address Bit A11
Note: X = don't care; 0 = bit set to low; 1 = bit set to high
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TABLE 17
Burst Length and Sequence
Burst Length 4 Starting Address (A2 A1 A0) x00 x01 x1 0 x1 1 8 000 001 010 011 100 101 110 111 Notes 1. Page Size and Length is a function of I/O organization: 128Mb x 4 organization (CA[9:0], CA11); Page Size = 1 KByte; Page Length = 2048 64Mb x 8 organization (CA[9:0]); Page Size = 1 KByte; Page Length = 1024 Sequential Addressing (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Interleave Addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
32Mb x 16 organization (CA[9:0]); Page Size = 2 KByte; Page Length = 1024 2. Order of burst access for sequential addressing is "nibblebased" and therefore different from SDR or DDR components
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4
Truth Tables
TABLE 18
Command Truth Table
This chapter contains the truth tables.
Function
CKE Previous Cycle Current Cycle H H L H H H H H H H H X X L H
CS RAS
CAS WE BA0 BA1
A[12:11]
A10 A[9:0]
Note1)2)3)
(Extended) Mode Register Set Auto-Refresh Self-Refresh Entry Self-Refresh Exit Single Bank Precharge Precharge all Banks Bank Activate Write Write with AutoPrecharge Read Read with AutoPrecharge No Operation Device Deselect Power Down Entry Power Down Exit
H H H L H H H H H H H H H H L
L L L H L L L L L L L L L H H L H L
L L L X H L L L H H H H H X X H X H
L L L X H H H H L L L L H X X H X H
L H H X H L L H L L H H H X X H X H
BA X X X BA X BA BA BA BA BA X X X X
OP Code X X X X X Column Column Column Column X X X X X X X L H L H L H X X X X X X X X X Column Column Column Column X X X X
4)5)
4) 4)6) 4)6)7)
4)5) 4) 4)5) 4)5)8) 4)5)8)
Row Address
4)5)8) 4)5)8)
4) 4) 4)9)
4)9)
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 2) "X" means "H or L (but a defined logic level)". 3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 5) Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register. 6) VREF must be maintained during Self Refresh operation. 7) Self Refresh Exit is asynchronous. 8) Burst reads or writes at BL = 4 cannot be terminated. 9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements
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TABLE 19
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1) CKE Previous Cycle6) (N-1) Power-Down Self Refresh Bank(s) Active All Banks Idle L L L L H H H Any State other than listed above
1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11)
Current Cycle6) (N) L H L H L L L H
Command (N)2) 3) RAS, CAS, WE
Action (N)2)
Note4)5)
X DESELECT or NOP X DESELECT or NOP DESELECT or NOP DESELECT or NOP AUTOREFRESH
Maintain Power-Down Power-Down Exit Maintain Self Refresh Self Refresh Exit Active Power-Down Entry Precharge Power-Down Entry Self Refresh Entry
7)8)11) 7)9)10)11) 8)11)12) 9)12)13)14) 7)9)10)11)15) 9)10)11)15)
7)11)14)16) 17)
H
Refer to the Command Truth Table
12) 13) 14) 15) 16) 17)
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. CKE must be maintained HIGH while the device is in OCD calibration mode. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in EMRS(1)). All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2xtCKE + tIH. VREF must be maintained during Self Refresh operation. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. Valid commands for Self Refresh Exit are NOP and DESELCT only. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table.
TABLE 20
Data Mask (DM) Truth Table
Name (Function) Write Enable Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
DM L H
DQs Valid X
Note
1) 1)
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5
5.1
AC & DC Operating Conditions
Absolute Maximum Ratings
TABLE 21
Absolute Maximum Ratings
This chapter contains the AC & DC Operating Conditions.
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 21 at any time.
Symbol
Parameter
Rating Min. Max. +2.3 +2.3 +2.3 +2.3
Unit
Note
Storage Temperature -55 +100 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
VDD VDDQ VDDL VIN, VOUT TSTG
Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS
-1.0 -0.5 -0.5 -0.5
V V V V C
1) 1)2) 1)2) 1) 1)2)
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 22
DRAM Component Operating Temperature Range
Symbol Parameter Rating Min. Max. 95 C
1)2)3)4)
Unit
Note
TOPER
Operating Temperature
0
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 C under all other specification parameters. 3) Above 85 C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 s 4) When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %
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5.2
DC Characteristics
TABLE 23
Recommended DC Operating Conditions (SSTL_18)
This chapter describes the DC characteristics.
Symbol
Parameter
Rating Min. Typ. 1.8 1.8 1.8 0.5 x VDDQ Max. 1.9 1.9 1.9 0.51 x VDDQ
Unit
Note
VDD VDDDL VDDQ VREF VTT
1) 2) 3) 4)
Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage
1.7 1.7 1.7 0.49 x VDDQ
V V V V
1) 1) 1) 2)3)
4) Termination Voltage VREF - 0.04 VREF VREF + 0.04 V VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. Peak to peak ac noise on VREF may not exceed 2% VREF (dc) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in die dc level of VREF.
TABLE 24
ODT DC Electrical Characteristics
Parameter / Condition Termination resistor impedance value for EMRS(1)[A6,A2] = [0,1]; 75 Ohm Termination resistor impedance value for EMRS(1)[A6,A2] =[1,0]; 150 Ohm Termination resistor impedance value for EMRS(1)(A6,A2)=[1,1]; 50 Ohm Deviation of VM with respect to VDDQ / 2 Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) delta VM Min. 60 120 40 -6.00 Nom. 75 150 50 -- Max. 90 180 60 Unit Note
1)
1)
1)
2) + 6.00 % 1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIH(ac) - VIL(ac)) I(I(VIHac) - I(VILac)). 2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) -
1) x 100%
TABLE 25
Input and Output Leakage Currents
Symbol IIL IOL Parameter / Condition Input Leakage Current; any input 0 V < VIN < VDD Output Leakage Current; 0 V < VOUT < VDDQ Min. -2 -5 Max. +2 +5 Unit A A Note
1) 2)
1) all other pins not under test = 0 V 2) DQ's, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
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5.3
DC & AC Characteristics
In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is verified by design and characterization but not subject to production test. In single ended mode, the DQS (and RDQS) signals are internally disabled and don't care.
DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF.
TABLE 26
DC & AC Logic Input Levels
Symbol Parameter DDR2-400, DDR2-533 Min. Max. DDR2-667 Min. Max. Unit
VIH(dc) VIL(dc) VIH(ac) VIL(ac)
DC input logic high DC input low AC input logic high AC input low
VREF + 0.125
-0.3
VDDQ + 0.3 VREF - 0.125
--
VREF + 0.125
-0.3
VDDQ + 0.3 VREF - 0.125
--
V V V V
VREF + 0.250
--
VREF + 0.200
--
VREF - 0.250
VREF - 0.200
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TABLE 27
Single-ended AC Input Test Conditions
Symbol Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum Slew Rate Value 0.5 x VDDQ 1.0 1.0 Unit V V V / ns Note
1) 1) 2)3)
VREF VSWING.MAX
SLEW
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to VIL(ac).MAX for falling edges as shown in Figure 4 3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions.
FIGURE 4
Single-ended AC Input Test Conditions Diagram
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TABLE 28
Differential DC and AC Input and Output Logic Levels
Symbol Parameter DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross point input voltage AC differential cross point output voltage Min. -0.3 0.25 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 Max. Unit -- -- V V V Note
1) 2) 3) 4) 5)
VIN(dc) VID(dc) VID(ac) VIX(ac) VOX(ac)
1) 2) 3) 4)
VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125
the voltage at which differential input signals must cross. 5) The value of VOX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc. VID(dc) specifies the input differential voltage VTR- VCP required for switching. The minimum value is equal to VIH(dc) - VIL(dc). VID(ac) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(ac) - VIL(ac). The value of is expected to equal 0.5 x VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac) indicates
FIGURE 5
Differential DC and AC Input and Output Logic Levels Diagram
VDDQ VTR
Crossing Point
VID VIX or VOX VSSQ
SSTL18_3
VCP
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5.4
Output Buffer Characteristics
TABLE 29
SSTL_18 Output DC Current Drive
This chapter describes the Output Buffer Characteristics.
Symbol
Parameter Output Minimum Source DC Current
SSTL_18 -13.4
Unit mA
Note
1)2)
2)3) Output Minimum Sink DC Current 13.4 mA 1) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 3). They are used to test drive current capability to ensure VIH.MIN. plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
IOH IOL
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement. 3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
TABLE 30
SSTL_18 Output AC Test Conditions
Symbol Parameter Minimum Required Output Pull-up Maximum Required Output Pull-down Output Timing Measurement Reference Level SSTL_18 Unit V V V Note
1) 1)
VOH VOL VOTR
VTT + 0.603 VTT - 0.603 0.5 x VDDQ
--
1) The SSTL_18 test load has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that 335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA x 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput device (13.4 mA x 45 Ohm = 603 mV).
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TABLE 31
OCD Default Characteristics
Symbol -- -- -- Description Output Impedance Pull-up / Pull down mismatch Output Impedance step size for OCD calibration Min. -- 0 0 -- -- 4 1.5 Nominal Max. Unit Ohms Ohms Ohms Note
1)2) 1)2)3) 4)
1)5)6)7) Output Slew Rate 1.5 -- 5.0 V / ns 1) Absolute Specifications (TOPER; VDD = 1.8 V 0.1 V; VDDQ = 1.8 V 0.1 V), altering OCD from default state no longer requires DRAM to
SOUT
2)
3) 4)
5) 6) 7)
meet timing, voltage and slew rate specifications on I/O's. Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT-VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ - 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = -280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV. Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 0.75 Ohms under nominal conditions. The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC. This is verified by design and characterization but not subject to production test. Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ's is included in tDQSQ and tQHS specification. DRAM output Slew Rate specification applies to 400, 533 and 667 MHz speed bins.
5.5
Input / Output Capacitance
TABLE 32
Input / Output Capacitance
This chapter describes the Input / Output Capacitance.
Symbol
Parameter
DDR2-400 & DDR2-533 Min. Max. 2.0 0.25 2.0 0.25 4.0 0.5
DDR2-667 Min. 1.0 -- 1.0 -- 2.5 -- Max. 2.0 0.25 2.0 0.25 3.5 0.5
Unit
CCK CDCK CI CDI CIO CDIO
Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS
1.0 -- 1.0 -- 2.5 --
pF pF pF pF pF pF
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5.6
Overshoot and Undershoot Specification
TABLE 33
AC Overshoot / Undershoot Specification for Address and Control Pins
This chapter describes the Overshoot and Undershoot Specification.
Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS
DDR2-400 0.9 0.9 1.33 1.33
DDR2-533 0.9 0.9 1.00 1.00
DD2-667 0.9 0.9 0.80 0.80
Unit V V V.ns V.ns
FIGURE 6
AC Overshoot / Undershoot Diagram for Address and Control Pins
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TABLE 34
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ DDR2-400 0.9 0.9 0.38 0.38 DDR2-533 0.9 0.9 0.28 0.28 DD2-667 0.9 0.9 0.23 0.23 Unit V V V.ns V.ns
FIGURE 7
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
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6
Currents, Specifications,Conditions
TABLE 35
IDD Measurement Conditions
This chapter contains the currents, specifications and conditions.
Parameter
Symbol Note
1)2)3)4)5) 6)
Operating Current - One bank Active - Precharge IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. Operating Current - One bank Active - Read - Precharge IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching.
IDD1
1)2)3)4)5) 6)
Precharge Power-Down Current IDD2P All banks idle; CKE is LOW; tCK = tCK(IDD); Other control and address inputs are stable; Data bus inputs are floating. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching, Data bus inputs are switching.
1)2)3)4)5) 6)
IDD2N
1)2)3)4)5) 6)
Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable, Data bus inputs are floating. Active Power-Down Current All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs are floating. MRS A12 bit is set to "0" (Fast Power-down Exit). Active Power-Down Current All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit); Active Standby Current All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; IOUT = 0 mA. Operating Current Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; Burst Refresh Current tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching.
1)2)3)4)5) 6)
IDD3P(0)
1)2)3)4)5) 6)
IDD3P(1)
1)2)3)4)5) 6)
IDD3N
1)2)3)4)5) 6)
IDD4R
1)2)3)4)5) 6)
IDD4W
1)2)3)4)5) 6)
IDD5B
1)2)3)4)5) 6)
Distributed Refresh Current IDD5D tCK = tCK(IDD), Refresh command every tREFI = 7.8 s interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching.
1)2)3)4)5) 6)
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Parameter
Symbol Note
1)2)3)4)5) 6)
Self-Refresh Current IDD6 CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current IDD7 1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 x tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs are stable during deselects; Data bus is switching. 2. Timing pattern: DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks) DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks) DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks) DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks) 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized. 3) IDD parameter are specified with ODT disabled.
4) 5) 6) 7) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. Definitions for IDD: see Table 36 Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7.. A = Activate, RA = Read with Auto-Precharge, D=DESELECT
1)2)3)4)5) 6)7)
TABLE 36
Definition for IDD
Parameter LOW HIGH STABLE FLOATING SWITCHING Description defined as VIN VIL(ac).MAX defined as VIN VIH(ac).MIN defined as inputs are stable at a HIGH or LOW level defined as inputs are VREF = VDDQ / 2 defined as: Inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for DQ signals not including mask or strobes
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TABLE 37
IDD Specification for HYB18T512xxxAF(L)
Symbol -3 DDR2-667 Max. -3S DDR2-667 Max. 71 90 85 104 50 5.5 -- 40 50 19 6 130 150 140 170 140 6 5.5 -- 147 228 -3.7 DDR2-533 Max. 65 80 75 90 40 5.5 2 30 40 16 5.5 90 115 95 130 130 6 5.5 2 145 220 -5 DDR2-400 Max. 55 70 60 75 32 5.5 -- 25 35 13 5.5 70 85 80 110 120 6 5.5 -- 140 210 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA x4/x8 x16 x4/x8 x16 -- --
1)
Unit
Note
IDD0 IDD1 IDD2N IDD2P IDD2P(L) IDD2Q IDD3N IDD3P(MRS= 0) IDD3P(MRS= 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD6(L) IDD7
1) 2) 3) 4)
75 95 90 110 50 5.5 -- 40 50 19 6 130 150 140 170 140 6 5.5 -- 155 240
-- --
2) 3)
x4/x8 x16 x4/x8 x16 --
4) 4) 1)4)
x4/x8 x16
For LowPower Components MRS(12)=0 MRS(12)=1 0 TCASE 85C
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7
7.1
Electrical Characteristics
Speed Grade Definitions
TABLE 38
Speed Grade Definition Speed Bins for DDR2-667
This chapter lists the electrical characteristics.
This chapter contains the speed grade definition tables.
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol
DDR2-667C -3 4-4-4 Min. 5 3 3 45 57 12 12 Max. 8 8 8 70000 -- -- --
DDR2-667D -3S 5-5-5 Min. 5 3.75 3 45 60 15 15 Max. 8 8 8 70000 -- -- --
Unit
Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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TABLE 39
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-533C -3.7 4-4-4 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- DDR2-400B -5 3-3-3 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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7.2
AC Timing Parameters
TABLE 40
DRAM Component Timing Parameter by Speed Grade - DDR2-667
This chapter contains the AC timing parameters.
Parameter
Symbol
DDR2-667 Min. Max. +450 -- 0.52 8000 -- 0.52 -- -- -- -- +400 -- -- 240 + 0.25 -- -- -- __
Unit
Note1)2)3)4)5)6)7)
DQ output access time from CK / CK CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low pulse width) Average clock low pulse width
tAC tCCD tCH.AVG tCK.AVG tCKE
-450 2 0.48 3000 3 0.48 WR + tnRP
ps nCK
8)
--
9)10)
tCK.AVG
ps nCK
--
11)
tCL.AVG Auto-Precharge write recovery + precharge time tDAL Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW DQ and DM input hold time
tCK.AVG
nCK ns ps ps
9)10) 12)13)
tIS + tCK .AVG + tIH
175 0.35 -400 0.35 0.35 -- - 0.25 100 0.2 0.2 Min (tCH.ABS, tCL.ABS) -- 275 0.6 200 2 x tAC.MIN
--
18)19)14)
tDH.BASE DQ and DM input pulse width for each input tDIPW DQS output access time from CK / CK tDQSCK DQS input high pulse width tDQSH DQS input low pulse width tDQSL DQS-DQ skew for DQS & associated DQ signals tDQSQ DQS latching rising transition to associated clock tDQSS
edges DQ and DM input setup time DQS falling edge hold time from CK DQS falling edge to CK setup time CK half pulse width Data-out high-impedance time from CK / CK
tCK.AVG --
8)
tCK.AVG -- tCK.AVG --
ps
15) 16)
tCK.AVG
ps
tDS.BASE tDSH tDSS tHP
17)18)19) 16) 16) 20)
tCK.AVG tCK.AVG
ps ps ps ps ps ps ns nCK ns ps ps
tHZ Address and control input hold time tIH.BASE Control & address input pulse width for each input tIPW Address and control input setup time tIS.BASE DQ low impedance time from CK/CK tLZ.DQ DQS/DQS low-impedance time from CK / CK tLZ.DQS MRS command to ODT update delay tMOD Mode register set command cycle time tMRD OCD drive mode output delay tOIT DQ/DQS output hold time from DQS tQH DQ hold skew factor tQHS
tAC.MAX
-- -- --
8)21) 24)22)
tCK.AVG --
23)24) 8)21) 8)21) 30)
tAC.MIN
0 2 0
tAC.MAX tAC.MAX
12 -- 12 -- 340
--
30) 25) 26)
tHP - tQHS
--
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Parameter
Symbol
DDR2-667 Min. Max.
Unit
Note1)2)3)4)5)6)7)
Average periodic refresh Interval 0C TCASE 85C 85C TCASE 95C Read preamble Read postamble Internal Read to Precharge command delay Write preamble Write postamble Write recovery time Internal write to read command delay Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit self-refresh to a non-read command Exit self-refresh to read command Write command to DQS associated clock edges
tREFI
-- - - 0.9 0.4 7.5 0.35 0.4 15 7.5 2 7 - AL 2 7.8 3.9 1.1 0.6 -- -- 0.6 -- -- -- -- -- -- -- s
tRPRE tRPST tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR tXSRD
WL
tCK.AVG tCK.AVG
ns
27)28) 27)29) 30)
tCK.AVG -- tCK.AVG --
ns ns nCK nCK nCK ns nCK nCK
30) 30)31)
-- -- --
30)
tRFC +10
200 RL-1
-- --
1) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V. See notes 4)5)6)7) 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) New units, `tCK.AVG` and `nCK`, are introduced in DDR2-667 and DDR2-800. Unit `tCK.AVG` represents the actual tCK.AVG of the input clock under operation. Unit `nCK` represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, `tCK` is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN - tERR(6-10PER).MAX = - 400 ps - 293 ps = - 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX - tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2-667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps - 293 ps = - 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 9) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 10) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations). 11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
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14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 9. 15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 9. 18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 22) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 10. 23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 10. 24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 25) tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 26) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 27) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 8 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 28) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.PER.MIN = - 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG - 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.DUTY.MIN = - 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG - 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 30) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
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FIGURE 8
Method for calculating transitions and endpoint
FIGURE 9
Differential input waveform timing - tDS and tDS
FIGURE 10
Differential input waveform timing - tlS and tlH
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TABLE 41
DRAM Component Timing Parameter by Speed Grade - DDR2-533
Parameter Symbol DDR2-533 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. +500 -- 0.55 -- 0.55 -- -- -- -- -- +450 -- 300 + 0.25 -- -- -- -- ps -- -- -- -- --
7)17)
Unit
Note1)2)3)4)5)
6)
tAC tCCD tCH tCKE tCL tDAL tDELAY tDH(base)
-500 2 0.45 3 0.45 WR + tRP
tCK tCK tCK tCK tCK
ns ps ps
tIS + tCK + tIH
225 -25 0.35 -450 0.35 -- - 0.25 100 -25 0.2 0.2 MIN. (tCL, tCH) -- 375 0.6 250 2 x tAC.MIN
8)
9)
DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
10)
tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS(base)
tCK
ps
-- -- --
10)
tCK
ps
tCK
ps ps
--
10)
DQ and DM input setup time (single ended data tDS1(base) strobe) DQS falling edge hold time from CK (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval
10)
tDSH
tCK tCK
ps ps
-- --
11) 12) 10)
DQS falling edge to CK setup time (write cycle) tDSS
tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS tREFI
tAC.MAX
-- -- --
tCK
ps ps ps
--
10) 13) 13)
tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 -- 400 7.8
tCK
ns ps s
-- -- -- --
13)14)
tHP -tQHS
-- --
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Parameter
Symbol
DDR2-533 Min. Max. 3.9 -- -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- -- -- --
Unit
Note1)2)3)4)5)
6)
Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command
tREFI tRFC tRP tRP tRPRE tRPST tRRD tRRD tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR tXSRD
-- 105
s ns ns ns
15)17) 16)
tRP + 1tCK
15 + 1tCK 0.9 0.40 7.5 10 7.5 0.25 0.40 15 7.5 2 6 - AL 2
-- --
13) 13) 13)17)
tCK tCK
ns ns ns
15)21)
-- --
18)
tCK tCK
ns ns
--
19) 20)
tCK tCK tCK
ns
20)
-- -- --
21)
tRFC +10
200
Write recovery time for write with AutoWR Precharge 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 4)5)6)7)
tWR/tCK
tCK tCK
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) For timing definition, refer to the Component data sheet. 10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
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12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 13) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 14) 0 C TCASE 85 C 15) 85 C < TCASE 95 C 16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 "Ordering Information for RoHS compliant products" on Page 6. 18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. 21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS.
TABLE 42
DRAM Component Timing Parameter by Speed Grade - DDR2-400
Parameter Symbol DDR2-400 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. +600 -- 0.55 -- 0.55 -- -- -- -- -- +500 -- 350 + 0.25 -- -- ps -- -- -- -- --
7)20)
Unit
Note1)2)3)4)5)
6)
tAC tCCD tCH tCKE tCL tDAL tDELAY tDH(base)
-600 2 0.45 3 0.45 WR + tRP
tCK tCK tCK tCK tCK
ns ps ps
tIS + tCK + tIH
275 -25 0.35 -500 0.35 -- - 0.25 150 -25
8)
9)
DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data strobe)
10)
tDIPW tDQSCK tDQSL,H tDQSQ
tCK
ps
-- -- --
10)
tCK
ps
Write command to 1st DQS latching transition tDQSS
tCK
ps ps
--
10)
tDS(base) tDS1(base)
10)
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
Parameter
Symbol
DDR2-400 Min. Max. -- --
Unit
Note1)2)3)4)5)
6)
DQS falling edge hold time from CK (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command
tDSH
0.2 0.2 MIN. (tCL, tCH) -- 475 0.6 350 2 x tAC.MIN
tCK tCK
ps ps
-- --
11) 12) 10)
DQS falling edge to CK setup time (write cycle) tDSS
tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS tREFI tREFI
tAC.MAX
-- -- --
tCK
ps ps ps
--
10) 13) 13)
tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 -- 450 7.8 3.9 -- -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- --
tCK
ns ps s s ns ns ns
-- -- -- --
13)14) 15)17) 16)
tHP -tQHS
-- -- -- 105
tRP tRP tRPRE tRPST tRRD tRRD tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR
tRP + 1tCK
15 + 1tCK 0.9 0.40 7.5 10 7.5 0.25 0.40 15 10 2 6 - AL 2
-- --
13) 13) 13)17)
tCK tCK
ns ns ns
15)21)
-- --
18)
tCK tCK
ns ns
--
19) 20)
tCK tCK tCK
ns
20)
-- --
tRFC +10
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Parameter
Symbol
DDR2-400 Min. Max. -- --
Unit
Note1)2)3)4)5)
6)
Exit Self-Refresh to Read command
tXSRD
200
Write recovery time for write with AutoWR Precharge 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 4)5)6)7)
tWR/tCK
tCK tCK
--
21)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) For timing definition, refer to the Component data sheet. 10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 13) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 14) 0 C TCASE 85 C 15) 85 C < TCASE 95 C 16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 "Ordering Information for RoHS compliant products" on Page 6. 18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. 21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS.
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7.3
ODT AC Electrical Characteristics
TABLE 43
ODT AC Characteristics and Operating Conditions for DDR2-667
This chapter contains the ODT AC electrical characteristics tables.
Symbol
Parameter / Condition
Values Min. Max. 2
Unit
Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
nCK
ns ns
1) 1)2) 1) 1) 1)3) 1) 1) 1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns
2.5
nCK
ns ns
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
nCK nCK
1) New units, "tCK.AVG" and "nCK", are introduced in DDR2-667 and DDR2-800. Unit "tCK.AVG" represents the actual tCK.AVG of the input clock under operation. Unit "nCK" represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, "tCK" is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.
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TABLE 44
ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400
Symbol Parameter / Condition Values Min. Max. 2 Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
tCK
ns ns
--
1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns
2.5
-- --
2)
tCK
ns ns
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
-- -- --
tCK tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
8
Package Dimensions
FIGURE 11
Package Outline PG-TFBGA-60
This chapter contains the package dimensions.
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
FIGURE 12
Package Outline PG-TFBGA-84
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9
Product Nomenclature
TABLE 45
Nomenclature Fields and Examples
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.
Example for
Field Number 1 2 18 3 T 4 512 5 16 6 7 0 8 A 9 C 10 -3.7 11 --
DDR2 DRAM
HYB
TABLE 46
DDR2 Memory Components
Field 1 2 3 4 Description QIMONDA Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 5+6 Number of I/Os 40 80 160 7 8 Product Variations Die Revision 0 .. 9 A B C 9 Package, Lead-Free Status Speed Grade C F 10 -1.9 -2.5F -2.5 -3 -3S -3.7 -5 11 N/A for Components -- Coding Constant SSTL_18 DDR2 256 M 512 M 1 Gb x4 x8 x 16 look up table First Second Third FBGA, lead-containing FBGA, lead-free DDR2-1066 DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3 --
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List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Pin Configuration for x 4 components, PG-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration for x 8 components, PG-TFBGA-60-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration for x 16 components, PG-TFBGA-84-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . Method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input waveform timing - tDS and tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input waveform timing - tlS and tlH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline PG-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline PG-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 14 30 31 34 35 44 44 44 52 53
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List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Performance table for -3(S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Performance table for -3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance table for -3S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 High Performance for DDR2-400B and DDR2-533C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DDR2 Addressing for x 4 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DDR2 Addressing for x 8 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DDR2 Addressing for x 16 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Mode Register Definition (BA[2:0] = 000B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Extended Mode Register Definition (BA[2:0] = 001B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Differential DC and AC Input and Output Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SSTL_18 Output DC Current Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 OCD Default Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . 35 IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 IDD Specification for HYB18T512xxxAF(L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Speed Grade Definition Speed Bins for DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DRAM Component Timing Parameter by Speed Grade - DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DRAM Component Timing Parameter by Speed Grade - DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DRAM Component Timing Parameter by Speed Grade - DDR2-400. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ODT AC Characteristics and Operating Conditions for DDR2-667. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . 51 Nomenclature Fields and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DDR2 Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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HYB18T512[40/80/16]0AF(L)-[3/3S/3.7/5] 512-Mbit DDR2 SDRAM
Table of Contents
1 1.1 1.2 1.3 2 2.1 2.1.1 2.2 3 4 5 5.1 5.2 5.3 5.4 5.5 5.6 6 7 7.1 7.2 7.3 8 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 5 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration for TFBGA-60 TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TFBGA Ball Out Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 512 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC & DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 28 29 32 33 34 39 39 41 50
Currents, Specifications,Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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Internet Data Sheet
Edition 2007-01 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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