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Product Specification
PE43404
Product Description
The PE43404 is a high linearity, 4-bit RF Digital Step Attenuator (DSA) covering a 15 dB attenuation range in 1.0 dB steps. This 75-ohm RF DSA provides both parallel (latched or direct mode) and serial CMOS control interface, operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE43404 exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4 mm QFN footprint. The PE43404 is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram
Switched Attenuator Array RF Input RF Output
75 RF Digital Attenuator 4-bit, 15 dB, DC - 2.0 GHz Features * Attenuation: 1.0 dB steps to 15 dB * Flexible parallel and serial programming interfaces * Parallel latched or direct mode * High attenuation accuracy and linearity over temperature and frequency * Unique power-up state selection * Very low power consumption * Single-supply operation * Positive CMOS control logic * 75 impedance * Packaged in a 20 Lead 4x4 mm QFN
Figure 2. Package Type
20 Lead 4x4 mm QFN
Parallel Control Serial Control Power-Up Control
5
3
Control Logic Interface
1
Table 1. Electrical Specifications @ +25C, VDD = 3.0 V
Parameter
Operation Frequency Insertion Loss
1
Test Conditions
Frequency
Minimum
DC
Typical
Maximum
2000
Units
MHz dB dB dBm dBm dB s
DC 1.2 GHz Any Bit or Bit Combination DC 1.2 GHz 1 MHz 1.2 GHz Two-tone inputs up to +18 dBm Zo = 75 ohms 50% control 1 MHz 1.2 GHz DC 1.2 GHz
30 10 -
1.4 34 52 13 -
1.95 (0.25+ 7% of atten setting) 1
Attenuation Accuracy 1 dB Compression3,4 Input IP31,2,4 Return Loss Switching Speed Notes: 1. 2. 3. 4.
Device Linearity will begin to degrade below 1MHz Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency. Note Absolute Maximum in Table 3. Measured in a 50 system. (c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11
Document No. 70-0258-02 www.psemi.com
PE43404
Product Specification
Figure 15. Pin Configuration (Top View)
GND GND C1 C2 C4
Table 3. Absolute Maximum Ratings
Symbol
VDD VI
Parameter/Conditions
Power supply voltage Voltage on any input Storage temperature range Input power (50) ESD voltage (Human Body Model)
Min
-0.3 -0.3 -65
Max
4.0 VDD+ 0.3 150 +30 500
Units
V V C dBm V
20
19
18
17
N/C RF1 Data Clock LE
16
1 2 3 4 5 10
15
C8 RF2 P/S Vss/GND GND
20-lead QFN 4x4mm
Exposed Solder Pad
TST PIN VESD
14 13 12 11
Table 2. Pin Descriptions
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Paddle
Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability.
6
7
8
N/C
9
Pin Name
N/C RF1 Data Clock LE VDD N/C PUP2 VDD GND GND Vss/ GND P/S RF2 C8 C4 C2 GND C1 GND GND No connect
PUP2
GND
VDD
VDD
Description
RF port (Note 1). Serial interface data input (Note 4). Serial interface clock input. Latch Enable input (Note 2). Power supply pin. No connect Power-up selection bit. Power supply pin. Ground connection. Ground connection. Negative supply voltage or GND connection (Note 3) Parallel/Serial mode select. RF port (Note 1). Attenuation control bit, 8 dB. Attenuation control bit, 4 dB. Attenuation control bit, 2 dB. Ground connection. Attenuation control bit, 1 dB. Ground for proper operation Ground for proper operation
Table 4. Operating Ranges
Parameter
VDD Power Supply Voltage IDD Power Supply Current Digital Input High Digital Input Low Digital Input Leakage Input Power Temperature range -40 0.7xVDD 0.3xVDD 1 +24 85
Min
2.7
Typ
3.0
Max
3.3 100
Units
V A V V A dBm C
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up.
Notes: 1. Both RF ports must be held at 0 VDC or DC blocked with an external series capacitor. 2. Latch Enable (LE) has an internal 100 kresistor to VDD. 3. Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to VSS (-VDD) to bypass and disable internal negative voltage generator. 4. Place a 10 kresistor in series, as close to pin as possible to avoid frequency resonance. See "Resistor on 3" paragraph
Switching Frequency
The PE43404 has a maximum 25 kHz switching rate.
Resistor on Pin 3
A 10 k resistor on the input to Pin 3 (see Figure 5) will eliminate package resonance between the RF input pin and the digital input. Specified attenuation error versus frequency performance is dependent upon this condition.
Document No. 70-0258-02 UltraCMOSTM RFIC Solutions
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package must be grounded for proper device operation.
(c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11
PE43404
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit was designed to ease customer evaluation of the PE43404 DSA. J9 is used in conjunction with the supplied DC cable to supply VDD, GND, and -VDD. If use of the internal negative voltage generator is desired, then connect - VDD (black banana plug) to ground. If an external -VDD is desired, then apply -3V. J1 should be connected to the LPT1 port of a PC with the supplied control cable. The evaluation software is written to operate the DSA in serial mode, so switch 7 (P/S) on the DIP switch SW1 should be ON with all other switches off. Using the software, enable or disable each attenuation setting to the desired combined attenuation. The software automatically programs the DSA each time an attenuation state is enabled or disabled. Note: Jumper J6 supplies power to the evaluation board support circuits. To evaluate the Power Up options, first disconnect the control cable from the evaluation board. The control cable must be removed to prevent the PC port from biasing the control pins. During power up with P/S=1 high and LE=1, the default power-up signal attenuation is set to the value present on the four control bits on the four parallel data inputs (C1 to C8). This allows any one of the 32 attenuation settings to be specified as the power-up state. During power up with P/S=0 high and LE=0, the control bits are automatically set to one of two possible values presented through the PUP interface. These two values are selected by the power-up control bit, PUP2, as shown in Table 6. Pins 1 and 7 are open and may be connected to any bias.
J18 SMA Z=75 Ohm 1 R25 DATA R23 0 OHM 10K CLK LE
Figure 4. Evaluation Board Layout
Peregrine Specification 101-0112
Figure 5. Evaluation Board Schematic
Peregrine Specification 102-0142
C1
C 2 18 17 C2
20
19
G ND
C1
C4
16
C 4
N/C
1 2 3 4 5
GND
N/C
C8
15 14 13 12 11
C8 R24 0 OHM PS -VDD
Z=75 Ohm 1
J19 SMA
RFIN DATA CLK
U4 MLPQ4X4
RFOUT PS VNEG
J20 SUPPLY VDD 4 3 2 1
2
or GND
PUP1
6
7
8
PUP2
VDD
LE
9
10
VDD_D GND
GND
C14 100pF
C12 0.1F VDD
PUP1
Note: Resistor on pin 3 is required and should be placed as close to the part as possible to avoid package resonance and meet error specifications over frequency.
P UP2
C10 100pF
C9 0.1F
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(c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11
2
PE43404
Product Specification
Typical Performance Data @ 25C, VDD = 3.0 V Figure 6. Insertion Loss (Zo=75 ohms)
0 -0.5 -40C -1 Insertion Loss (dB) -1.5 -2 -2.5 -3 -3.5 -4 0 500 1000 RF Frequency (MHz) 1500 2000 25C
Figure 7. Attenuation at Major steps
16 14 12 Attenuation (dB)
85C
15dB
10 8 6 4 2 0 0 500 1000 RF Frequency (MHz) 1500 2000 4dB 2dB 1dB 8dB
Figure 8. Input Return Loss at Major Attenuation Steps (Zo=75 ohms)
0
Figure 9. Output Return Loss at Major Attenuation Steps (Zo=75 ohms)
0
-5
-10 Output Return loss (dB)
Input Return Loss (dB)
-10
-20
-15
-30
-20 8dB -25 15dB -30 0 500 1000
4dB
-40
-50
1500
2000
0
500
1000 RF Frequency (MHz)
1500
2000
RF Frequency (MHz)
(c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11
Document No. 70-0258-02 UltraCMOSTM RFIC Solutions
PE43404
Product Specification
Typical Performance Data @ 25C, VDD = 3.0 V Figure 10. Attenuation Error Vs. Frequency Figure 11. Attenuation Error Vs. Attenuation Setting
1 10Mhz 250Mhz 500Mhz 750Mhz 1010Mhz 1210Mhz
0.5
0
0.5
Attenuation Error (dB)
-0.5 8dB -1 15dB
Attenuation Error (dB)
0
-1.5
-0.5
-2 0 500 1000 RF Frequency (MHz) 1500 2000
-1 0 2 4 6 8 10 12 14 16
Attenuation Setting (dB)
Figure 12. Input IP3 vs. Frequency (Zo=50 ohms)
Figure 13. Input 1 dB Compression (Zo=50 ohms)
60 55 50 1dB Compression (dBm) Input IP3 (dBm) 45 40 35 30 25 20 0 500 1000 RF Frequency (MHz) 1500 2000
40 35 30 25 20 15 10 5 0 0 500 1000 RF Frequency (MHz) 1500 2000
Note: Positive attenuation error indicates higher attenuation than target value
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PE43404
Product Specification
Typical Performance Data @ 25C, VDD = 3.0 V Figure 14. Attenuation Error Vs. Attenuation Setting
0.4 0.3 0.2 Attenuation Error (dB) 0.1 0 -0.1 10MHz, -40C -0.2 -0.3 -0.4 0 2 4 6 8 10 12 14 16 10MHz, 25C 10MHz, 85C
Figure 15. Attenuation Error Vs. Attenuation Setting
0.4 0.3 0.2 Attenuation Error (dB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0 2 4 6 8 10 12 14 16 500MHz, -40C 500MHz, 25C 500MHz, 85C
Attenuation Setting (dB)
Attenuation Setting (dB)
Figure 16. Attenuation Error Vs. Attenuation Setting
0.4 0.3 0.2 Attenuation Error (dB) 0.1 0 -0.1 -0.2 -0.3 1000MHz, 85C -0.4 0 2 4 6 8 10 12 14 16 1000MHz, -40C 1000MHz, 25C
Attenuation Error (dB)
Figure 17. Attenuation Error Vs. Attenuation Setting
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 2 4 6 8 10 12 14 16 1200MHz, 85C 1200MHz, 25C
1200MHz, -40C
Attenuation Setting (dB)
Attenuation Setting (dB)
Note: Positive attenuation error indicates higher attenuation than target value
(c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11
Document No. 70-0258-02 UltraCMOSTM RFIC Solutions
PE43404
Product Specification
Programming Options
Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE43404. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel / Direct Mode Interface The parallel interface consists of four CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 19 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched parallel programming, the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 19) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers).
serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The start bit (B5) and stop bit (B0) of the data should always be low to prevent an unknown state in the device. The timing for this operation is defined by Figure 18 (Serial Interface Timing Diagram) and Table 8 (Serial Interface AC Characteristics). Power-up Control Settings The PE43404 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/ S=1), the four control bits are set to whatever data is present on the four parallel data inputs (C1 to C8). This allows any one of the 16 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/ S=0) with LE=0, the control bits are automatically set to one of two possible values. These two values are selected by the power-up control bit, PUP2, as shown in Table 6 (Power-Up Truth Table, Parallel Mode).
Table 5. Truth Table
P/S
0 0 0 0 0 0
C8
0 0 0 0 1 1
C4
0 0 0 1 0 1
C2
0 0 1 0 0 1
C1
0 1 0 0 0 1
Attenuation State
Reference Loss 1 dB 2 dB 4 dB 8 dB 15 dB
Table 6. Power-Up Truth Table, Parallel Interface Mode
P/S
0 0 0 Note:
Note: Not all 16 possible combinations of C1-C8 are shown in table
LE
0 0 1
PUP2
0 1 X
Attenuation State
Reference Loss 8 dB Defined by C1-C8
Serial Interface The PE43404's serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. The latch is controlled by three CMOScompatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be
Power up with LE=1 provides normal parallel operation with C1-C8, and PUP2 is not active.
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PE43404
Product Specification
Figure 18. Serial Interface Timing Diagram
LE
Table 7. 4-Bit Attenuator Serial Programming Register Map
Clock
B5 0
B4 C8
B3 C4
B2 C2
B1 C1
B0 0
Data
MSB
LSB
MSB (first in)
tLESUP tLEPW
LSB (last in)
tSDSUP
tSDHLD
Note: The start bit (B5) and stop bit (B0) must always be low to prevent an unknown state in the device .
Figure 19. Parallel Interface Timing Diagram
LE
Parallel Data C8:C1
tPDSUP
tLEPW
tPDHLD
Table 8. Serial Interface AC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
fClk tClkH tClkL tLESUP tLEPW tSDSUP tSDHLD Note:
Table 9. Parallel Interface AC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
tLEPW tPDSUP tPDHLD
Parameter
Serial data clock frequency (Note 1) Serial clock HIGH time Serial clock LOW time LE set-up time after last clock falling edge LE minimum pulse width Serial data set-up time before clock rising edge Serial data hold time after clock falling edge
Min
Max
10
Unit
MHz ns ns ns ns ns ns
Parameter
LE minimum pulse width Data set-up time before rising edge of LE Data hold time after falling edge of LE
Min
10 10 10
Max
----
Unit
ns ns ns
30 30 10 30 10 10
fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification.
(c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11
Document No. 70-0258-02 UltraCMOSTM RFIC Solutions
PE43404
Product Specification
Figure 20. Package Drawing
20 Lead 4x4 mm QFN
4.00 INDEX AREA 2.00 X 2.00 -B2.00
2.00 0.25 C -A0.10 C 0.08 C 0.020 0.20 REF EXPOSED PAD & TERMINAL PADS SEATING PLANE 0.80 4.00 -C2.00 TYP 0.50 TYP 0.55 2.00 1.00
5 11
0.435 0.18 1.00 EXPOSED PAD 0.23 1 0.10 CAB 2.00
1 15 20 16 6 10
0.435
0.18
4.00
DETAIL A
DETAIL A
2
1. Dimension applies to metallized terminal and is measured between 0.25 and 0.30 from terminal tip. 2. Coplanarity applies to the exposed heat sink slug as well as the terminals. 3. Dimensions are in millimeters.
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PE43404
Product Specification
Figure 21. Marking Specifications
43404 YYWW ZZZZZ
YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number
Figure 22. Tape and Reel Drawing
Table 10. Ordering Information
Order Code
PE43404MLI PE43404MLI-Z EK43404-01
Part Marking
43404 43404 PE43404-EK
Description
PE43404G-20MLP 4x4mm-75A PE43404G-20MLP 4x4mm-3000C PE43404-20MLP 4x4mm-EK
Package
Green 20-lead 4x4 mm QFN Green 20-lead 4x4 mm QFN Evaluation Kit
Shipping Method
Tape or loose 3000 units / T&R 1 / Box
(c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11
Document No. 70-0258-02 UltraCMOSTM RFIC Solutions
PE43404
Product Specification
Sales Offices
The Americas Peregrine Semiconductor Corporation
9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499
North Asia Pacific Peregrine Semiconductor K.K.
Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213
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South Asia Pacific Peregrine Semiconductor, China
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Space and Defense Products
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Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).
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