|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
TECHNICAL DATA IN74HC574A Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS N SUFFIX PLASTIC DIP The IN74HC574A is identical in pinout to the LS/ALS574. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The OE input does not affect the states of the flipflops, but when OE is high, all device outputs are forced to the highimpedance state; thus, data may be stored even when the outputs are not enabled. * * * * Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices 20 1 20 1 DW SUFFIX SOIC ORDERING INFORMATION IN74HC574AN IN74HC574ADW IN74HC574ATDS Plastic DIP SOIC SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM OE D0 D1 D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK 2 3 4 5 6 7 8 9 11 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 V CC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK D2 D3 D4 D5 D6 D7 GND FUNCTION TABLE Inputs Output D H L L,H, X X X Q H L no change Z OE PIN 20=VCC PIN 10 = GND L L L H Clock 1 OE H= high level L = low level X = don't care Z = high impedance Rev. 00 IN74HC574A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1.5 mm from Case for 4 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 35 75 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Rev. 00 IN74HC574A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VC C Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 0.5 85 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 5.0 125 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 10 A A V Unit V Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage Test Conditions VOUT VCC-0.1 V IOUT 20 A VOUT 0.1 V IOUT 20 A VIN=VIH IOUT 20 A VIN=VIH IOUT 6.0 mA IOUT 7.8 mA V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 VIL V VOH V VOL Maximum Low-Level Output Voltage VIN= VIL IOUT 20 A VIN= VIL IOUT 6.0 mA IOUT 7.8 mA IIN IOZ Maximum Input Leakage Current Maximum Three State Leakage Current VIN=VCC or GND Output in High-Impedance State VIN =VIH VOUT= VCC or GND VIN=VCC or GND IOUT=0A ICC Maximum Quiescent Supply Current (per Package) 6.0 4.0 40 160 A Rev. 00 IN74HC574A AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns) VCC Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock to Q (Figures 1 and 4) Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Enabled Output) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 6.0 30 35 160 32 27 150 30 26 140 28 24 60 12 10 10 15 85C 4.8 24 28 200 40 34 190 38 33 175 35 30 75 15 13 10 15 125 C 4.0 20 24 240 48 41 225 45 38 210 42 36 90 18 15 10 15 Unit MHz tPLH, tPHL ns tPLZ, tPHZ ns tPZH, tPZL ns tTLH, tTHL ns CIN COUT pF pF Typical @25C,VCC=5.0 V 24 pF TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns) VCC Symbol tSU Parameter Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) Minimum Pulse Width, Clock (Figure 1) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 25 C to -55C 50 10 9 5 5 5 75 15 13 1000 500 400 Guaranteed Limit 85C 65 13 11 5 5 5 95 19 16 1000 500 400 125C 75 15 13 5 5 5 110 22 19 1000 500 400 Unit ns th ns tw ns tr, tf ns Rev. 00 IN74HC574A tr CLOCK 90% 50% 10% tf VCC VCC GND OE t PZL Q t PHL Q t THL tPZH 50% 50% 50% GND t PLZ 10% t PHZ 90% HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE tw 1/fmax tPLH Q 50% 10% 90% tTLH Figure 1. Switching Waveforms VALID D Figure 2. Switching Waveforms VCC 50% GND t su CLOCK 50% th VCC GND Figure 3. Switching Waveforms TEST POINT TEST POINT 1k CL * DEVICE UNDER TEST OUTPUT * CL DEVICE UNDER TEST OUTPUT Connect to V CC when testing tPLZ and tPZL Connect to GND when testing tPHZ and tPZH * Includes all probe and jig capacitance Figure 4. Test Circuit * Includes all probe and jig capacitance Figure 5. Test Circuit EXPANDED LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 D CQ CLOCK D CQ D CQ D CQ D CQ D CQ D CQ D CQ OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Rev. 00 IN74HC574A N SUFFIX PLASTIC DIP (MS - 001AD) A Dimension, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLANE G H H J N G D 0.25 (0.010) M T K M J K L M N 10 3.81 8.26 0.36 NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 013AC) A 20 11 Dimension, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0 0.1 0.23 10 0.25 8 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SEATING PLANE J F M G H J K M P R NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. Rev. 00 IN74HC574A TSSOP-20 Rev. 00 |
Price & Availability of IN74HC574ADW |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |