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FUJITSU SEMICONDUCTOR DATA SHEET
DS06-20112-2E
Semicustom
CMOS
Embedded array
CE77 Series
DESCRIPTION
The CE77 series 0.25 m CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed and low power consumption at the same time. CE77 series is available in 15 frames with the enhanced lineup of 470 K to 6980 K gates.
FEATURES
* * * * * * * * * * * * * * * * * Technology : 0.25 m silicon-gate CMOS, 3- to 4-layer wiring Supply voltage : +2.5 V 0.2 V (normal) to +1.5 V 0.1 V Junction temperature range : -40 C to +125 C Gate delay time : tpd = 33 ps (2.5 V, inverter cell High Speed type, F/O = 1, No load) Gate power consumption : 0.02 W/MHz (1.5 V, F/O = 1, No load) High-load driving capability : IOL = 2 mA/4 mA/8 mA/12 mA mixable Output buffer cells with noise reduction circuits Inputs with on-chip input pull-up/pull-down resistors (25 k typical) and bidirectional buffer cells Buffer cells dedicated to crystal oscillator Special interface (P-CML, LVDS, T-LVTTL, SSTL, PCI, USB, GTL+, and others including those under development) IP macros (CPU, PCI, USB, IrDA, PLL, DAC, ADC, and others including those under development) Capable of incorporating compiled cells (RAM/ROM/FIFO/Delay line, and others.) Configurable internal bus circuits Advanced hardware/software co-design environment Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time Hierarchical design environment for supporting large-scale circuits Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture (Continued)
Copyright(c)2002-2007 FUJITSU LIMITED All rights reserved
CE77 Series
(Continued) * Support for memory (RAM/ROM) SCAN * Support for memory (RAM) BIST * Support for boundary SCAN * Support for path delay test * A variety of package options (SQFP, HQFP, PBGA, LQFP, FBGA under development)
MACRO LIBRARY (Including macros being prepared)
1.
* * * * * * * * * * *
Logic cells (about 700 types)
Adder AND-OR Inverter Clock Buffer Latch NAND AND NOR SCAN Flip Flop BUS Driver EOR Others * * * * * * * * * * AND-OR Decoder Non-SCAN Flip Flop Inverter Buffer OR-AND Inverter OR Selector ENOR Boundary Scan Register
2. IP macros
CPU Interface macro Multimedia processing macros Mixed signal macros Compiled macros PLL SPARClite, ARM7 USB, IrDA, etc. JPEG, etc. ADC, DAC, Analog switch, etc. RAM, ROM, FIFO, Delay Line, Analog PLL
3. Special I/O interface macros
* P-CML * USB
2
CE77 Series
CHIP STRUCTURE
The chip layout of the CE77 series consists of two major areas : chip peripheral area and basic cell area. The chip peripheral area contains the input/output buffer cells for interfacing with external devices and the associated bonding pads. The basic cell area contains some of input/output buffer cells, the unit cells and the compiled cells. * Chip configuration
Bonding pad
I/O buffer cell
Basic cell area
3
CE77 Series
COMPILED CELLS
Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CE77 series has the following types of compiled cells (Note that each macro is different in word/bit range depending on the column type) .
1. Clock synchronous single-port RAM (1 address, 1 RW)
(High density type) / (Partial write type) Column type Memory capacity 4 16 16 to 72 K 64 to 72 K Word range 16 to 1 K 64 to 4 K Bit range 1 to 72 1 to 18 Unit bit bit
(Ultra high density type) Column type Memory capacity 4 4 16 64 to 72 K 2064 to 512 K 4160 to 512 K
Word range 32 to 1 K 1032 to 4 K 2080 to 16 K
Bit range 2 to 72 2 to 128 2 to 32
Unit bit bit bit
(Low power consumption type) Column type Memory capacity 4 8 (High speed type) Column type 8 128 to 72 K 256 to 72 K
Word range 32 to 1 K 64 to 2 K
Bit range 4 to 72 4 to 36
Unit bit bit
Memory capacity 128 to 144 K
Word range 32 to 2 K
Bit range 4 to 72
Unit bit
2. Clock synchronous dual-port RAM (2 addresses, 1 RW/1 R)
Column type 4 16 Memory capacity 16 to 72 K 64 to 72 K Word range 16 to 1 K 64 to 4 K Bit range 1 to 72 1 to 18 Unit bit bit
3. Clock synchronous register file (3 addresses, 1W/2R)
Column type 1 Memory capacity 4608 Word range 4 to 64 Bit range 1 to 72 Unit bit
4. Clock synchronous register file (4 addresses, 2W/2R)
Column type 1 Memory capacity 4608 Word range 4 to 64 Bit range 1 to 72 Unit bit
4
CE77 Series
5. Clock synchronous ROM (1 address, 1R)
Column type 8 16 Memory capacity 128 to 512 K 128 to 512 K Word range 32 to 4 K 64 to 8 K Bit range 4 to 128 2 to 64 Unit bit bit
6. Clock synchronous delay line memory (2 addresses, 1W/1R)
Column type 8 16 32 Memory capacity 512 to 32 K 512 to 32 K 512 to 32 K Word range 32 to 1 K 64 to 2 K 128 to 4 K Bit range 16 to 32 8 to 16 4 to 8 Unit bit bit bit
7. Clock synchronous FIFO memory (2 addresses, 1W/1R)
Column type 8 16 32 Memory capacity 512 to 32 K 512 to 32 K 512 to 32 K Word range 32 to 1 K 64 to 2 K 128 to 4 K Bit range 16 to 32 8 to 16 4 to 8 Unit bit bit bit
5
CE77 Series
ABSOLUTE MAXIMUM RATINGS
Rating Min - 0.5 - 0.5 - 0.5 -55 -40 Max +3.0*4 +4.0*5 VDD + 0.5 ( 3.0 V) *4 VDD + 0.5 ( 4.0 V) *5 VDD + 0.5 ( 3.0 V) *4 VDD + 0.5 ( 4.0 V) *5 +125 +125 13 13 mA 13 26 60 mA
Parameter Power supply voltage*1 Input voltage *1 Output voltage*1 Storage temperature Junction temperature L type M type Output current*
2
Symbol VDD VI VO Tst Tj
Application VDD = 1.4 V to 2.7 V VDD = 2.7 V to 3.6 V Powerless type (IOL = 2 mA) Normal type (IOL = 4 mA) Power type (IOL = 8 mA) High power type (IOL = 12 mA)
Unit V V V C C
IO H type V type
Power-supply pin current *3 *1 : VSS = 0 V
ID
Per VDD, GND pin
*2 : Maximum output current which can be supplied constantly. *3 : Maximum supply current which can be supplied constantly. *4 : Internal gate part in case of single power supply or dual power supply. *5 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
6
CE77 Series
RECOMMENDED OPERATING CONDITIONS
1. Single power supply
* Conditions: VDD = 2.5 V0.2 V, VSS = 0 V Parameter Power supply voltage "H" level input voltage "L" level input voltage Junction temperature * Conditions: VDD = 1.8 V0.15 V, VSS = 0 V Parameter Power supply voltage "H" level input voltage "L" level input voltage Junction temperature * Conditions: VDD = 1.5 V0.1 V, VSS = 0 V Parameter Power supply voltage "H" level input voltage "L" level input voltage Junction temperature CMOS normal CMOS schmitt CMOS normal CMOS schmitt Symbol VDDI VIH VIL Tj Value Min 1.4 VDD x 0.7 VDD x 0.8 -0.3 -40 Typ 1.5 Max 1.6 VDD + 0.3 VDD x 0.3 VDD x 0.2 +125 Unit V V V C CMOS normal CMOS schmitt CMOS normal CMOS schmitt Symbol VDDI VIH VIL Tj Value Min 1.65 VDD x 0.65 VDD x 0.8 -0.3 -40 Typ 1.8 Max 1.95 VDD + 0.3 VDD x 0.35 VDD x 0.2 +125 Unit V V V C CMOS normal CMOS schmitt CMOS normal CMOS schmitt Symbol VDD VIH VIL Tj Value Min 2.3 1.7 VDD x 0.8 -0.3 -40 Typ 2.5 Max 2.7 VDD + 0.3 +0.7 VDD x 0.2 +125 Unit V V V C
7
CE77 Series
2. Dual power supply
* Conditions: VDDE = 3.3 V0.3 V/VDDI = 2.5 V0.2 V, VDDI = 1.8 V0.15 V, VDDI = 1.5 V0.1 V, VSS = 0 V Value Parameter Symbol Min Typ Max Power supply voltage 1.5 V CMOS normal 1.8 V CMOS normal 2.5 V CMOS normal 3.3 V CMOS normal "H" level input voltage 1.5 V CMOS schmitt 1.8 V CMOS schmitt 2.5 V CMOS schmitt 3.3 V CMOS schmitt 5 V Tolerant 1.5 V CMOS normal 1.8 V CMOS normal 2.5 V CMOS normal 3.3 V CMOS normal "L" level input voltage 1.5 V CMOS schmitt 1.8 V CMOS schmitt 2.5 V CMOS schmitt 3.3 V CMOS schmitt 5 V Tolerant Junction temperature Tj -40 VDDE x 0.2 + 0.8 +125 C VIL -0.3 VDDI x 0.2 VDDE x 0.8 2.0 VDDE + 0.3 5.5 VDDI x 0.3 VDDI x 0.35 + 0.7 + 0.8 V VIH VDDI x 0.8 VDDE VDDI 3.0 1.4 VDDI x 0.7 VDDI x 0.65 1.7 2.0 VDDI + 0.3 VDDE + 0.3 V VDDI + 0.3 3.3 3.6 2.7
Unit V
8
CE77 Series
* Conditions: VDDE = 2.5 V0.2 V/VDDI = 1.8 V0.15 V, VDDI = 1.5 V0.1 V, VSS = 0 V Value Parameter Symbol Min Typ Power supply voltage 1.5 V CMOS normal 1.8 V CMOS normal "H" level input voltage 2.5 V CMOS normal 1.5 V CMOS schmitt 1.8 V CMOS schmitt 2.5 V CMOS schmitt 1.5 V CMOS normal 1.8 V CMOS normal "L" level input voltage 2.5 V CMOS normal 1.5 V CMOS schmitt 1.8 V CMOS schmitt 2.5 V CMOS schmitt Junction temperature Tj -40 VIL -0.3 VIH VDDE VDDI 2.3 1.4 VDDI x 0.7 VDDI x 0.65 1.7 VDDI x 0.8 VDDE x 0.8 2.5
Max 2.7 1.95 VDDI + 0.3 VDDE + 0.3 VDDI + 0.3 VDDE + 0.3 VDDI x 0.3 VDDI x 0.35 0.7 VDDI x 0.2 VDDE x 0.2 +125
Unit V
V
V
C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
9
CE77 Series
DC CHARACTERISTICS
* Single power supply : VDD = 2.5 V (Standard) Parameter Symbol T2 T3, T4 T5 to T7 T8, T9 Power supply current*1 IDDS TA TB, TC TD TE TF TG "H" level output voltage "L" level output voltage "H" level output voltage V-I characteristics "L" level output current V-I characteristics Input leakage current Pull-up/pull-down resistance VOH VOL IL RP IOH = -100 A IOL = 100 A 2.5 V VDD = 2.5 V0.2 V 2.5 V VDD = 2.5 V0.2 V Pull-up VIL = 0 V Pull-down VIH = VDD Conditions (VDD = 2.5 V 0.2 V, VSS = 0 V, Tj = -40 C to +125 C) Value Min VDD - 0.2 0 *2 *2 10 Typ 25 Max 0.1 0.2 0.3 0.4 0.5 0.6 0.8 1.0 1.1 1.3 VDD 0.2 5 120 V V A k mA Unit
*1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : Refer to "(2) 2.5 V" in V-I CHARACTERISTICS.
10
CE77 Series
* Single power supply : VDD = 1.8 V Parameter Symbol T2 T3, T4 T5 to T7 T8, T9 Power supply current*1 IDDS TA TB, TC TD TE TF TG "H" level output voltage "L" level output voltage "H" level output voltage V-I characteristics "L" level output current V-I characteristics Input leakage current Pull-up/pull-down resistance VOH VOL IL RP IOH = -100 A IOL = 100 A 1.8 V VDD = 1.8 V0.15 V 1.8 V VDD = 1.8 V0.15 V Pull-up VIL = 0 V Pull-down VIH = VDD Conditions (VDD = 1.8 V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C) Value Min VDD - 0.2 0 *2 *2 10 Typ 40 Max 0.1 0.2 0.3 0.4 0.5 0.6 0.8 1.0 1.1 1.3 VDD 0.2 5 120 V V A k mA Unit
*1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : Refer to "(3) 1.8 V" in V-I CHARACTERISTICS.
11
CE77 Series
* Single power supply : VDD = 1.5 V Parameter Symbol T2 T3, T4 T5 to T7 T8, T9 Power supply current*1 IDDS TA TB, TC TD TE TF TG "H" level output voltage "L" level output voltage "H" level output voltage V-I characteristics "L" level output current V-I characteristics Input leakage current Pull-up/pull-down resistance VOH VOL IL RP IOH = -100 A IOL = 100 A 1.5 V VDD = 1.5 V0.1 V 1.5 V VDD = 1.5 V0.1 V Pull-up VIL = 0 V Pull-down VIH = VDD Conditions (VDD = 1.5 V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C) Value Min VDD - 0.2 0 *2 *2 10 Typ 55 Max 0.1 0.2 0.3 0.4 0.5 0.6 0.8 1.0 1.1 1.3 VDD 0.2 5 120 V V A k mA Unit
*1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : Refer to "(4) 1.5 V" in V-I CHARACTERISTICS.
12
CE77 Series
* Dual power supply : VDDE = 3.3 V/VDDI = 2.5 V, 1.8 V, 1.5 V (VDDE = 3.3 V 0.3 V/VDDI = 2.5 V0.2 V, 1.8 V 0.15 V, 1.5 V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C) Parameter Symbol T2 T3, T4 T5 to T7 T8, T9 Power supply current*1 IDDS TA TB, TC TD TE TF TG VOH4 "H" level output voltage VOH3 VOH2 VOH1 VOL4 "L" level output voltage VOL3 VOL2 VOL1 "H" level output V-I characteristics "L" level output V-I characteristics Input leakage current IL 3.3 V 2.5 V RP 1.8 V 1.5 V 3.3 V output IOH = -100 A 2.5 V output IOH = -100 A 1.8 V output IOH = -100 A 1.5 V output IOH = -100 A 3.3 V output IOL = 100 A 2.5 V output IOL = 100 A 1.8 V output IOL = 100 A 1.5 V output IOL = 100 A 3.3 V VDDE = 3.3 V0.3 V 2.5 V VDDI = 2.5 V0.2 V 1.8 V VDDE = 1.8 V0.15 V 1.5 V VDDI = 1.5 V0.1 V 3.3 V VDDE = 3.3 V0.3 V 2.5 V VDDI = 2.5 V0.2 V 1.8 V VDDE = 1.8 V0.15 V 1.5 V VDDI = 1.5 V0.1 V Pull-up VIL = 0 Pull-down VIH = VDDE Pull-up VIL = 0 Pull-down VIH = VDDI Pull-up VIL = 0 Pull-down VIH = VDDI Pull-up VIL = 0 Pull-down VIH = VDDI Conditions Value Min VDDE - 0.2 VDDI - 0.2 VDDI - 0.2 VDDI - 0.2 0 0 0 0 *2 *3 *4 *5 *2 *3 *4 *5 10 10 10 10 Typ 25 25 40 55 Max 0.1 0.2 0.3 0.4 0.5 0.6 0.8 1.0 1.1 1.3 VDDE VDDI VDDI VDDI 0.2 0.2 0.2 0.2 5 70 120 k 120 120 A V V mA Unit
Pull-up/pull-down resistance
*1: When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2: Refer to "(1) 3.3 V" in V-I CHARACTERISTICS. *3: Refer to "(2) 2.5 V" in V-I CHARACTERISTICS. *4: Refer to "(3) 1.8 V" in V-I CHARACTERISTICS". *5: Refer to "(4) 1.5 V" in V-I CHARACTERISTICS. 13
CE77 Series
* Dual power supply : VDDE = 2.5 V/VDDI = 2.5 V, 1.8 V, 1.5 V (VDDE = 2.5 V 0.2 V/VDDI = 1.8 V0.15 V, 1.5 V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C) Parameter Symbol T2 T3, T4 T5 to T7 T8, T9 Power supply current*1 IDDS TA TB, TC TD TE TF TG VOH3 "H" level output voltage VOH2 VOH1 VOL3 "L" level output voltage VOL2 VOL1 "H" level output V-I characteristics "L" level output V-I characteristics Input leakage current IL 2.5 V Pull-up/pull-down resistance RP 1.8 V 1.5 V 2.5 V output IOH = -100 A 1.8 V output IOH = -100 A 1.5 V output IOH = -100 A 2.5 V output IOL = 100 A 1.8 V output IOL = 100 A 1.5 V output IOL = 100 A 2.5 V VDDE = 2.5 V0.2 V 1.8 V VDDI = 1.8 V0.15 V 1.5 V VDDI = 1.5 V0.1 V 2.5 V VDDE = 2.5 V0.2 V 1.8 V VDDI = 1.8 V0.15 V 1.5 V VDDI = 1.5 V0.1 V Pull-up VIL = 0 Pull-down VIH = VDDE Pull-up VIL = 0 Pull-down VIH = VDDI Pull-up VIL = 0 Pull-down VIH = VDDI Conditions Value Min VDDE - 0.2 VDDI - 0.2 VDDI - 0.2 0 0 0 *2 *3 *4 *2 *3 *4 10 10 10 Typ 25 40 55 Max 0.1 0.2 0.3 0.4 0.5 0.6 0.8 1.0 1.1 1.3 VDDE VDDI VDDI 0.2 0.2 0.2 5 120 120 120 k A V V mA Unit
*1: When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2: Refer to "(2) 2.5 V" in V-I CHARACTERISTICS. *3: Refer to "(3) 1.8 V" in V-I CHARACTERISTICS". *4: Refer to "(4) 1.5 V" in V-I CHARACTERISTICS.
14
CE77 Series
V-I CHARACTERISTICS
(1) 3.3 V * 3.3 V normal I/O V-I characteristics [ Condition : VDD = 3.0 V ] "L" level output V-I characteristics (VDD = 3.0 V) "H" level output V-I characteristics (VDD = 3.0 V) 3.0 V normal I/O VOL-IOL (Min) 3.0 V normal I/O VOH-IOH (Min)
VOH (V)
0.0 0.0 -10.0 1.0 2.0 3.0 30.0 40.0
L type IOL (Min) (mA)
V type
M type H type V type
IOH (Min) (mA)
H type
20.0
-20.0 -30.0 -40.0
M type
10.0
L type
0.0 0.0 -50.0
1.0
2.0
3.0
VOL (V)
* 3.3 V normal I/O V-I characteristics [ Condition : VDD = 3.3 V ] "H" level output V-I characteristics (VDD = 3.3 V) "L" level output V-I characteristics (VDD = 3.3 V) 3.3 V normal I/O VOH-IOH (Min) 3.3 V normal I/O VOL-IOL (Min)
VOH (V)
0.0 0.0 -10.0 1.0 2.0 3.0 30.0 40.0
V type
L type IOL (Min) (mA)
M type
H type
20.0
IOH (Min) (mA)
-20.0 -30.0
H type V type
M type
10.0
L type
-40.0 -50.0
0.0 0.0
1.0
2.0
3.0
VOL (V)
* 3.3 V normal I/O V-I characteristics [ Condition : VDD = 3.6 V ] "H" level output V-I characteristics (VDD = 3.6 V) 3.3 V normal I/O VOH-IOH (Min)
VOH (V)
0.0 0.0 -10.0 1.0 2.0 3.0
"L" level output V-I characteristics (VDD = 3.6 V) 3.3 V normal I/O VOL-IOL (Min)
40.0
L type IOL (Min) (mA)
30.0
V type H type
20.0
M type
IOH (Min) (mA)
-20.0
H type
-30.0 -40.0 -50.0
M type
10.0
L type
V type
0.0 0.0 1.0 2.0 3.0
VOL (V)
15
CE77 Series
(2) 2.5 V * 2.5 V normal I/O V-I characteristics [ Condition : VDD = 2.3 V ] "H" level output V-I characteristics (VDD = 2.3 V) 2.5 V normal I/O VOH-IOH (Min)
VOH (V)
0.0 0.0 1.0 2.0 3.0
"L" level output V-I characteristics (VDD = 2.3 V) 2.5 V normal I/O VOL-IOL (Min)
30.0
L type IOL (Min) (mA) M type
20.0
V type H type
10.0
IOH (Min) (mA)
-10.0
H type
-20.0
M type L type
V type
-30.0 0.0 0.0 1.0 2.0 3.0
VOL (V)
* 2.5 V normal I/O V-I characteristics [ Condition : VDD = 2.5 V ] "H" level output V-I characteristics (VDD = 2.5 V) 2.5 V normal I/O VOH-IOH (Min)
VOH (V)
0.0 0.0 1.0 2.0 3.0
"L" level output V-I characteristics (VDD = 2.5 V) 2.5 V normal I/O VOL-IOL (Min)
30.0
V type
L type IOH (Min) (mA) M type
-10.0
IOL (Min) (mA)
20.0
H type
H type
-20.0
10.0
M type L type
V type
-30.0
0.0 0.0
1.0
2.0
3.0
VOL (V)
* 2.5 V normal I/O V-I characteristics [ Condition : VDD = 2.7 V ] "H" level output V-I characteristics (VDD = 2.7 V) 2.5 V normal I/O VOH-IOH (Min)
VOH (V)
0.0 0.0 1.0 2.0 3.0
"L" level output V-I characteristics (VDD = 2.7 V) 2.5 V normal I/O VOL-IOL (Min)
30.0
V type
L type IOL (Min) (mA) M type H type
20.0
IOH (Min) (mA)
-10.0
H type
-20.0
10.0
M type L type
-30.0
V type
0.0 0.0
-40.0
1.0
2.0
3.0
VOL (V)
16
CE77 Series
(3) 1.8 V * 1.8 V normal I/O V-I characteristics [ Condition : VDD = 1.65 V ] "H" level output V-I characteristics (VDD = 1.65 V) 1.8 V normal I/O VOH-IOH (Min)
VOH (V)
0.0 0.0 1.0 2.0
"L" level output V-I characteristics (VDD = 1.65 V) 1.8 V normal I/O VOL-IOL (Min)
20.0
L type M type IOL (Min) (mA)
V type H type M type L type
0.0 0.0 1.0 2.0
IOH (Min) (mA)
10.0
-10.0
H type
V type
-20.0
VOL (V)
* 1.8 V normal I/O V-I characteristics [ Condition : VDD = 1.8 V ] "H" level output V-I characteristics (VDD = 1.8 V) "L" level output V-I characteristics (VDD = 1.8 V) 1.8 V normal I/O VOH-IOH (Min) 1.8 V normal I/O VOL-IOL (Min)
VOH (V)
0.0 0.0 1.0 2.0 20.0
L type IOH (Min) (mA) M type IOL (Min) (mA)
V type H type
10.0
-10.0
H type
M type L type
V type
-20.0
0.0 0.0
1.0
2.0
VOL (V)
* 1.8 V normal I/O V-I characteristics [ Condition : VDD = 1.95 V ] "H" level output V-I characteristics (VDD = 1.95 V) 1.8 V normal I/O VOH-IOH (Min)
VOH (V)
0.0 0.0 1.0 2.0
"L" level output V-I characteristics (VDD = 1.95 V) 1.8 V normal I/O VOL-IOL (Min)
20.0
V type IOL (Min) (mA)
L type M type H type
10.0
IOH (Min) (mA)
-10.0
H type V type
M type L type
0.0 0.0
-20.0
-30.0
1.0
2.0
VOL (V)
17
CE77 Series
(4) 1.5 V * 1.5 V normal I/O V-I characteristics [ Condition : VDD = 1.4 V ] "H" level output V-I characteristics (VDD = 1.4 V) "L" level output V-I characteristics (VDD = 1.4 V) 1.5 V normal I/O VOH-IOH (Min) 1.5 V normal I/O VOL-IOL (Min)
VOH (V)
0.0 0.0 0.5 1.0 1.5 15.0
L type M type IOL (Min) (mA)
10.0
V type
IOH (Min) (mA)
-5.0
H type
H type
-10.0
5.0
M type L type
V type
0.0 0.0 -15.0 0.5 1.0 1.5
VOL (V)
* 1.5 V normal I/O V-I characteristics [ Condition : VDD = 1.5 V ] "H" level output V-I characteristics (VDD = 1.5 V) "L" level output V-I characteristics (VDD = 1.5 V) 1.5 V normal I/O VOH-IOH (Min) 1.5 V normal I/O VOL-IOL (Min)
VOH (V)
0.0 0.0 0.5 1.0 1.5 15.0
V type IOL (Min) (mA)
10.0
L type IOH (Min) (mA) M type
-5.0
H type
H type
-10.0
5.0
M type L type
V type
-15.0
0.0 0.0
0.5
1.0
1.5
VOL (V)
* 1.5 V normal I/O V-I characteristics [ Condition : VDD = 1.6 V ] "H" level output V-I characteristics (VDD = 1.6 V) "L" level output V-I characteristics (VDD = 1.6 V) 1.5 V normal I/O VOH-IOH (Min) 1.5 V normal I/O VOL-IOL (Min)
VOH (V)
0.0 0.0 0.5 1.0 1.5 15.0
L type IOL (Min) (mA) M type H type
10.0
V type H type
IOH (Min) (mA)
-5.0
-10.0
5.0
M type L type
-15.0
V type
0.0 0.0 0.5 1.0
1.5
-20.0
VOL (V)
18
CE77 Series
AC CHARACTERISTICS
(VDD = 1.8 V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C) Parameter Delay time Symbol tpd*1 Value Min typ*2 x tmin*3 Typ typ*2 x ttyp*3 Max typ*2 x tmax*3 Unit ns
*1 : Delay time = propagation delay time, enable time, disable time *2 : "typ" is calculated from the cell specification. *3 : Measurement condition Measurement condition VDD = 2.5V 0.2 V, VSS = 0 V, Tj = -40 C to +125 C VDD = 1.8V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C VDD = 1.5V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C tmin 0.60 0.84 1.14 ttyp 1.00 1.57 2.22 tmax 1.64 2.84 4.09
Note : tpd Max is calculated according to the maximum junction temperature (Tj) .
INPUT/OUTPUT CAPACITANCE
(f = 1 MHz, VDD = VI = 0 V, Tj = +25 C) Parameter Input pin Output pin Input/output capacitance Symbol CIN COUT CI/O Value Max 16 Max 16 Max 16 Unit pF pF pF
DESIGN METHOD
Linking a floor plan tool and a logic synthesis tool enables automatic circuit optimization using floor plan information. In addition, CDDM (Clock Driven Design Method) clock tree synthesis tools using floor plan information is also available. Using floor plan information at a pre-layout stage prevents major problems with setup and hold timings which can occur after layout. Using a hierarchical layout method to support larger-scale circuit design considerably shortens the overall design cycle time.
19
CE77 Series
THE NUMBER OF GATES USED AND PACKAGES
1. Counting the number of the gates used
Evaluation of the basic cell count used has revealed some problems including the circuit complexities, difference of the utilization depending on the circuit design scheme (whether it is designed with the logic synthesis) or being unable to achieve the minimum layout with the logically synthesized circuit. To cope with those problems, Fujitsu developed the AREA as a criteria where the circuit size and the layout feasibility is determined. The AREA is a basic cell conceived from the viewpoint of congestion of the wiring; it has been calculated from the actual basic cell count and pin count in units of BC. Estimate method for the frame include the conventional one by the basic cell count and the one by the AREA for more detailed estimate. Hard macro basic cell count and AREA count for unit cell, I/O buffer cell or compiled cell are listed in the respective cell characteristic table.
2. Packages
The table below lists the package types available and the reference number of gates used. Consult Fujitsu for the combination of each package and the availability. CE77 (V-FRAME)
Package Pin 0k & Pitch Pin Count (mm) S Q F P H Q F P P B G A 176 208 240 208 240 256 304 256 0.5 0.5 0.5 0.5 0.5 0.4 0.5 1.27 618k 1000k 274k 803k 965k 1776k 2276k 1776k 7128k 2000k 3000k 4000k 5000k 6000k 7000k 8000k~
Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu.
20
CE77 Series
CE77 (T-FRAME)
Package Pin 0k & Pitch Pin Count (mm) L Q F P H Q F P F B G A P B G A 144 176 208 256 208 240 256 304 144 176 224 228 256 352 420 0.5 0.5 0.5 0.4 0.5 0.5 0.4 0.5 0.8 0.8 0.8 0.75 1.27 1.27 1.27 461k 646k 1375k 2109k 2109k 2678k 3789k 500k 1000k 1500k 1241k 744k 1375k 2109k 2678k 2109k 2109k 4538k 2000k 2500k 3000k 3500k 4000k 4500k 5000k 5500k
Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu.
21
CE77 Series
BASIC CHARACTERISTICS
Transfer characteristics (Typical CMOS input buffer) 1
VDD = 1.95 V VDD = 1.8 V VDD = 1.6 V VDD = 1.5 V VDD = 1.4 V 1.0
Transfer characteristics (Typical CMOS input buffer) 2
3.0 VDD = 2.7 V VDD = 2.5 V VDD = 2.3 V
2.0
2.5 2.0
1.5
VOUT (V)
0.5 0.5 0.0 0.6 0.0 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40
0.7
0.8
0.9
1.0
1.1
VOUT (V)
1.5 1.0
VIN (V)
VIN (V)
Transfer characteristics (Typical schmitt input buffer) 1
2.0 VDD = 1.95 V VDD = 1.8 V VDD = 1.6 V VDD = 1.5 V VDD = 1.4 V VDD =1.95 V 1.4 VDD = 2.7 V VDD = 2.5 V VDD = 2.3 V VDD = 2.7 V VDD = 1.4 V VDD = 1.5 V VDD = 1.6 V 1.2 VDD = 1.8 V 1.3 VDD = 2.5 V
VOUT (V)
1.5
1.0
0.5
0.0 0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VIN (V)
Transfer characteristics (Typical schmitt input buffer) 2
3.0 2.5 2.0
VOUT (V)
1.5 1.0 0.5 0.0 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 VDD = 2.3 V
VIN (V)
(Continued) 22
CE77 Series
(Continued) Transfer characteristics (3.3 V normal CMOS input buffer VDDI = 2.5 V)
3.00 2.50 VDDE = 3.0 V VDDE = 3.3 V 2.00 VDDE = 3.6 V 1.40 1.50
VOUT (V)
1.50 1.00 0.50 0.00
-0.50 1.00
1.10
1.20
1.30
1.60
1.70
VIN (V)
Transfer characteristics (3.3 V normal schmitt input buffer VDDI = 2.5 V)
3.00 2.50 2.00 VDDE = 3.0 V VDDE = 3.3 V
VDDE = 3.6 V
1.50 1.00 0.50
0.00 0.80
1.30
1.80
VDDE = 3.0 V
VIN (V)
VDDE = 3.3 V
VOUT (V)
2.30
VDDE = 3.6 V
23
CE77 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
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