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TECHNICAL NOTE
High Reliability Series Serial EEPROM Series
SPI BUS Serial EEPROMs
Supply voltage 1.8V~5.5V Operating temperature -40C~+85C type
BR25L010-W, BR25L020-W, BR25L040-W, BR25L080-W, BR25L160-W, BR25L320-W, BR25L640-W
Description BR25L-W series is a serial EEPROM of SPI BUS interface method.
Features High speed clock action up to 5MHz (Max.) Wait function by HOLD terminal Part or whole of memory arrays settable as read only memory area by program 1.8 ~ 5.5V single power source action most suitable for battery use Page write mode useful for initial value write at factory shipment Highly reliable connection by Au pad and Au wire For SPI bus interface (CPOL, CPHA) = (0, 0), (1, 1) Auto erase and auto end function at data rewrite Low current consumption At write action (5V) : 1.5mA (Typ.) At read action (5V) : 1.0mA (Typ.) Page write At standby action (5V) : 0.1A (Typ.) Number of Address auto increment function at read action pages Write mistake prevention function Write prohibition at power on Write prohibition by command code (WRDI) Product Write prohibition by WP pin number Write prohibition block setting by status registers (BP1, BP0) Write mistake prevention function at low voltage SOP8, SOP-J8, SSOP-B8, TSSOP-B8, MSOP8 TSSOP-B8J package *1 *2 Data at shipment Memory array : FFh, status register WPEN, BP1, BP0 : 0 Data kept for 40 years Data rewrite up to 1,000,000 times *1 BR25L080/160-W : SOP8, SOP-J8, SSOP-B8, TSSOP-B8 *2 BR25L320/640-W : SOP8, SOP-J8

16 Byte BR25L010-W BR25L020-W BR25L040-W
32 Byte BR25L080-W BR25L160-W BR25L320-W BR25L640-W

BR25L series
Capacity 1Kbit 2Kbit 4Kbit 8Kbit 16Kbit 32Kbit 64Kbit Bit format 128 X 8 256 X 8 512 X 8 1K X 8 2K X 8 4K X 8 8K X 8 Type BR25L010-W BR25L020-W BR25L040-W BR25L080-W BR25L160-W BR25L320-W BR25L640-W
Power source voltage
SOP8
F
SOP-J8
FJ
SSOP-B8
FV
TSSOP-B8
FVT
MSOP8
FVM
TSSOP-B8J
FVJ
1.8 ~ 5.5V 1.8 ~ 5.5V 1.8 ~ 5.5V 1.8 ~ 5.5V 1.8 ~ 5.5V 1.8 ~ 5.5V 1.8 ~ 5.5V Oct. 2008
Absolute maximum ratings (Ta = 25C)
Parameter
Impressed voltage
Recommended action conditions
Unit V
*1 *2 *3
Symbol VCC
Limits -0.3 ~ +6.5
450(SOP8) 450(SOP-J8)
Parameter Power source voltage Input voltage
Symbol VCC Vin
Limits 1.8 ~ 5.5 0 ~ VCC Limits Typ.
Unit V
Permissible dissipation
Pd
300(SSOP-B8) 310(MSOP8) 310(TSSOP-B8J)
mW
Memory cell characteristics (Ta=25C, VCC=1.8 ~ 5.5V)
Parameter Number of data rewrite times Data hold years
*1 *1
330(TSSOP-B8) *4
*5 *6
Min. 1,000,000 40
Max.
Unit Times Years
- -
- -
Storage temperature range Operating temperature range
Tstg Topr
Terminal voltage
-
-65 ~ +125 -40 ~ +85 -0.3 ~ VCC+0.3
C C V
*1:Not 100% TESTED
Input / output capacity (Ta=25C, frequency=5MHz)
Parameter Input capacity *1 Output capacity *1 Symbol Conditions CIN VIN=GND COUT VOUT=GND Min.
When using at Ta = 25C or higher, 4.5mW (*1, *2), 3.0mW (*3), 3.3mW(*4), 3.1mW (*5, *6) to be reduced per 1C
- -
Max. 8 8
Unit pF pF
*1:Not 100% TESTED
Electrical characteristics (Unless otherwise specified, Ta = -40 ~ +85C, VCC = 1.8 ~ 5.5V)
Parameter "H" input voltage 1 "L" input voltage 1 "L" output voltage 1 "L" output voltage 2 "H" output voltage 1 "H" output voltage 2 Input leak current Output leak current Symbol VIH1 VIL1 VOL1 VOL2 VOH1 VOH2 ILI ILO ICC1 Limits Typ. Min. 0.7x - VCC -0.3 0 0 VCC -0.5 VCC -0.2 -1 -1 Max. VCC +0.3 0.3x VCC 0.4 0.2 VCC VCC 1 1 1.0 Unit V V V V V V A A mA 1.8VCC5.5V 1.8VCC5.5V IOL=2.1mA(VCC=2.5V ~ 5.5V) IOL=150A(VCC=1.8V ~ 2.5V) IOH=-0.4mA(VCC=2.5V ~ 5.5V) IOH=-100A(VCC=1.8V ~ 2.5V) VIN=0 ~ VCC VOUT=0 ~ VCC,CS=VCC VCC=1.8V,fSCK=2MHz,tE/W=5ms Byte write Page write Write status register VCC=2.5V,fSCK=5MHz,tE/W=5ms Byte write Page write Write status register VCC=5.5V,fSCK=5MHz,tE/W=5ms Byte write Page write Write status register VCC=2.5V,fSCK=5MHz Read Read status register VCC=5.5V,fSCK=5MHz Read Read status register VCC=5.5V CS=HOLD=WP=VCC,SCK=SI=VCC or =GND,SO=OPEN
* Radiation resistance design is not made.
Conditions
- - - - - - - -
-
Current consumption at write action
ICC2
-
-
2.0
mA
ICC3
-
-
3.0
mA
Current consumption at read action
ICC4
- - -
- - -
1.5
mA
ICC5 Standby current ISB
2.0 2
mA A
Block diagram
CS INSTRUCTION DECODE CONTROL CLOCK SCK GENERATION WRITE INHIBITION HIGH VOLTAGE GENERATOR VOLTAGE DETECTION
SI
INSTRUCTION REGISTER ADDRESS REGISTER DATA REGISTER ADDRESS DECODER READ/WRITE AMP
7~13bit *1
STATUS REGISTER
7~13bit *1
HOLD
1K~64K EEPROM
8bit
WP
8bit
*1 7bit : BR25L010-W 8bit : BR25L020-W 9bit : BR25L040-W 10bit : BR25L080-W 11bit : BR25L160-W 12bit : BR25L320-W 13bit : BR25L640-W
SO
Fig.1 Block diagram
2/16
Pin assignment and description
VCC HOLD SCK SI
Terminal name Input/output
VCC GND CS SCK SI SO
Function
Power source to be connected All input / output reference voltage, 0V Chip select input Serial clock input Start bit, ope code, address, and serial data input Serial data output Hold input Command communications may be suspended temporarily (HOLD status). Write protect input Write command is prohibited.*1 Write status register command is prohibited.
*1:BR25L010/020/040-W
BR25L010-W BR25L020-W BR25L040-W BR25L080-W BR25L160-W BR25L320-W BR25L640-W
CS SO WP GND
Input Input Input Output Input Input
- -
HOLD WP
Fig. 2 Pin assignment diagram
Operating timing characteristics (Ta = -40 ~ +85C, unless otherwise specified, load capacity CL1 100pF)
Parameter Symbol 1.8VCC<2.5V 2.5VCC<5.5V Unit Min. Typ. Max. Min. Typ. Max. 2 5 MHz - - - - 200 85 - - - - ns 85 200 - - - - ns 85 200 - - - - ns ns 200 - - 90 - - ns 200 - - 85 - - 90 200 - - - - ns 90 200 - - - - ns 20 40 - - - - ns 40 50 - - - - ns ns - - 150 - - 70
CS
Sync data input / output timing
tCS tCSS
tSCKS SCK
tSCKWL tSCKWH
tRC
tFC
fSCK SCK frequency tSCKWH SCK high time tSCKWL SCK low time tCS CS high time tCSS CS setup time tCSH CS hold time SCK setup time tSCKS SCK hold time tSCKH tDIS SI setup time tDIH SI hold time tPD1 Data output delay time 1 Data output delay time 2 tPD2 (CL2=30pF) Output hold time Output disable time HOLD setting setup time HOLD setting hold time HOLD release setup time HOLD release hold time Time from HOLD to output High-Z Time from HOLD to output change SCK rise time SCK fall time OUTPUT rise time OUTPUT fall time Write time
*1
tDIS tDIH SI SO High-Z
Fig. 3 Input timing
SI is taken into IC inside in sync with data rise edge of SCK. Input address and data from the most significant bit MSB.
tCS CS SCK SI SO tCSH tSCKH
-
0
- - - - - - - - - - - - - -
145
-
0
- - - - - - - - - - - - - -
55
ns ns ns ns ns ns ns ns ns s s ns ns ms
tOH tOZ tHFS tHFH tHRS tHRH tHOZ tHPD tRC tFC tRO tFO tE/W
-
250
-
100
-
120 90 120 140
-
60 40 60 70
tPD
tOH
tRO,tFO tOZ
High-Z
- - - -
250 150 1 1 100 100 5
- - - -
100 70 1 1 50 50 5
Fig. 4 Input / output timing
SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB.
"H" "L" tHFS tHFH tHRS tHRH tDIS
CS SCK SI SO
- - - - - - -
- - - - - - -
n+1 tHOZ Dn+1 Dn High-Z
n tHPD Dn
n-1 Dn-1
HOLD
Fig. 5 HOLD timing
*1
*1
*1
*1NOT 100% TESTED
AC measurement conditions
Parameter Load capacity 1 Load capacity 2 Input rise time Input fall time Input voltage Input / output judgment voltage Symbol CL1 CL2 Min. Limits Unit Typ. Max. 100 pF - - - - 30 pF - - 50 ns - - 50 ns 0.2VCC/0.8VCC V 0.3VCC/0.7VCC V
- - - -
3/16
Characteristic data (The following characteristic data are Typ. values.)
6 5 4 VIH[V] VIL[V] 3 2 1 00 Ta=85C Ta=25C Ta=-40C 1 2 VCC[V] 3 4 5 6 0 0 1 2 VCC[V] SPEC 6 5 4 3 2 SPEC 1 SPEC 3 4 5 6 0 0 1 2 IOL[mA] 3 0.2 Ta=-40C 4 5 6
VOL[V]
1
0.8
Ta=85C Ta=25C Ta=-40C
0.6
Ta=85C Ta=25C
0.4
Fig.6 "H" input voltage VIH(CS,SCK,SI,HOLD,WP)
Fig.7 "L" input voltage VIL(CS,SCK,SI,HOLD,WP)
Fig.8 "L" output voltage VOL-IOL(VCC=1.8V)
2
1 Ta=-40C
2.6 Ta=-40C
1.8
0.8
2.4
VOH[V]
1.6 SPEC 1.4
VOL[V]
VOH[V]
0.6 Ta=25C Ta=85C SPEC 0.4 Ta=85C Ta=25C
2.2 SPEC 2
Ta=25C Ta=85C
0.2 Ta=-40C 0 0.4 IOH[mA] 0.8 0 0 1 2 IOL[mA] 3 4 5
1.2
1.8
0
0.4 IOH[mA]
0.8
Fig.9 "H" output voltage VOH-IOH(VCC=1.8V)
Fig.10 "L" output voltage VOL-IOL(VCC=2.5V)
Fig.11 "H" output voltage VOH-IOH(VCC=2.5V)
1.2 SPEC 1 0.8 ILO[ A] ILI[ A] 0.8 0.4 0.2 0
1.2 SPEC 1
4 fSCK=5MHz 3 DATA=55h
VCC=2.5V 2mA VCC=5.5V 3mA
SPEC
0.8 ICC2,3[mA] 0.6 0.4 0.2 0 2 SPEC Ta=25C Ta=-40C 1 Ta=85C 6 0 0 1 2 VCC[V] 3 4 5 6
Ta=85C Ta=25C Ta=-40C
Ta=85C Ta=25C Ta=-40C 0 1 2 VCC[V] 3 4 5
0
1
2 VCC[V]
3
4
5
6
Fig.12 Input leak current ILI(CS,SCK,SI,WP,HOLD)
Fig.13 Output leak current ILO(SO)
Fig.14 Current consumption at WRITE operation ICC1,2,3(WRITE,PAGE WRITE,WRSR,fSCK=5MHz) BR25L010-W,BR25L020-W,BR25L040-W
2.5 fSCK=5MHz 2 DATA=55h
Vcc=2.5V 1.5mA Vcc=5.5V 2.0mA SPEC
2.5 SPEC 2
100 Ta=-40C
Ta=25C
SPEC ICC4,5[mA] Ta=25C 1 Ta=85C fSCK[MHz] ISB[A] 1.5 Ta=-40C 1.5
10 SPEC 1 SPEC
Ta=85C
1 Ta=85C Ta=25C Ta=-40C
0.5
0.5
0
0
1
2 VCC[V]
3
4
5
6
0
0
1
2 VCC[V]
3
4
5
6
0.1
0
1
2 VCC[V]
3
4
5
6
Fig.15 Consumption current at READ operation ICC4,5(READ,WRSR,fSK=5MHz)
Fig.16 Consumption current at standby operation ISB
Fig.17 SCK frequency fSCK
250 SPEC 200
250 SPEC 200
250 SPEC 200
tSCKWL[ns]
tSCKWH[ns]
tCS[ns]
150
150
150 SPEC Ta=25C Ta=-40C
100 Ta=-40C
SPEC Ta=85C Ta=25C
100 Ta=25C
SPEC Ta=-40C
100
50
50
50 Ta=85C 0 1 2 VCC[V] 3 4 5 6
Ta=85C
0
0
1
2 VCC[V]
3
4
5
6
0
0
0
1
2 VCC[V]
3
4
5
6
Fig.18 tSCK high time tSCKWH
Fig.19 SCK low time tSCKWL
Fig.20 CS high time tCS
4/16
250 SPEC 200 150 tCSS[ns] tCSH[ns] 100 50 0 -50 SPEC
250
60
200
SPEC
40
SPEC
100
SPEC Ta=85C Ta=25C
tDIS[ns]
150
20
SPEC
Ta=85C Ta=25C Ta=-40C 50
0 Ta=85C
Ta=-40C
-20 Ta=-40C Ta=25C
0
1
2
3 VCC[V]
4
5
6
0
0
1
2
3 VCC[V]
4
5
6
-40
0
1
2
3 VCC[V]
4
5
6
Fig.21 CS setup time tCSS
Fig.22 CS hold time tCSH
Fig.23 SI setup time tDIS
60 50 40 tDIH[ns] tPD1[ns] SPEC SPEC
200 SPEC 150 tPD2[ns]
200
150
SPEC
30 Ta=85C Ta=-40C 20
100 Ta=85C SPEC
100
Ta=85C
SPEC 50 Ta=-40C Ta=25C 6 0 0 1 2 3 VCC[V] 4 5 6 0 0 1 50 Ta=25C Ta=-40C 2 3 VCC[V] 4 5 6
10 0
Ta=25C 0 1 2 3 VCC[V] 4 5
Fig.24 SI hold time tDIH
Fig.25 Data output delay time tPD1(CL=100pF)
Fig.26 Data output delay time tPD2(CL=30pF)
300 250 200 tOZ[ns] 150 SPEC 100 Ta=85C 50 Ta=-40C 0 0 1 2 3 VCC[V] 4 5 6 Ta=25C SPEC
140 120 100 tHFH[ns] 80 60 40 20 0 -20 0 1 2 Ta=85C SPEC
150 120 90 tHRH[ns] 60 30 Ta=25C Ta=-40C 3 VCC[V] 4 5 6 0 -30 Ta=-40C Ta=85C Ta=25C SPEC
SPEC
SPEC
0
1
2
3 VCC[V]
4
5
6
Fig.27 Output disable time tOZ
Fig.28 HOLD setting hold time tHFH
Fig.29 HOLD release hold time tHRH
300 250 200 SPEC
160 SPEC 120 SPEC
120 SPEC 90
tHPD[ns]
tHFH[ns]
tRO[ns]
80
150 100 50 Ta=-40C 0 0 1 2
SPEC
60 Ta=85C
40 Ta=85C Ta=25C Ta=-40C 3 VCC[V] 4 5 6
SPEC
Ta=85C Ta=25C
0
30
Ta=25C
3 VCC[V]
4
5
6
-40
0
1
2
0
Ta=-40C 0 1 2 3 VCC[V] 4 5 6
Fig.30 Time from HOLD to output High-Z tHOZ
Fig.31 Time from HOLD to output change tHPD
Fig.32 Output rise time tRO
120 SPEC 90
10
8
60
SPEC Ta=85C
tE/W[ms]
tFO[ns]
6
SPEC Ta=-40C
4
30
Ta=25C Ta=-40C
2
Ta=85C
Ta=25C
0
0
1
2
3 VCC[V]
4
5
6
0
0
1
2
3 VCC[V]
4
5
6
Fig.33 Output fall time
Fig.34 Write cycle time tE/W
5/16
Features Status registers This IC has status registers. The status registers are of 8 bits and express the following parameters. BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are valid even when power source is turned off. Rewrite characteristics and data hold time are same as characteristics of the EEPROM. WEN can be set by write enable command and write disable command. WEN becomes write disable status when power source is turned off. R/B is for write confirmation, therefore cannot be set externally. The value of status register can be read by read status command. Status registers
Product number BR25L010-W BR25L020-W BR25L040-W BR25L080-W BR25L160-W BR25L320-W BR25L640-W
Memory location
bit 7 1
bit 6 1
bit 5 1
bit 4 1
bit 3 BP1
bit 2 BP0
bit 1 WEN
bit 0 R/B
WPEN
0
0
0
BP1
BP0
WEN
R/B
bit WPEN BP1 BP0 WEN R/B
Function WP pin enable / disable designation bit
WPEN = 0 = invalid WPEN = 1 = valid
Contents This enables / disables the functions of WP pin. This designates the write disable area of EEPROM. Write designation areas of product numbers are shown below.
EEPROM EEPROM Register Register
EEPROM write disable block designation bit Write and write status register write enable / disable status confirmation bit
WEN = 0 = prohibited WEN = 1 = permitted R/B=0=READY R/B=1=BUSY
Write cycle status (READY / BUSY) status confirmation bit
Write disable block setting
BP1 0 0 1 1 BP0 0 1 0 1 Write disable block BR25L010-W None 60h-7Fh 40h-7Fh 00h-7Fh BR25L020-W None C0h-FFh 80h-FFh 00h-FFh BR25L040-W None 180h-1FFh 100h-1FFh 000h-1FFh BR25L080-W None 300h-3FFh 200h-3FFh 000h-3FFh BR25L160-W None 600h-7FFh 400h-7FFh 000h-7FFh BR25L320-W None C00h-FFFh 800h-FFFh 000h-FFFh BR25L640-W None 1800h-1FFFh 1000h-1FFFh 0000h-1FFFh
WP pin By setting WP = LOW, write command is prohibited. As for BR25L080, 160, 320, 640-W, only when WPEN bit is set "1", the WP pin functions become valid. And the write command to be disabled at this moment is WRSR. As for BR25L010, 020, 040-W, both WRITE and WRSR commands are prohibited. However, when write cycle is in execution, no interruption can be made.
Product number BR25L010-W BR25L020-W BR25L040-W BR25L080-W BR25L160-W BR25L320-W BR25L640-W Prohibition possible but WPEN bit "1" Prohibition impossible WRSR Prohibition possible WRITE Prohibition possible
HOLD pin By HOLD pin, data transfer can be interrupted. When SCK = "1", by making HOLD from "1" into "0", data transfer to EEPROM is interrupted. When SCK = "0", by making HOLD from "0" into "1", data transfer is restarted.
6/16
Command mode
Ope code Command Contents BR25L010-W BR25L020-W 0000 0000 0000 0000 0000 0000 * 110 * 100 * 011 * 010 * 101 * 001 BR25L040-W 0000 0000 0000 0000 0000 0000 * 110 * 100 A8011 A8010 * 101 * 001 BR25L080-W BR25L160-W BR25L320-W BR25L640-W 0000 0000 0000 0000 0000 0000 0110 0100 0011 0010 0101 0001
WREN Write enable WRDI READ Write disable Read
Write enable command Write disable command Read command Write command Status register read command Status register write command
WRITE Write RDSR Read status register
WRSR Write status register
Timing chart 1. Write enable (WREN) / disable (WRDI) cycle
1.WREN (WRITE ENABLE) : Write enable
CS SCK 0 1 2 3 4 5 6 7
SI
0
0
0
0
*1
1
1
0
SO
High-Z
Fig. 35 Write enable command
*1 BR25L010/020/040-W=Don't care BR25L080/160/320/640-W="0" input
1.WRDI (WRITE DISABLE) : Write disable
CS SCK 0 1 2 3 4 5 6 7
SI
0
0
0
0
*1
1
0
0
SO
High-Z
Fig. 36 Write disable
*1 BR25L010/020/040-W=Don't care BR25L080/160/320/640-W="0" input
This IC has write enable status and write disable status. It is set to write enable status by write enable command, and it is set to write disable status by write disable command. As for these commands, set CS LOW, and then input the respective ope codes. The respective commands accept command at the 7-th clock rise. Even with input over 7 clocks, command becomes valid. When to carry out write and write status register command, it is necessary to set write enable status by the write enable command. If write or write status register command is input in the write disable status, commands are cancelled. And even in the write enable status, once write and write status register command is executed once, it gets in the write disable status. After power on, this IC is in write disable status.
7/16
2. Read command (READ)
CS
SCK
0
1
2
3
4
5
6
7
8
9
10
11
14
15
16
17
22
Product number BR25L010-W BR25L020-W BR25L040-W
Address length A6-A0 A7-A0 A8-A0
SI
0
0
0
0
*1
0
1
1
A7
A6
A5
A4
A1
A0
SO
High-Z
D7
D6
D2
D1
D0
Fig. 37 Read command (BR25L010/020/040-W) * 1 BR25L010/020-W=Don't care BR25L040-W=A8
CS
SCK
0
1
2
3
4
5
6
7
8
23
24
30
Product number BR25L080-W BR25L160-W BR25L320-W BR25L640-W
Address length A9-A0 A10-A0 A11-A0 A12-A0
SI
0
0
0
0
0
0
1
1
*
*
*
A12
A1
A0
SO
High-Z
D7
D6
D2
D1
D0
Fig. 38 Read command (BR25L080/160/320/640-W)
* =Don't care
By read command, data of EEPROM can be read. As for this command, set CS LOW, then input address after read ope code. EEPROM starts data output of the designated address. Data output is started from SCK fall of 15/23*1 clock, and from D7 to D0 sequentially. This IC has increment read function. After output of data for 1 byte (8 bits), by continuing input of SCK, data of the next address can be read. Increment read can read all the addresses of EEPROM. After reading data of the most significant address, by continuing increment read, data of the most insignificant address is read.
* =Don't care
* 1 BR25L010/020/040-W=15 clocks BR25L080/160/320/640-W=23 clocks
3. Write command (WRITE)
CS
Product number
0 1 2 3 4 5 6 7 8 15 16 22 23
Address length A6-A0 A7-A0 A8-A0
SCK
BR25L010-W BR25L020-W BR25L040-W
SI SO
0
0
0
0
*1
0
1
0
A7
A6
A5
A4
A1
A0
D7
D6
D2
D1
D0
High-Z
Fig.39 Write command (BR25L010/020/040-W)
CS
* 1 BR25L010/020-W=Don't care BR25L040-W=A8
Product number
0 1 2 3 4 5 6 7 8 23 24 30 31
Address length A9-A0 A10-A0 A11-A0 A12-A0
SCK
BR25L080-W
SI SO
0 0 0 0 0 0 1 0
*
*
*
A12
A1
A0
D7
D6
D2
D1
D0
BR25L160-W BR25L320-W BR25L640-W
High-Z
Fig.40 Write command (BR25L080/160/320/640-W)
* =Don't care
By write command, data of EEPROM can be written. As for this command, set CS LOW, then input address and data after write ope code. Then, by making CS HIGH, the EEPROM starts writing. The write time of EEPROM requires time of tE/W (Max 5ms). During tE/W, other than status read command is not accepted. Start CS after taking the last data (D0), and before the next SCL clock starts. At other timing, write command is not executed, and this write command is cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input without starting CS, data up to 16/32*1 bytes can be written for one tE/W. In page write, the insignificant 4/5*2 bit of the designated address is incremented internally at every time when data of 1 byte is input, and data is written to respective addresses. When data of the maximum bytes or higher is input, address rolls over, and previously input data is overwritten.
* 1 BR25L010/020/040-W=16 bytes at maximum BR25L080/160/320/640-W=32 bytes at maximum * 2 BR25L010/020/040-W=Insignificant 4 bits BR25L080/160/320/640-W=Insignificant 5 bits
8/16
4. Status register write / read command
CS
SCK
0
1
2
3
4
5
6
7
8
bit7
9
bit6
10
bit5
11
bit4
12
bit3
13
bit2
14
bit1
15
bit0
SI
0
0
0
0
*
0
0
1
*
*
*
*
BP1 BP0
*
*
SO
High-Z
* =Don't care
Fig.41 Status register write command (BR25L010/020/040-W)
CS
SCK
0
1
2
3
4
5
6
7
8
bit7
9
bit6
10
bit5
11
bit4
12
bit3
13
bit2
14
bit1
15
bit0
SI
0
0
0
0
0
0
0
1
WPEN
*
*
*
BP1 BP0
*
*
SO
High-Z
* =Don't care
Fig.42 Status register write command (BR25L080/160/320/640-W)
Write status register command can write status register data. The data the can be written by this command are 2 bits *1, that is, BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be set. As for this command, set CS LOW, and input ope code of write status register, and input data. Then, by making CS HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CS rise, start CS after taking the last data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array. (Refer to the write disable block setting table.) To the write disabled block, write cannot be made, and only read can be made.
* 3 bits including BR25L080, 160, 320, 640-W WPEN (bit7)
CS
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SI
0
0
0
0
*
1
0
1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SO
High-Z
1
1
1
1
BP1 BP0 WEN R/B
Fig.43 Status register read command (BR25L010/020/040-W)
* =Don't care
CS
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SI
0
0
0
0
0
1
0
1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SO
High-Z
WPEN
0
0
0
BP1 BP0 WEN
R/B
Fig.44 Status register read command (BR25L080/160/320/640-W)
9/16
At standby Current at standby Set CS "H", and be sure to set SCK, SI, WP, HOLD input "L" or "H". Do not input intermediate electric potential. Timing As shown in Fig. 45, at standby, when SCK is "H", even if CS is fallen, SI status is not read at fall edge. SI status is read at SCK rise edge after fall of CS. At standby and at power ON/OFF, set CS "H" status.
Even if CS is fallen at SCL = SI = "H", SI status is not read at that edge.
CS
Command start here. SI is read.
SCK
0
1
2
SI
Fig.45 Operating timing
WP cancel valid area WP is normally fixed to "H" or "L" for use, but when WP is controlled so as to cancel write status register command and write command, pay attention to the following WP valid timing. While write or write status register command is executed, by setting WP = "L" in cancel valid area, command can be cancelled. The area from command ope code before CS rise at internal automatic write start becomes the cancel valid area. However, once write is started, any input cannot be cancelled. WP input becomes Don't Care, and cancellation becomes invalid.
SCK
15
16
CS
Ope code
WP cancel invalid area invalid
Data
WP cancel invalid area
tE/W data write time
WP cancel invalid area
Fig.46 WP valid timing (WRSR)
Ope code
WP cancel invalid area invalid
Address
Data
tE/W data write time
WP cancel invalid area
WP cancel invalid area valid
Fig.47 WP valid timing (WRITE)
HOLD pin By HOLD pin, command communication can be stopped temporarily. (HOLD status) The HOLD pin carries out command communications normally when it is HIGH. To get in HOLD status, at command communication, when SCK = LOW, set the HOLD pin LOW. At HOLD status, SCK and SI become Don't Care, and SO becomes high impedance (High-Z). To release the HOLD status, set the HOLD pin HIGH when SCK = LOW. After that, communication can be restarted from the point before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of HOLD status, by starting A4 address input, read can be restarted. When in HOLD status, leave CS LOW. When it is set CS = HIGH in HOLD status, the IC is reset, therefore communication after that cannot be restarted.
10/16
Method to cancel each command READ Method to cancel : cancel by CS = "H"
Ope code 8 bits Address 8 bits /16bits Data 8 bits
Cancel available in all areas of read mode
Fig.48 READ cancel valid timing
RDSR Method to cancel : cancel by CS = "H"
Ope code 8 bits
Data 8 bits
Cancel available in all areas of read mode
Fig.49 RDSR cancel valid timing
WRITE, PAGE WRITE a : Ope code, address input area. Cancellation is available by CS = "H". b : Data input area (D7 ~ D1 input area) Cancellation is available by CS = "H". c : Data input area (D0 area) When CS is started, write starts. After CS rise, cancellation cannot be made by any means. d : tE/W area Cancellation is available by CS = "H". However, when write starts (CS is started) in the area c, cancellation cannot be made by any means. And, by inputting on SCK clock, cancellation cannot be made. In page write mode, there is write enable area at every 8 clocks.
Ope code 8 bits
Address 8 bits a
Data (n) 8 bits b c
tE/W
d
Fig.50 WRITE cancel valid timing
SCK
SI
D7
D6
D5
D4
D3
D2
D1
D0
b
c
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again. Note 2) If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is recommended to fall in SCK = "L" area. As for SCK rise, assure timing of tCSS / tCSH or higher. WRSR a : From ope code to 15 clock rise Cancel by CS = "H". b : From 15 clock rise to 16 clock rise (write enable area) When CS is started, write starts. After CS rise, cancellation cannot be made by any means. c : After 16 clock rise Cancel by CS = "H". However, when write starts (CS is started) in the area b, cancellation cannot be made by any means. And, by inputting on SCK clock, cancellation cannot be made.
SCK
14 15 16 17
SI
D1
D0
a Ope code 8 bit a Address 8 bit
b
c tE/W
c b
Fig.51 WRSR cancel valid timing
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again. Note 2) If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is recommended to fall in SCK = "L" area. As for SCK rise, assure timing of tCSS/tCSH or higher.
WREN/WRDI a : From ope code to clock rise, cancel by CS = "H". b : Cancellation is not available when CS is started after 7 clock.
SCK
7
8
9
a Ope code 8 bit a
b
b
Fig.52 WREN / WRDI cancel valid timing
11/16
High speed operation In order to realize stable high speed operations, pay attention to the following input / output pin conditions.
Input pin pull up, pull down resistance When to attach pull up, pull down resistance to EEPROM input pin, select an appropriate value for the microcontroller VOL, IOL from VIL characteristics of this IC.
Pull up resistance
RPU VOLM
VCC - VOLM IOLM VILE
Microcontroller VOLM "L" output
IOHM
EEPROM VILE "L" input
Example) When Vcc = 5V, VILM = 1.5V, VOLM = 0.4V, IOLM = 2mA, from the equation , RPU RPU
Fig.53 Pull up resistance
5-0.4 2 X 10-3 2.3[k]
With the value of Rpu to satisfy the above equation, VOLM becomes 0.4V or higher, and with VILE (= 1.5V), the equation is also satisfied. VILM : EEPROM VIH specifications VOLM : Microcontroller VOL specifications IOLM : Microcontroller IOL specifications
And, in order to prevent malfunction, mistake write at power ON/OFF, be sure to make CS pull up.
Pull down resistance
EEPROM VOHM IOHM VIHE
RPD VOHM
VOHM IOHM VIHE
Example) When Vcc = 5V, VOHM = Vcc - 0.5V, IOHM = 0.4mA, , VIHM = Vcc X 0.7V, from the equation Fig.54 Pull down resistance RPD RPD
5-0.5 0.4 X 10-3 11.3[k]
Further, by amplitude VIHE, VILE of signal input to EEPROM, operation speed changes. By inputting signal of amplitude of VCC / GND level to input, more stable high speed operations can be realized. On the contrary, when amplitude of 0.8VCC / 0.2VCC is input, operation speed becomes slow.
12/16
In order to realize more stable high speed operation, it is recommended to make the values of RPU, RPD as large as possible, and make the amplitude of signal input to EEPROM close to the amplitude of VCC / GND level. (*1 At this moment, operating timing guaranteed value is guaranteed.)
tPD-VIL characteristics
80
75
70
tPD [ns]
65
60
55 0 0.2 0.4 0.6
VCC=1.8V Ta=25C VIH=VCC CL=100pF
0.8 1
VIL[V]
Fig.55 VIL dependency of data output delay time
SO load capacity condition Load capacity of SO output pin affects upon delay characteristic of SO output. (Data output delay time, time from HOLD to High-Z) In order to make output delay characteristic into higher speed, make SO load capacity small. In concrete, "Do not connect many devices to SO bus", "Make the wire between the controller and EEPROM short", and so forth.
tPD-CL characteristics
80
VCC=1.8V Ta=25C VIH/VIL=0.8VCC/0.2VCC
70
EEPROM SO
tPD [ns]
60
CL
50
40 0 20 40 60 80 100 120
CL [V]
Fig.56 SO load dependency of data output delay time
Other cautions Make the wire length from the microcontroller to EEPROM input signal same length, in order to prevent setup / hold violation to EEPROM, owing to difference of wire length of each input.
13/16
Equivalent circuit Output circuit
SO
OEint.
Fig.57 SO output equivalent circuit
Input circuit
RESETint.
CS
Fig.58 CS input equivalent circuit
SCK
SI
Fig.59 SCK input equivalent circuit
Fig.60 SI input equivalent circuit
HOLD
WP
Fig.61 HOLD input equivalent circuit
Fig.62 WP input equivalent circuit
14/16
Notes on power ON/OFF
At power ON/OFF, set CS "H" (= VCC). When CS is "L", this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause malfunction, mistake write or so. To prevent these, at power ON, set CS "H". (When CS is in "H" status, all inputs are canceled.)
Vcc Vcc GND Vcc CS GND Good example Bad example
Fig.63 CS timing at power ON/OFF
(Good example)
(Bad example)
CS terminal is pulled up to VCC. At power OFF, take 10ms or higher before re supply. If power is turned on without observing this condition, the IC internal circuit may not be reset, which please note. CS terminal is "L" at power ON/OFF. In this case, CS always becomes "L" (active status), and EEPROM may have malfunction, mistake write owing to noises and the likes. Even when CS input is High-Z, the status becomes like this case, which please note.
PORcircuit
This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the recommended conditions of the following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to noises and the likes.
tR VCC Recommended conditions of tR, tOFF, Vbot tR tOFF 0 Vbot tOFF Vbot 10ms or below 10ms or higher 0.3V or below 100ms or below 10ms or higher 0.2V or below
Fig.64 Rise waveform
Noise countermeasures Vcc noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
SCK noise
When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement. To avoid this, a Schmitt trigger circuit is built in SCK input. The hysteresis width of this circuit is set about 0.2V, if noises exist at SCK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SCK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible.
WP noise
During execution of write status register command, if there exist noises on WP pin, mistake in recognition may occur and forcible cancellation may result, which please note. To avoid this, a Schmitt trigger circuit is built in WP input. In the same manner, a Schmitt trigger circuit is built in SI input and HOLD input too.
Cautions on use
(1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5) Heat design In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal short circuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
15/16
Selection of order type
BR
Rohm type name
25
L
010
F
-W
E2
Package specifications E2 : reel shape emboss taping TR : reel shape emboss taping (MSOP8 package only)
BUS type Operating temperature Capacity Package type Double cell 25:SPI 010= 1 K F : SOP8 L : -40 85 020= 2 K FJ : SOP-J8 H : -40 125 040= 4 K FV : SSOP-B8 080= 8 K FVT :TSSOP-B8 160= 16K FVM : MSOP8 320= 32K FVJ : TSSOP-B8J 640= 64K Package specifications SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J

SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J
* SOP8
5.00.2 8 6.20.3 4.40.2 5
* SOP-J8
4.90.2 8765 0.3Min. 0.45Min. 6.00.3 3.90.2
* SSOP-B8
3.00.2 8 6.40.3 4.40.2 5 0.3Min.
* TSSOP-B8
3.00.1 85 0.50.15 1.00.2 6.40.2 4.40.1
* TSSOP-B8J
4.90.2 3.00.1 0.450.15 0.950.2 3.00.1 85
Package type Package quantity Package direction
Emboss taping 2500pcs E2 (When the reel is gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of the product is at the left top.)
1.150.1
1.50.1
0.1
0.17 0.11 1.27 0.420.1 0.1
+0.1 -0.05
1.3750.1 0.175
0.10.05
1
4
1234
1 0.20.1 0.1
4
0.150.1 0.1 1.00.1
1
4
1 0.145 -0.03 0.08 S 0.850.05
+0.05
4
0.145
+0.05 -0.03
1234
1234
1234
1234
1234
1234
1234
1234
0.10.05
0.08 S 0.32 0.65
+0.05 -0.04
1.27 0.420.1
0.220.1 0.65
0.245 0.65
+0.05 -0.04
(0.52)
(Unit : mm)
* For ordering, specify a number of multiples of the package quantity.
Reel
Pin No.1
Pulling side
MSOP8

2.9 0.1 4.0 0.2 8 2.8 0.1 5 0.29 0.15 0.6 0.2
MSOP8
Package type Package quantity Package direction Emboss taping 3000pcs TR (When the reel is gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of the product is at the right top.)
0.475 0.9Max. 0.75 0.05 0.08 0.05
1
4
0.145 +0.05 -0.03 0.22 +0.05 -0.04 0.08 M

0.65
0.08 S

(Unit : mm)
* For ordering, specify a number of multiples of the package quantity.
Reel
Pin No.1
Pulling side
Catalog No. 08T565A '08.10 ROHM(c)
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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