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PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
Rev. 03 -- 20 November 2008 Product data sheet
1. Product profile
1.1 General description
SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Higher operating power due to low thermal resistance Low conduction losses due to low on-state resistance Suitable for high frequency applications due to fast switching characteristics
1.3 Applications
DC-to-DC converters Switched-mode power supplies
1.4 Quick reference data
Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 C; VGS = 10 V; see Figure 1; see Figure 2 Tmb = 25 C; see Figure 3 Min Typ Max 100 47 150 Unit V A W drain-source voltage Tj 25 C; Tj 175 C drain current total power dissipation gate-drain charge Symbol Parameter
Dynamic characteristics QGD VGS = 10 V; ID = 45 A; VDS = 80 V; Tj = 25 C; see Figure 12 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 10; see Figure 11 25 nC
Static characteristics RDSon drain-source on-state resistance 22 25 m
NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
2. Pinning information
Table 2. Pin 1 2 3 mb Pinning information Symbol G D S D Description gate drain source mounting base; connected to drain
2 1 3
Simplified outline [1]
mb
Graphic symbol
D
G
mbb076
S
SOT428 (SC-63; DPAK)
[1] It is not possible to make connection to pin 2.
3. Ordering information
Table 3. Ordering information Type number Package Name Description PSMN025-100D SC-63; plastic single-ended surface-mounted package (DPAK); 3 leads (one DPAK lead cropped)
Version SOT428
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C pulsed; Tmb = 25 C VGS = 10 V; Tmb = 100 C; see Figure 1 VGS = 10 V; Tmb = 25 C; see Figure 1; see Figure 2 pulsed; Tmb = 25 C; see Figure 2 Tmb = 25 C; see Figure 3 Conditions Tj 25 C; Tj 175 C Tj 175 C; Tj 25 C; RGS = 20 k Min -20 -55 -55 Max 100 100 20 33 47 188 150 175 175 47 188 Unit V V V A A A W C C A A
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
PSMN025-100D_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 20 November 2008
2 of 11
NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
Table 4. Symbol EDS(AL)S
Limiting values ...continued Parameter Conditions Min Max 260 Unit mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 40 A; Vsup 25 V; drain-source avalanche unclamped; tp = 100 s; RGS = 50 energy non-repetitive avalanche current Vsup 25 V; VGS = 10 V; Tj(init) = 25 C; RGS = 50 ; unclamped; see Figure 4
IAS
-
47
A
Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150
lma016
1000
Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID
lma017
100
tp = 10 us 100 us
10 D.C. 1
1 ms 10 ms 100 ms
175
0.1 1 10 100 Drain-Source Voltage, VDS (V) 1000
Fig 1.
Continuous drain current as a function of mounting base temperature
Fig 2.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
Maximum Avalanche Current, IAS (A)
lma029
Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150
lma015
100
25 C
10
Tj prior to avalanche = 150 C
1 0.001
0.01
0.1 Avalanche time, tAV (ms)
1
10
175
Fig 3.
Normalized total power dissipation as a function of mounting base temperature
Fig 4.
Maximum permissible non-repetitive avalanche current as a function of avalanche time
PSMN025-100D_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 20 November 2008
3 of 11
NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-a) Rth(j-mb) Thermal characteristics Parameter Conditions Min Typ 50 Max 1 Unit K/W K/W thermal resistance from SOT428 package; printed-circuit board junction to ambient mounted; minimum footprint thermal resistance from see Figure 5 junction to mounting base
1
Transient thermal impedance, Zth j-mb (K/W) D = 0.5 0.2
lma018
0.1
0.1 0.05 0.02
0.01 single pulse
P D
tp
D = tp/T
T
0.001 1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN025-100D_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 20 November 2008
4 of 11
NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 0.25 mA; VGS = 0 V; Tj = -55 C ID = 0.25 mA; VGS = 0 V; Tj = 25 C ID = 1 mA; VDS = VGS; Tj = 175 C; see Figure 8 ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 8; see Figure 9 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 8 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 100 V; VGS = 0 V; Tj = 25 C VDS = 100 V; VGS = 0 V; Tj = 175 C VGS = 10 V; VDS = 0 V; Tj = 25 C VGS = -10 V; VDS = 0 V; Tj = 25 C VGS = 10 V; ID = 25 A; Tj = 175 C; see Figure 10 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 10; see Figure 11 Dynamic characteristics QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf LD LS total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time internal drain inductance internal source inductance source-drain voltage reverse recovery time recovered charge measured from tab to centre of die; Tj = 25 C measured from source lead to source bond pad; Tj = 25 C IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 15 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 25 V; Tj = 25 C VDS = 50 V; RL = 1.8 ; VGS = 10 V; RG(ext) = 5.6 ; Tj = 25 C VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 13 ID = 45 A; VDS = 80 V; VGS = 10 V; Tj = 25 C; see Figure 12 61 13 25 2600 340 195 18 72 69 58 3.5 7.5 nC nC nC pF pF pF ns ns ns ns nH nH Min 89 100 1 2 Typ 3 0.05 0.02 0.02 22 Max 4 6 10 500 100 100 68 25 Unit V V V V V A A nA nA m m
Static characteristics
Source-drain diode VSD trr Qr 0.87 82 0.26 1.2 V ns C
PSMN025-100D_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 20 November 2008
5 of 11
NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
40 35 30 25 20 15 10 5
Drain Current, ID (A) VGS = 10V 8V 6V
lma019
Transconductance, gfs (S) 50 45 40 35 30 VDS > ID X RDS(ON) Tj = 25 C
lma022
Tj = 25 C
175 C
5V 4.8 V 4.6 V 4.4 V 4V 4.2 V 1.8 2
25 20 15 10 5 0 0 5 10 15 20 25 30 35 Drain current, ID (A) 40 45 50
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6
Fig 6.
Output characteristics: drain current as a function of drain-source voltage; typical values
Threshold Voltage, VGS(TO) (V) maximum
lma024
Fig 7.
Forward transconductance as a function of drain current; typical values
Drain current, ID (A)
lma025
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0
1.0E-01
1.0E-02 typical 1.0E-03 minimum 1.0E-04 maximum 1.0E-05 minimum typical
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
1.0E-06 0 0.5 1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V) 4 4.5 5
Junction Temperature, Tj (C)
Fig 8.
Gate-source threshold voltage as a function of junction temperature
Normalised On-state Resistance
lma023
Fig 9.
Sub-threshold drain current as a function of gate-source voltage
Drain-Source On Resistance, RDS(on) (Ohms) 4.2 V 4.4 V 4.6 V 4V 4.8 V
lma020
2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C)
0.16 0.14 0.12 0.1 0.08 0.06 0.04
Tj = 25 C
5V
8V 0.02 0 0 2 4 6 8 10 12 Drain Current, ID (A) 14 16 18
6V
VGS = 10V 20
Fig 10. Normalized drain source on-state resistance factor as a function of junction temperature
PSMN025-100D_3
Fig 11. Drain-source on-state resistance as a function of drain current; typical values
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 20 November 2008
6 of 11
NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ID = 45 A Tj = 25 C
lma027
10000
Capacitances, Ciss, Coss, Crss (pF)
lma026
Ciss
VDD = 20 V
1000
VDD = 80 V
Coss
100
Crss
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Gate charge, QG (nC)
10 0.1 1 10 Drain-Source Voltage, VDS (V) 100
Fig 12. Gate-source voltage as a function of gate charge; typical values
Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
Source-Drain Diode Current, IF (A) 50 45 40 35 30 25 20 15 10 5 0 175 C Tj = 25 C VGS = 0 V
lma028
Drain current, ID (A) 50 45 40 35 30 25 20 15 10 5 0 0 1 2 3 4 5 175 C VDS > ID X RDS(ON)
lma021
Tj = 25 C
6
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5
Gate-source voltage, VGS (V)
Source-Drain Voltage, VSDS (V)
Fig 14. Transfer characteristics: drain current as a function of gate-source voltage; typical values
Fig 15. Source current as a function of source-drain voltage; typical values
PSMN025-100D_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 20 November 2008
7 of 11
NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
7. Package outline
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428
y E b2 A A1 A E1
mounting base D1 HD
D2
2 L2 1 3
L L1
b1 e e1
b
w
M
A
c
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.93 0.46 b 0.89 0.71 b1 1.1 0.9 b2 5.46 5.00 c 0.56 0.20 D1 6.22 5.98 D2 min 4.0 E 6.73 6.47 E1 min 4.45 e 2.285 e1 4.57 HD 10.4 9.6 L 2.95 2.55 L1 min 0.5 L2 0.9 0.5 w 0.2 y max 0.2
OUTLINE VERSION SOT428
REFERENCES IEC JEDEC TO-252 JEITA SC-63
EUROPEAN PROJECTION
ISSUE DATE 06-02-14 06-03-16
Fig 16. Package outline SOT428 (DPAK)
PSMN025-100D_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 20 November 2008
8 of 11
NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
8. Revision history
Table 7. Revision history Release date 20081120 Data sheet status Product data sheet Change notice Supersedes PSMN025-100D_2 Document ID PSMN025-100D_3 Modifications:
* *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product data sheet Objective data sheet PSMN025-100D_1 -
PSMN025-100D_2 PSMN025-100D_1
19990801 19990201
PSMN025-100D_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 20 November 2008
9 of 11
NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN025-100D_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 20 November 2008
10 of 11
NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . .9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Contact information. . . . . . . . . . . . . . . . . . . . . .10
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: Rev. 03 -- 20 November 2008 Document identifier: PSMN025-100D_3

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