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General Information
DDR SDRAM
DDR SDRAM Product Guide
December 2007
Memory Division
December 2007
General Information
A. DDR SDRAM Component Ordering Information
1 2 3 4 5 6 7 8 9 10 11
DDR SDRAM
K4 HXXXXXXX-XXXX
SAMSUNG Memory DRAM Product Density & Refresh Organization Speed Temperature & Power Package Type Revision Interface (VDD, VDDQ) Bank
1. SAMSUNG Memory : K
2. DRAM : 4
3. Product H : DDR SDRAM
8. Revision M : 1st Gen. A : 2nd Gen. B : 3rd Gen. C : 4th Gen. D : 5th Gen. E : 6th Gen. F : 7th Gen. G : 8th Gen. H : 9th Gen.
J : 11st Gen. N : 14th Gen.
4. Density & Refresh 28 : 128Mb, 4K/64ms 56 : 256Mb, 8K/64ms 51 : 512Mb, 8K/64ms 1G: 1Gb, 8K/64ms 2G: 2Gb, 8K/64ms 9. Package Type T : TSOP II N : sTSOP II G : FBGA L H F 6 : : : : U : TSOP II (Lead-free)*1 V : sTSOP II (Lead-free)*1 Z : FBGA (Lead-free)*1
5. Organization 04 : 06 : 07 : 08 : 16 : x4 x 4 Stack x 8 Stack x8 x16
TSOP II (Lead-free & Halogen-free)*1 FBGA (Lead-free & Halogen-free)*1 FBGA for 64Mb DDR (Lead-free & Halogen-free)*1 sTSOP II (Lead-free & Halogen-free)*1
Note 1: All of Lead-free or Halogen-free product are in compliance with RoHS 10. Temperature & Power C : Commercial Temp.( 0C ~ 70C) & Normal Power L : Commercial Temp.( 0C ~ 70C) & Low Power I : Industrial Temp.( -40C ~ 85C) & Normal Power P : Industrial Temp.( -40C ~ 85C) & Low Power
6. Bank 3 : 4 Banks
7. Interface ( VDD, VDDQ) 8 : SSTL-2 (2.5V, 2.5V)
11. Speed CC B3 A2 B0 : : : : DDR400 DDR333 DDR266 DDR266 (200MHz @ CL=3, tRCD=3, tRP=3) (166MHz @ CL=2.5, tRCD=3, tRP=3)*1 (133MHz @ CL=2 , tRCD=3, tRP=3) (133MHz @ CL=2.5, tRCD=3, tRP=3)
Note 1: "B3" has compatibility with "A2" and "B0"
December 2007
General Information
B. DDR SDRAM Component Product Guide
Density Bank Part Number Package*1 & Power*2 & Speed*3 LCCC/CB3 LLCC/LB3 FCCC/CB3 FLCC/LB3 UCA2/CB0 ULA2/LB0 ZCCC/CB3 ZLCC/LB3 UCCC/CB3 ULCC/LB3 ZCCC/CB3 ZLCC/LB3 UCCC/CB3 ULCC/LB3 ZCCC/CB3 ZLCC/LB3 LCB3/CB0 LLB3/LB0 LCCC/CB3 LLCC/LB3 LCCC/CB3 LLCC/LB3 UCB0 ULB0 ZCCC ZLCC UCCC/CB3 ULCC/LB3 ZCCC/CB3 ZLCC/LB3 UCCC/CB3 ULCC/LB3 ZCCC/CB3 ZLCC/LB3
Note 2 : C L Commercial Temperature, Normal Power Commercial Temperature, Low Power CL = 2 CL = 2.5 CL = 3
DDR SDRAM
Org.
Interface Refresh
Power (V)
Package 66pinTSOPII
Avail. Now
CS
64Mb N-die
4Banks K4H641638N
4M x 16
SSTL_2
4K/64m
2.5 0.2V 60ball FBGA 66pinTSOPII
K4H560438H
64M x 4 60ball FBGA 60ball FBGA 32M x 8 SSTL_2 8K/64m 2.5 0.2V*4 60ball FBGA 66pinTSOPII 16M x 16 60ball FBGA 64M x 4 32M x 8 16M x 16 SSTL_2 8K/64m 2.5 0.2V*4 66pinTSOPII 66pinTSOPII 66pinTSOPII 66pinTSOPII 128M x 4 60ball FBGA 66pinTSOPII 64M x 8 SSTL_2 8K/64m 2.5 0.2V*4 60ball FBGA 66pinTSOPII 32M x 16 60ball FBGA Now
CS
256Mb H-die
4Banks K4H560838H
Now
K4H561638H
K4H560438J 256Mb J-die 4Banks K4H560838J K4H561638J
CS
CS
K4H510438D
512Mb D-die
4Banks K4H510838D
K4H511638D
Note 1 : U : TSOP II (Lead-free) V : sTSOP II (Lead-free) Z : FBGA (Lead-free) L H F 6 : : : : TSOP II (Lead-free & Halogen-free) FBGA (Lead-free & Halogen-free) FBGA for 64Mb DDR (Lead-free & Halogen-free) sTSOP II (Lead-free & Halogen-free)
Note 3 : 133Mhz DDR266(A2) DDR266(B0) 166Mhz DDR333(B3) 200Mhz DDR400(CC)
- Commercial Temp. (0C - "B3" has compatibility with "A2" and "B0"
Note 4 : DDR400 VDD/VDDQ 2.6V 0.1V DDR333/266 2.5V 0.2V
December 2007
General Information
C. Industrial temp DDR SDRAM Component Product Guide
Density Bank Part Number Package*1 & Power*2 & Speed*3 Org. Interface Refresh Power (V)
DDR SDRAM
Package Avail.
256Mb H-die
4Banks K4H561638J
UICC/IB3/IB0 UPCC/PB3/PB0 ZIB3/IB0 ZPB3/PB0 LICC/IB3 LPCC/PB3 UIB3/IB0 UPB3/PB0 ZIB3/IB0 ZPB3/PB0 UIB3/IB0 UPB3/PB0 ZIB3/IB0 ZPB3/PB0
Note 2 : I P
66pinTSOPII 16M x 16 SSTL_2 8K/64m 2.5 0.2V*4 60ball FBGA 16M x 16 SSTL_2 8K/64m 2.5 0.2V*4 66pinTSOPII 66pinTSOPII 64M x 8 60ball FBGA SSTL_2 32M x 16 60ball FBGA 8K/64m 2.5 0.2V*4 66pinTSOPII Now
CS
Now
256Mb J-die
4Banks K4H561638J
K4H510838D 512Mb D-die 4Banks K4H511638D
Note 1 : U : TSOP II (Lead-free) V : sTSOP II (Lead-free) Z : FBGA (Lead-free) L H F 6 : : : : TSOP II (Lead-free & Halogen-free) FBGA (Lead-free & Halogen-free) FBGA for 64Mb DDR (Lead-free & Halogen-free) sTSOP II (Lead-free & Halogen-free)
Note 3 : 133Mhz CL = 2 CL = 2.5 CL = 3 DDR266(A2) DDR266(B0) 166Mhz DDR333(B3) 200Mhz DDR400(CC)
Industrial Temperature, Normal Power Industrial Temperature, Low Power
- Industrial Temp. (-40C - "B3" has compatibility with "A2" and "B0"
Note 4 : DDR400 VDD/VDDQ 2.6V 0.1V DDR333/266 2.5V 0.2V
December 2007
General Information
D. DDR SDRAM Module Ordering Information
1 2 3 4 5 6 7 8 9 10 11 12
DDR SDRAM
MXXXLXXXXXXX-XXX
Memory Module DIMM Configuration Data bits Feature Depth Refresh, # of Banks in Comp. & Interface Speed Power PCB revision & Type Package Component Revision Composition Component
1. Memory Module : M
7. Composition Component 0 3 4 8 9 : : : : : x4 x8 x16 x 4 Stack x 8 Stack
2. DIMM Configuration 3 : DIMM 4 : SODIMM 3. Data Bits 68 : 81 : 83 : 12 : 70 : 63 : x64 x72 x72 x72 x64 x64 184pin Unbuffered DIMM 184pin ECC unbuffered DIMM 184pin Registered DIMM 184pin Low Profile Registered DIMM 200pin Unbuffered SODIMM 172pin Micro DIMM
8. Component Revision A : 2nd Gen. M : 1st Gen. C : 4th Gen. B : 3rd Gen. E : 6th Gen. D : 5th Gen. G : 8th Gen F : 7th Gen. J : 11th Gen. H : 9th Gen. 9. Package U : TSOP II*1 (Lead-Free) T : TSOP II (400mil) V : sTSOP II*1 (Lead-Free) N : sTSOP : FBGA Z : FBGA*1 (Lead-Free) G (Note 1 : All of Lead-free product are in compliance with RoHS) 10. PCB Revision & Type
4. Feature L : DDR SDRAM (2.5V VDD) 5. Depth 16 : 16M 32 : 32M 64 : 64M 28 : 128M 56 : 256M 51 : 512M 17 33 65 29 57 : 16M (for 128Mb/512Mb) : 32M (for 128Mb/512Mb) : 64M (for 128Mb/512Mb) : 128M (for 128Mb/512Mb) : 256M (for 512Mb)
0 : Mother PCB 1 : 1st Rev. 2 : 2nd Rev. 3 : 3rd Rev. S : Reduced layer PCB 11. Temp & Power C : Commercial Temp.( 0C ~ 70C) & Normal Power L : Commercial Temp.( 0C ~ 70C) & Low Power
6. Refresh, # of Banks in comp. & Interface 1: 2: 4K/ 64ms Ref., 4Banks & SSTL-2 8K/ 64ms Ref., 4Banks & SSTL-2 12. Speed CC : B3 : A2 : B0 :
DDR400 DDR333 DDR266 DDR266
(200MHz @ CL=3, tRCD=3, tRP=3) (166MHz @ CL=2.5, tRCD=3, tRP=3) (133MHz @ CL=2 , tRCD=3, tRP=3) (133MHz @ CL=2.5, tRCD=3, tRP=3)
December 2007
General Information
E. DDR SDRAM Module Product Guide
Org. Density Part Number Speed Composition Comp. Version Voltage Internal Banks External Banks
DDR SDRAM
PKG*1 Feature Avail.
184Pin DDR Unbuffered DIMM
M368L3223HUS 32Mx 64 256MB M368L3223JUS M368L6423HUN 64Mx 64 512MB M368L6423JUN M368L6523DUS*2 128Mx 64 1GB M368L2923DUN*2 CCC/CB3 CCC/CB3 CCC/CB3 CCC/CB3 CCC/CB3 32Mx 8 64Mx 8 64Mx 8 64Mx 8 64Mx 8 * 8pcs * 16pcs * 16pcs * 8pcs * 16pcs 256Mb 256Mb 256Mb 512Mb 512Mb J-die H-die J-die D-die D-die 2 2.5 0.2V*3 4 1 66pin TSOP(II) DS,1250mil SS,1250mil DS,1250mil Now Now Now CCC/CB3 32Mx 8 * 8pcs 256Mb H-die 1 SS,1250mil Now
184Pin DDR Low Profile Registered DIMM
M312L6420HUS 64Mx 72 512MB M312L6420JUS M312L6523DZ3*2 M312L2920DUS*2 128Mx 72 1GB M312L2923DZ3*2 CCC/CB3 64Mx 8 * 18pcs 512Mb D-die 2 60ball FBGA DS,1125mil Now CB0 CB0 CCC/CB3 CB0 64Mx 4 64Mx 4 64Mx 8 128Mx 4 * 18pcs * 18pcs * 9pcs * 18pcs 256Mb 256Mb 512Mb 512Mb H-die J-die D-die D-die 2.5 0.2V*3 1 4 1 60ball FBGA 66pin TSOP(II) SS,1125mil DS,1200mill Now Now 66pin TSOP(II) DS,1200mil Now
200Pin DDR SODIMM
M470L3224HU0 32Mx 64 64Mx 64 128Mx 64 256MB M470L3224JU0 512MB 1GB M470L6524DU0*2 M470L2923DV0*2 CB3 CB3 CB3 16Mx 16 * 8pcs 32Mx 16 * 8pcs 64Mx 8 * 16pcs 256Mb 512Mb 512Mb J-die D-die D-die 2.5 0.2V*3 4 2 54pin sTSOP(II) CB3 16Mx 16 * 8pcs 256Mb H-die 66pin TSOP(II) DS,1250mi Now Now Now
Note 1 : (All of DDR DIMMs can support Lead-free) U : TSOP II (Lead-Free) V : sTSOP II (Lead-Free) Z : FBGA (Lead-Free) Note 2 : All of DDR components support both Leaded and Lead-free. And 256Mb H-die, Jdie and 512Mb D-die Lead-free is default PKG Type.
Note 3 : DDR400 VDD/VDDQ 2.6V 0.1V DDR333/266 2.5V 0.2V
December 2007
General Information
F. Package Dimension
DDR SDRAM
Unit : mm
(0.80) #66 #34 (0.50) (10) (10) 0.125 - 0.035 1.20 MAX
+0.075
10.16 0.10
(1.50)
(0.80)
#1 (1.50) 0.665 0.05 0.210 0.05 22.22 0.10
(R
#33
0 .1
5)
(10)
1.00 0.10
(0.50)
11.76 0.20
(10.76)
(0.71)
0.65TYP [0.65 0.08]
0.30 0.08
[
(R
0.075 MAX
0.
(R
(R
0.
25 )
25 )
NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS'Y OUT QUALITY
66Pin TSOP(II) Package Dimension
[
(10)
0.05 MIN
0. 15
(4)
0.10 MAX
)
(0 8)
December 2007
0.45 ~ 0.75 0.25TYP
General Information
60Ball FBGA (For 64Mb)
DDR SDRAM
Units : Millimeters 8.00 0.10 0.80 x 8 = 6.40 0.80 9 (Datum A) A (Datum B) B C D 12.00 0.10 12.00 0.10 B 3 2 1 14.00 0.10 E F 0.50 G H J 1.00 K L M 1.00 x 11 = 11.00 1.00 x 11 = 11.00 8 7 6 5 1.60 4 3 2 1 A #A1 MARK
#A1
8.0 0 0.10
0.10 Max
B
0.32 0.05 1.10 0.10
60 - 0.45 SOLDER BALL (Post Reflow 0.50 0.05) 0.20 M AB
TOP VIEW
BOTTOM VIEW
60Ball FBGA (For 256Mb)
Units : Millimeters 8.00 0.10 0.80 x 8 = 6.40 0.80 9 (Datum A) A (Datum B) B C D 14.00 0.10 E F 0.50 AB G H J 1.00 ENCAPSULANT AREA K L M 8 7 6 5 1.60 4
0.10 Max
A #A1 MARK
#A1
8.0 0 0.10
0.35 0.05 1.10 0.10
60 - 0.45 SOLDER BALL (Post Reflow 0.50 0.05) 0.20 M
TOP VIEW
BOTTOM VIEW
December 2007
General Information
60Ball FBGA (For 512Mb)
10.00 0.10 1.00MAX
DDR SDRAM
A 0.80 x8 = 6.40 #A1 MARK(option) (Datum A) 3.20 1.60 0.80 987654321 A B D 5.50 C B
10.00 0.10
#A1
(Datum B)
1.00 x 11 = 11.00
12.00 0.10
12.00 0.10
E F G 0.45 0.05 H J K L M 1.00 0.50
1.20 MAX 4-CORNER MARK(option) 60-0.45 0.05
(0.90) (1.80)
(0.90) WINDOW MOLD AREA
Top view
0.20 M A B
Bottom view
December 2007
12.00 0.10
General Information
DDR SDRAM
For further information,
semiconductor@samsung.com
December 2007

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