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| Evaluation board available. NX2119/2119A SYNCHRONOUS PWM CONTROLLER WITH CURRENT LIMIT PROTECTION PRELIMINARY DATA SHEET Pb Free Product DESCRIPTION FEATURES n n n n n n Bus voltage operation from 2V to 25V The NX2119 controller IC is a synchronous Buck conFixed 300kHz and 600kHz troller IC designed for step down DC to DC converter Internal Digital Soft Start Function applications. It is optimized to convert bus voltages from Prebias Startup 2V to 25V to outputs as low as 0.8V voltage. The Less than 50 nS adaptive deadband NX2119 operates at fixed 300kHz, while NX2119A operCurrent limit triggers latch out by sensing Rdson of ates at fixed 600kHz, making it ideal for applications Synchronous MOSFET requiring ceramic output capacitors. The NX2119 emn No negative spike at Vout during startup and ploys fixed loss-less current limiting by sensing the Rdson shutdown of synchronous MOSFET followed by latch out feature. n Pb-free and RoHS compliant Feedback under voltage triggers Hiccup. Other features of the device are: 5V gate drive, Adaptive deadband control, Internal digital soft start, Vcc n Graphic Card on board converters undervoltage lock out and shutdown capability via the n Memory Vddq Supply comp pin. n On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V n ADSL Modem APPLICATIONS TYPICAL APPLICATION Vin +5V C4 100uF L2 1uH C5 1uF D1 MBR0530T1 1 Cin 280uF 18mohm R5 10 5 C3 1uF Vcc 7 BST Hdrv 2 C6 0.1uF M1 L1 1.5uH HI=SD M3 NX2119 COMP R4 37.4k C7 27pF SW Ldrv 8 C2 2.2nF 4 M2 R1 4k R2 10k Co 2 x (1500uF,13mohm) Vout +1.8V 9A 6 FB Gnd 3 C1 4.7nF R3 8k Figure1 - Typical application of 2119 ORDERING INFORMATION Device NX2119CSTR NX2119ACSTR NX2119ACUTR Rev.3.2 04/10/08 Temperature 0 to 70oC 0 to 70o C 0 to 70o C Package SOIC - 8L SOIC - 8L MSOP - 8L Frequency 300kHz 600kHz 600kHz Pb-Free Yes Yes Yes 1 NX2119/2119A ABSOLUTE MAXIMUM RATINGS VCC to GND & BST to SW voltage .................... -0.3V to 6.5V BST to GND Voltage ........................................ -0.3V to 35V SW to GND ...................................................... -2V to 35V All other pins .................................................... -0.3V to VCC+0.3V or 6.5V Storage Temperature Range ............................... -65oC to 150oC Operating Junction Temperature Range ............... -40oC to 125oC ESD Susceptibility ........................................... 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION 8-LEAD PLASTIC SOIC(S) JA 130o C/W 8-LEAD PLASTIC MSOP JA 216o C/W BST 1 HDrv 2 Gnd 3 LDrv 4 8 SW 7 Comp 6 Fb 5 Vcc BST HDrv Gnd LDrv 1 2 3 4 8 7 6 5 SW Comp Fb Vcc ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc = 5V, and TA= 0 to 70oC. Typical values refer to Ta = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range VCC Supply Current (Static) VCC Supply Current (Dynamic) Supply Voltage(VBST) VBST Supply Current (Static) VBST Supply Current (Dynamic) SYM VREF Test Condition Min TYP 0.8 0.2 4.5 5 3 TBD 5.5 MAX Units V % V mA mA VCC ICC (Static) Outputs not switching ICC CLOAD=3300pF FS=300kHz (Dynamic) IBST (Static) Outputs not switching IBST CLOAD=3300pF (Dynamic) FS=300kHz 0.2 TBD mA mA Rev.3.2 04/10/08 2 NX2119/2119A PARAMETER Under Voltage Lockout VCC-Threshold VCC-Hysteresis Oscillator (Rt) Frequency Ramp-Amplitude Voltage Max Duty Cycle Min Duty Cycle Min LDRV on time Controllable Min on time Error Amplifiers Transconductance Input Bias Current Comp SD Threshold Soft Start Soft Start time High Side Driver(CL=3300pF) Sourcing Output Impedance , Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time SYM TEST CONDITION MIN 3.8 TYP 4 0.2 300 600 1.5 93 0 250 100 2000 10 0.3 FS=300kHz I=200mA I=200mA 6.8 0.9 0.65 50 50 30 MAX 4.2 UNITS V V kHz kHz V % % nS nS umho nA V mS ohm ohm ns ns ns VCC_UVLO VCC Rising VCC_Hyst VCC Falling FS VRAMP 2119 2119A Ib Tss Rsource(Hdrv) Rsink(Hdrv) THdrv(Rise) VBST-VSW=4.5V THdrv(Fall) VBST-VSW=4.5V Tdead(L to Ldrv going Low to Hdrv going H) High, 10%-10% Low Side Driver (CL=3300pF) Output Impedance, Sourcing CurrentImpedance, Sinking Output Current Rise Time Fall Time Deadband Time OCP OCP voltage Rsource(Ldrv) I=200mA Rsink(Ldrv) I=200mA TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% 0.9 0.5 50 50 30 ohm ohm ns ns ns 320 mV Rev.3.2 04/10/08 3 NX2119/2119A PIN DESCRIPTIONS PIN # 5 PIN SYMBOL VCC PIN DESCRIPTION Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. 1 BST This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is placed as close as possible to and connected to these pins and respected SW pins. Ground pin. This pin is the error amplifier inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage. When FB pin voltage is lower than 0.6V, hiccup circuit starts to recycle the soft start circuit after 2048 switching cycles. This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is also used as a shut down pin. When this pin is pulled below 0.3V, both drivers are turned off and internal soft start is reset. This pin is connected to source of high side FET and provides return path for the high side driver. It is also used to hold the low side driver low until this pin is brought low by the action of high side turning off. LDRV can only go high if SW is below 1V threshold . High side gate driver output. Low side gate driver output. 3 GND 6 FB 7 COMP 8 SW 2 4 HDRV LDRV Rev.3.2 04/10/08 4 NX2119/2119A BLOCK DIAGRAM VCC FB 0.6V Bias Generator 1.25V 0.8V UVLO POR START Hiccup Logic OC BST HDRV COMP 0.3V START 0.8V OSC Digital start Up ramp S R FB 0.6V CLAMP COMP START GND Q PWM OC Control Logic VCC SW LDRV 1.3V CLAMP latch out OCP comparator 320mV Figure 2 - Simplified block diagram of the NX2119 Rev.3.2 04/10/08 5 NX2119/2119A APPLICATION INFORMATION Symbol Used In Application Information: VIN VOUT IOUT FS - Input voltage - Output voltage - Output current IRIPPLE = = VIN -VOUT VOUT 1 x x LOUT VIN FS ...(2) 5V-1.8V 1.8v 1 x x = 2.56A 1.5uH 5v 300kHz DVRIPPLE - Output voltage ripple - Working frequency DIRIPPLE - Inductor current ripple Output Capacitor Selection Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(3). Design Example The following is typical application for NX2119, the schematic is figure 1. VIN = 5V VOUT=1.8V FS=300kHz IOUT=9A DVRIPPLE <=20mV DVDROOP<=100mV @ 9A step VRIPPLE = ESR x IRIPPLE + IRIPPLE 8 x FS x COUT ...(3) Where ESR is the output capacitors' equivalent series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected such as Aluminum Electrolytic,POSCAP and OSCON types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. For this example, POSCAP are chosen as output capacitors, the ESR and inductor current typically determines the output voltage ripple. Output Inductor Selection The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations: ESR desire = VRIPPLE 20mV = = 7.8m IRIPPLE 2.56A ...(4) If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP ...(1) 2R5TPE220MC with 12m are chosen. V -V V 1 L OUT = IN OUT x OUT x IRIPPLE VIN FS IRIPPLE =k x IOUTPUT where k is between 0.2 to 0.4. Select k=0.3, then L OUT = 5V-1.8V 1.8V 1 x x 0.3 x 9A 5V 300kHz L OUT =1.4uH N= E S R E x IR I P P L E VR IPPLE ...(5) Number of Capacitor is calculated as N= 12mx 2.56A 20mV Choose inductor from COILCRAFT DO5010P152HC with L=1.5uH is a good choice. Current Ripple is recalculated as N =1.5 The number of capacitor has to be round up to a integer. Choose N =2. If ceramic capacitors are chosen as output ca Rev.3.2 04/10/08 6 NX2119/2119A pacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors . For example, one 100uF, X5R ceramic capacitor of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L L crit is true. In that case, the transient spec is dependent on the ESR of capacitor. In most cases, the output capacitors are multiple capacitors in parallel. The number of capacitors can be calculated by the following N= ESR E x Istep Vtran + VOUT x 2 2 x L x C E x Vtran with 2m ESR is used. The amount of output ripple is VRIPPLE 2.56A = 2mx 2.56A + 8 x 300kHz x 100uF = 15mV ...(9) where Although this meets DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient is specified as: 0 if L L crit = L x Istep - ESR E x CE V OUT sient is 100mV for 9A load step. if L L crit ...(10) For example, assume voltage droop during tranIf the POSCAP 2R5TPE220MC(220uF, 12m ) is used, the critical inductance is given as VDROOP L crit = ESR E x C E x VOUT = Istep 12m x 220F x 1.9V = 0.56H 9A The selected inductor is 1.5uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitors is where is the a function of capacitor, etc. = = L x Istep VOUT - ESR E x C E 0 if L L crit = L x Istep - ESR x COUT V OUT where L crit = if L L crit ...(7) 1.5H x 9A - 12m x 220F = 4.86us 1.8V ESR E x Istep Vtran + VOUT x 2 2 x L x CE x Vtran ESR x COUT x VOUT ESR E x C E x VOUT = Istep Istep N= ...(8) where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR 12m x 9A + 100mV 1.8V x (4.86us) 2 2 x1.5H x 220F x 100mV = 1.7 = The number of capacitors has to satisfied both ripple and transient requirement. Overall, we can choose N=2. Rev.3.2 04/10/08 7 NX2119/2119A It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. FZ1 = FZ2 = FP1 = FP2 = 1 2 x x R 4 x C2 1 2 x x (R 2 + R3 ) x C3 1 2 x x R3 x C3 1 2 x x R4 x C1 x C2 C1 + C2 ...(11) ...(12) ...(13) ...(14) where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. Their locations are shown in figure 4. The transfer function of type III compensator for transconductance amplifier is given by: Ve 1 - gm x Z f = VOUT 1 + gm x Zin + Z in / R1 Compensator Design Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response,compensator is employed to provide highest possible bandwidth and enough phase margin.Ideally,the Bode plot of the closed loop system has crossover frequency between1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with -20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen. For the voltage amplifier, the transfer function of compensator is Ve -Z f = VOUT Zin To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R 4>>2/gm. And it would be desirable if R 1||R2||R3>>1/gm can be met at the same time. Zin R3 Vout Zf C1 C2 Fb gm Ve R4 A. Type III compensator design For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier. R2 C3 R1 Vref Figure 3 - Type III compensator using transconductance amplifier Rev.3.2 04/10/08 8 NX2119/2119A Case 1: FLC power stage FLC 40dB/decade C3 = = 1 11 ) x( 2 x x R2 Fz2 Fp1 loop gain FESR 20dB/decade compensator 1 1 1 x( ) 2 x x 10k 6.2kHz 60.3kHz =2.3nF R4 = = VOSC 2 x x FO x L x x Cout Vin C3 1.5V 2 x x 30kHz x 1.5uH x x 440uF 5V 2.2nF =16.9k Choose C3=2.2nF, R 4=16.9k. 5. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). FZ1 FZ2 FO FP1 FP2 C2 = Figure 4 - Bode plot of Type III compensator 1 2 x x FZ1 x R 4 = Design example for type III compensator are in order. The crossover frequency has to be selected as FLC Choose C2=2.2nF. 6. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. FLC = = 1 2 x x L OUT x COUT 1 C1 = = 1 2 x x R 4 x FP2 2 x x 1.5uH x 440uF = 6.2kHz 1 2 x x 16.9k x 150kHz = 63pF Choose C1=68pF. 7. Calculate R 3 by equation (13). FESR 1 = 2 x x ESR x C OUT 1 2 x x 6m x 440uF = 60.3kHz = R3 = = 1 2 x x FP1 x C3 2. Set R2 equal to 10k. R1 = R 2 x VREF 10k x 0.8V = = 8k VOUT -VREF 1.8V-0.8V 1 2 x x 60.3kHz x 2.2nF = 1.2k Choose R3=1.2k. Rev.3.2 04/10/08 9 NX2119/2119A Case 2: FLC R 2 x VREF 10k x 0.8V = = 8k VOUT -VREF 1.8V-0.8V Gain(db) power stage FLC 40dB/decade Choose R1=8.06k. 3. Set zero FZ2 = FLC and Fp1 =FESR . 4. Calculate C3 . C3 = 1 11 x( ) 2 x x R2 Fz2 Fp1 FESR loop gain 1 1 1 x( ) 2 x x 10k 2.3kHz 8.2kHz =4.76nF = 20dB/decade compensator Choose C3=4.7nF. 5. Calculate R3 . R3 = = 1 2 x x FP1 x C3 1 2 x x 8.2kHz x 4.7nF = 4.1k FZ1 FZ2 FP1 FO FP2 Choose R3 =4k. 6. Calculate R4 with FO=30kHz. R4 = VOSC 2 x x FO x L R2 x R3 x x Vin ESR R 2 + R3 Figure 5 - Bode plot of Type III compensator (FLC C2 = = 1 2 x x FZ1 x R 4 1 2 x x 0.75 x 2.3kHz x 37.4k = 2.4nF FLC = = 1 2 x x LOUT x COUT 1 Choose C2=2.2nF. 8. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. 2 x x 1.5uH x 3000uF = 2.3kHz C1 = = 1 2 x x R 4 x FP2 FESR = = 1 2 x x ESR x COUT 1 2 x x 6.5m x 3000uF = 8.2kHz Rev.3.2 04/10/08 1 2 x x 37.4k x 150kHz = 28pF Choose C1=27pF. 10 NX2119/2119A B. Type II compensator design If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. Type II compensator can be realized by simple RC circuit without feedback as shown in figure 6. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain. Vout R2 Fb gm R1 Vref Ve R3 C2 C1 Gain=gm x R1 x R3 R1+R2 ... (15) Figure 7 - Type II compensator with 1 Fz = 2 x x R3 x C1 Fp 1 2 x x R3 x C2 ... (16) ... (17) transconductance amplifier For this type of compensator, FO has to satisfy FLC 1500uF with 13m electrolytic capacitors. 1.Calculate the location of LC double pole F LC and ESR zero FESR. FLC = = 1 2 x x L OUT x COUT 1 2 x x 1.5uH x 3000uF = 2.3kHz compensator Gain FESR = = 1 2 x x ESR x C OUT FZ FLC FESR FO FP R1 = 1 2 x x 6.5m x 3000uF = 8.2kHz 2.Set R2 equal to 1k. Figure 6 - Bode plot of Type II compensator R 2 x VREF 1k x 0.8V = = 800 VOUT -VREF 1.8V-0.8V Choose R1=800. 3. Set crossover frequency at 1/10~ 1/5 of the swithing frequency, here FO=30kHz. 4.Calculate R3 value by the following equation. Rev.3.2 04/10/08 11 NX2119/2119A Vout 4.Calculate R3 value by the following equation. R2 Fb R1 Vref Voltage divider Figure 8 - Voltage divider V 2 x x FO x L 1 VOUT x x R3 = OSC x Vin RESR gm VREF 1.5V 2 x x 30kHz x 1.5uH 1 x x 5V 6.5m 2.0mA/V 1.8V x 0.8V =14.6k = Choose R 3 =14.7k. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. 1 C1= 2 x x R 3 x Fz 1 = 2 x x 14.7k x 0.75 x 2.3kHz =6.3nF Input Capacitor Selection Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as: Choose C1=6.8nF. 6. Calculate C 2 by setting compensator pole Fp at half the swithing frequency. 1 C2= x R 3 x Fs 1 p x 1 4 .7k x 3 0 0 k H z =72pF = IRMS = IOUT x D x 1- D D= VOUT VIN ...(19) VIN = 5V, VOUT=1.8V, IOUT=9A, using equation (19), the result of input RMS current is 4.3A. For higher efficiency, low ESR capacitors are recommended. One Sanyo OS-CON 16SP270M 16V 270uF 18m with 4.4A RMS rating are chosen as input bulk capacitors. Choose C1=68pF. Output Voltage Calculation Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation and picture show the relationship between Power MOSFETs Selection The power stage requires two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In this design example, two IRFR3706 are used. They have the following parameters: V DS=30V, ID =75A,RDSON =9m,QGATE =23nC. There are two factors causing the MOSFET power loss:conduction loss, switching loss. Conduction loss is simply defined as: 12 VOUT , VREF and voltage divider. . R 2 x VR E F V O U T -V R E F ...(18) R 1= where R2 is part of the compensator, and the value of R1 value can be set by voltage divider. See compensator design for R1 and R2 selection. Rev.3.2 04/10/08 NX2119/2119A PHCON =IOUT 2 x D x RDS(ON) x K PLCON =IOUT 2 x (1 - D) x RDS(ON) x K PTOTAL =PHCON + PLCON ...(20) ISET = 320mV K x RDSON If MOSFET RDSON=9m, the worst case thermal consideration K=1.5, then ISET = 320mV 320mV = = 23.7A K x RDSON 1.5 x 9m where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 at 125oC according to IRFR3706 datasheet. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated. Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources,and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. 1 PSW = x VIN x IOUT x TSW x FS ...(21) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. Switching loss PSW is frequency dependent. Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as: Pgate = (QHGATE x VHGS + QLGATE x VLGS ) x FS ...(22) where QHGATE is the high side MOSFETs gate charge,QLGATE is the low side MOSFETs gate charge,VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. This power dissipation should not exceed maximum power dissipation of the driver device. Over Current Limit Protection Over current Limit for step down converter is achieved by sensing current through the low side MOSFET. For NX2119, the current limit is decided by the RDSON of the low side mosfet. When synchronous FET is on, and the voltage on SW pin is below 320mV, the over current occurs. The over current limit can be calculated by the following equation. Rev.3.2 04/10/08 13 NX2119/2119A SOIC8 PACKAGE OUTLINE DIMENSIONS Rev.3.2 04/10/08 14 NX2119/2119A Rev.3.2 04/10/08 15 NX2119/2119A MSOP8 PACKAGE OUTLINE DIMENSIONS Rev.3.2 04/10/08 16 |
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