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NX2114/2114A
300kHz & 600kHz SYNCHRONOUS PWM CONTROLLER
PRELIMINARY DATA SHEET Pb Free Product
DESCRIPTION
The NX2114 controller IC is a synchronous Buck controller IC designed for step down DC to DC converter applications. Synchronous control operation replaces the traditional catch diode with an Nch MOSFET resulting in improved converter efficiency. Although the NX2114 controller is optimized to convert single 5V bus voltages to supplies as low as 0.8V output voltage, however using a few external components it can also be used for other input supplies such as 12V input (See NX2113 data sheet for more optimized solution). The NX2114 operates at 300kHz while 2114A is set at 600kHz operation which together with less than 50 nS of dead band provides an efficient and cost effective solution. Other features of the device are: Internal digital soft start; Vcc undervoltage lock out; Output undervoltage protection with digital filter and shutdown capability via the enable pin.
Vin +5V
C4 47uF,70mohm R5 10 C8 47uF,70mohm C6 1uF 5 1 D1 MBR0530T1 C5 1uF M1 L1 1.5uH Cin 220uF,12mohm
FEATURES
n n n n n n n n Synchronous Controller in 8 Pin Package Bus voltage operation from 2V to 25V Single 5V Supply Operation Short protection with feedback UVLO Internal 300kHz for 2114 and 600kHz for 2114A Internal Digital Soft Start Function Shut Down via pulling comp pin low Pb-free and RoHS compliant
APPLICATIONS
n n n n n Graphic Card on board converters Memory Vddq Supply in mother board applications On board DC to DC such as 5V to 3.3V, 2.5V or 1.8V Hard Disk Drive Set Top Box
TYPICAL APPLICATION
L2 1uH
Vcc
7 OFF R6 10k ON 2N3904 R7 10k C1 47pF C2 1.5nF R4 22.1k 6
BST
C7 0.1uF 2
NX2114
Comp
Hdrv SW Ldrv
8
Fb Gnd
3
4
M2
Co 2 x (220uF,15mohm)
Vout +1.6V,6A
R2 10.2k
R1 10.2k R3 1.5k C3 2.2nF
Figure1 - Typical application of 2114
ORDERING INFORMATION
Device NX2114CSTR NX2114ACSTR Temperature 0 to 70oC 0 to 70o C Package SOIC-8L SOIC-8L Frequency 300kHz 600kHz Pb-Free Yes Yes
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ABSOLUTE MAXIMUM RATINGS(NOTE1)
Vcc to GND & BST to SW voltage ................... 6.5V BST to GND Voltage ...................................... 35V Storage Temperature Range ............................. -65oC to 150oC Operating Junction Temperature Range ............. -40oC to 125oC NOTE1: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
8-PIN PLASTIC SOIC (S)
JA 130o C/W
BST 1 HDrv 2 Gnd 3 LDrv 4
8 SW 7 Comp 6 Fb 5 Vcc
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range VCC Supply Current (Static) VCC Supply Current (Dynamic) Supply Voltage(VBST) VBST Supply Current (Static) VBST Supply Current (Dynamic) Under Voltage Lockout VCC-Threshold VCC-Hysteresis SYM VREF Test Condition 4.5VVCC ICC (Static) Outputs not switching ICC CLOAD=3300pF FS=300kHz (Dynamic) IBST (Static) Outputs not switching IBST CLOAD=3300pF (Dynamic) VCC_UVLO VCC Rising VCC_Hyst VCC Falling FS=300kHz
0.15 5
mA mA
4.2 0.22
V V
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PARAMETER SS Soft Start time Oscillator (Rt) Frequency Ramp-Amplitude Voltage Max Duty Cycle Min Duty Cycle Error Amplifiers Transconductance Input Bias Current Comp SD Threshold FB Under Voltage Protection FB Under voltage threshold High Side Driver(C L=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Output Sourcing Current Output Sinking Current Rise Time Fall Time Deadband Time Low Side Driver (C L=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Output Sourcing Current Output Sinking Current Rise Time Fall Time Deadband Time SYM Tss FS VRAMP Test Condition Fsw=300Khz, 2114 Fsw=600Khz, 2114A 2114 2114A Min TYP 3.4 1.7 300 600 1.7 94 0 1900 10 0.3 0.4 Rsource(Hdrv) Rsink(Hdrv) I=200mA I=200mA VBST-VHDRV=5V VHDRV-VSW =5V 10% to 90% 90% to 10% Ldrv going Low to Hdrv going High, 10%-10% I=200mA I=200mA 1.1 0.8 2 2 50 50 30 MAX Units mS kHz kHz V % % umho nA V V ohm ohm A A ns ns ns
Ib
THdrv(Rise) THdrv(Fall) Tdead(L to H) Rsource(Ldrv) Rsink(Ldrv)
1.1 0.5 2 4 50 50 30
ohm ohm A A ns ns ns
VPVCC-VLDRV=5V VLDRV-PGND=5V TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv L) going High, 10% to 10%
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PIN DESCRIPTIONS
PIN # 1 PIN SYMBOL BST PIN DESCRIPTION This pin supplies voltage to the high side driver. A high frequency ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin. High side MOSFET gate driver. Ground pin. Low side MOSFET gate driver. Voltage supply for the internal circuit as well as the low side MOSFET gate driver. A 1uF high frequency ceramic capacitor must be connected from this pin to GND pin. This pin is the error amplifier inverting input. This pin is also connected to the output UVLO comparator. When this pin falls below 0.4V, both HDRV and LDRV outputs are latched off. This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is also used as a shut down pin. When this pin is pulled below 0.3V, both drivers are turned off and internal soft start is reset. This pin is connected to the source of the high side MOSFET and provides return path for the high side driver.
2 3 4
HDRV GND LDRV
5
Vcc
6
FB
7
COMP
8
SW
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BLOCK DIAGRAM
5 UVLO DRIVER 1 2 8 4 3 BST Hdrv SW Ldrv GND
VCC
OSC 7
Q Q S
COMP FB
6
R
0.3V LATCH
DIGITAL SS
TIMER
0.4V
VREF
Figure 1 - Simplified block diagram of the NX2114
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Demoboard design and waveforms
Vin +5V
C4 47uF,70mohm R5 10 C8 47uF,70mohm C6 1uF 5 1 D1 1N5819 C5 1uF M1 L1 1.5uH Cin 220uF,12mohm L2 1uH
sdfd
Vcc
7 C2 1.5nF C1 47pF R4 22.1k 6
BST
C7 0.1uF 2
NX2114
Comp
Hdrv SW Ldrv
8
Fb Gnd
3
4
M2
Co 2 x (220uF,15mohm)
Vout +1.6V,6A
R2 10.2k
R1 10.2k R3 C3 1.5kohm 2.2nF
Figure 2 - demoboard design on NX2114 Bill of Material
Name R1 R2 R3 R4 R5 C1 C2 C3 C4,C8 C5,C6 C7 CIN CO D1 M1,M2 L1 L2 Component de scription 10.2k 10.2k 1.5k 10 1% chip resistor 1% c hip resistor 1% c hip resistor Vendor Vendor P/N Num b e r 1 1 1
22.1k 1% c hip resistor chip resistor 47pF ceramic 1.5nF ceramic 2.2nF ceramic 47uF,16V,70mohm,SMD 1uF ceramic 0.1uF ceramic 220uF,6.3V,12mohm,SMD 220uF,4V,15mohm,SMD Diode MOSFET 1.5uH,6.8A 1uH,6.4A
sdfdsf
1 1 1 1 1
Sanyo
16TQC47M
1 1 1 1 2 1 1 1 1
Sanyo Sanyo Fairchild Coilcraft Coilcraft
6TPD220M 4TPE220MF D1N5819 FDS6294 DO3316P-152 DO3316P-102
Note: To make sure short circuit protection of device functions correctly, C8 and R5 are necessary for filtering noise in single power supply design.
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95 f
Vin=5V,Vout=1.6V
90
Efficiency (%)
85
80
75
70 0 1 2 3 C rrent (A u ) 4 5 6
Figure 3: Output efficiency
Figure 4: Voltage ripple @1.6 V output voltage, 7A output current
Figure 5: Start up time
Figure 6: Output voltage transient response for load curent 0A-6A
Figure 7: Output voltage droop during transient(0A-6A)
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Figure 8: Startup operation waveform
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NX2114/2114A
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN VOUT IOUT FS - Input voltage - Output voltage - Output current - Working frequency
IRIPPLE = =
VIN -VOUT VOUT 1 x x LOUT VIN FS 5V-1.6V 1.6v 1 x x = 2.4A 1.5uH 5v 300kHz
...(2)
Output Capacitor Selection
Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(3).
DVRIPPLE - Output voltage ripple DIRIPPLE - Inductor current ripple
Design Example
The following is typical application for NX2114, the schematic is figure 2. VIN = 5V VOUT=1.6V IOUT=6A DVRIPPLE <=20mV DVDROOP<=60mV @ 6A step
VRIPPLE = ESR x IRIPPLE +
IRIPPLE 8 x FS x COUT ...(3)
Where ESR is the output capacitors' equivalent series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected such as Aluminum Electrolytic,POSCAP and OSCON types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. For this example, POSCAP are chosen as output capacitors, the ESR and inductor current typically determines the output voltage ripple.
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
ESR desire =
VRIPPLE 20mV = = 8.6m IRIPPLE 2.3A
...(4)
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP 4TPE220MF with 15m are chosen.
LOUT
V -V V 1 = IN OUT x OUT x IRIPPLE VIN FS
IRIPPLE = k x IOUTPUT
where k is between 0.2 to 0.4. Select k=0.4, then
5V-1.6V 1.6V 1 L OUT = x x 0.4 x 6A 5V 300kHz L OUT =1.51uH
...(1)
N=
E S R E x IR I P P L E VR IPPLE
...(5)
Number of Capacitor is calculated as
N= 15m x 2.3A 20mV
Choose inductor from COILCRAFT DO3316P-152 with L=1.5uH is a good choice. Current Ripple is recalculated as
N =1.8 The number of capacitor has to be round up to a integer. Choose N =2.
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If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors. For example, one 100uF, X5R ceramic capacitor voltage droop or overshoot is only dependent on the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L L crit is true. In that case, the transient spec is dependent on the ESR of capacitor. In most cases, the output capacitors are multiple capacitors in parallel. The number of capacitors can be calculated by the following
N= ESR E x Istep Vtran + VOUT x 2 2 x L x C E x Vtran
with 2m ESR is used. The amount of output ripple is
VRIPPLE 2.3A = 2m x 2.3A + 8 x 300kHz x 100uF = 4.6mV + 9.6mV = 13.2mV
...(9)
where
Although this meets DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient is specified as: VDROOP 0 if L L crit = L x Istep - ESR E x CE V OUT
sient is 100mV for 6A load step.
if
L L crit
...(10)
For example, assume voltage droop during tranIf the POSCAP 2R5TPE220MC (220uF, 12m ) is used, the critical inductance is given as
Lcrit =
ESR E x C E x VOUT = Istep
15m x 220F x 1.6V = 0.88H 6A
The selected inductor is 1.5uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitors is
Vovershoot = ESR x Istep +
VOUT x 2 2 x L x COUT
...(6)
where is the a function of capacitor, etc.
= =
L x I step VOUT
- ESR E x C E
0 if L L crit = L x Istep - ESR x COUT V OUT
where
L crit =
if
L L crit
...(7)
1.5H x 6A - 15m x 220F = 2.3us 1.6V
ESR E x Istep Vtran + VOUT x 2 2 x L x CE x Vtran
ESR x COUT x VOUT ESR E x C E x VOUT = Istep Istep
N=
...(8)
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected output inductor is smaller than the critical inductance, the
15m x 6A = + 60mV 1.6V x 2.3us 2 2 x1.5H x 220F x 60mV = 1.7
The number of capacitors has to satisfied both ripple and transient requirement. Overall, we can choose N=2.
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It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters.
FZ1 = FZ2 = FP1 = FP2 =
1 2 x x R 4 x C2 1 2 x x (R 2 + R3 ) x C3 1 2 x x R3 x C3 1 2 x x R4 x C1 x C2 C1 + C2
...(11) ...(12) ...(13) ...(14)
where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. Their locations are shown in figure 10. The transfer function of type III compensator for transconductance amplifier is given by:
Ve 1 - gm x Z f = VOUT 1 + gm x Zin + Z in / R1
Compensator Design
Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen.
For the voltage amplifier, the transfer function of compensator is
Ve -Z f = VOUT Zin
To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. R1||R2||R3>>1/gm is desirable.
Zin R3
Vout
Zf C1 C2 Fb gm Ve R4
A. Type III compensator design
For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier.
R2 C3 R1
Vref
Figure 9 - Type III compensator using transconductance amplifier
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FO=30kHz.
Gain(db)
power stage
C3 =
FLC
40dB/decade
=
1 11 x( ) 2 x x R2 Fz2 Fp1
1 1 1 x( ) 2 x x 10k 6.2kHz 48kHz =2.2nF
R4 = VOSC 2 x x FO x L x x Cout Vin C3
loop gain
FESR
20dB/decade compensator
=
1.7V 2 x x 30kHz x 1.5uH x x 440uF 5V 2.2nF =19.2k
Choose C3=2.2nF, R 4=22.1k. 5. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11).
FZ1 FZ2
FO FP1
FP2
C2 = =
1 2 x x FZ1 x R 4
Figure 10 - Bode plot of Type III compensator Design example for type III compensator are in order. The crossover frequency has to be selected as FLC1 2 x x 0.75 x 6.2kHz x 22.1k = 1.55nF
Choose C2=1.5nF. 6. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency.
C1 = =
1 2 x x R 4 x FP2
FLC = =
1 2 x x L OUT x COUT 1
1 2 x x 22.1k x 150kHz = 48pF
Choose C1=47pF. 7. Calculate R 3 by equation (13).
2 x x 1.5uH x 440uF = 6.2kHz
FESR = =
1 2 x x ESR x COUT
R3 = =
1 2 x x FP1 x C3
1 2 x x 7.5m x 440uF = 48kHz
2. Set R2 equal to10.2k, then R1= 10.2k. 3. Set zero FZ2 = FLC and Fp1 =FESR . 4. Calculate R 4 and C3 with the crossover frequency at 1/10~ 1/5 of the switching frequency. Set
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1 2 x x 48kHz x 2.2nF = 1.5k
Choose R3=1.5k.
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NX2114/2114A
B. Type II compensator design
If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. Type II compensator can be realized by simple RC circuit without feedback as shown in figure 12. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain.
Vout R2 Fb gm R1 Vref Ve R3 C2 C1
Gain=gm x Fz =
R1 x R3 R1+R2
... (15) ... (16) ... (17)
Figure 12 - Type II compensator with transconductance amplifier For this type of compensator, FO has to satisfy FLC1 2 x x R3 x C1 1 2 x x R3 x C2
Fp
power stage Gain(db) 40dB/decade loop gain 20dB/decade
and ESR zero FESR.
FLC = =
1 2 x x L OUT x COUT 1
2 x x 1.5uH x 1360uF = 3.5kHz
FESR =
1 2 x x ESR x COUT
compensator Gain
1 2 x x 20.5m x 1360uF = 5.7kHz =
2.Set R2 equal to10.2k. Using equation 18, the final selection of R1 is 3.24k. 3. Set crossover frequency at 1/10~ 1/5 of the swithing frequency, here FO=30kHz. 4.Calculate R3 value by the following equation.
FZ FLC FESR
FO FP
Figure 11- Bode plot of Type II compensator
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1.6V, the result of R1 is 10k.
R3 = =
VOSC 2 x x FO x L 1 R1+R2 x x x Vin RESR gm R1
Vout R2 Fb R1 Vref Voltage divider
Figure 13 - Voltage divider In general, the minimum output load impedance including the resistor divider should be less than 5k to prevent overcharge the output voltage by leakage current (e.g. Error Amplifier feedback pin bias current). A minimum load for 5k less (<1/16w for most of application) is recommended to put at the output. For example, in this application, Vout=1.6V The power loss is 1/16W less
1.7V 2 x x 30kHz x 1.5uH 1 x x 12 20.5 1.9mA/V 10.2k+3.24k x 3.24k =4.23k
Choose R 3 =4.53k. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole.
C1 = =
1 2 x x R3 x Fz
1 2 x x 4.51k x 0.75 x 3.5kHz =13.3nF
Choose C1=12nF. 6. Calculate C2 by setting compensator pole Fp at half the swithing frequency.
1 C2 = p x R3 x Fs 1 = p x 3.74k x 300kHz =235pF
Choose C2=220pF.
RLOAD = 1.6V x 1.6V /(1/16W) = 40
Select minimum load, 1k should be good enough.
Input Capacitor Selection
Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise. The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as:
Output Voltage Calculation
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation and picture show the relationship between
IRMS = IOUT x D x 1- D D= VOUT VIN
...(19)
VOUT , VREF and voltage divider. .
R 2 x VR E F V O U T -V R E F
...(18)
R 1=
VIN = 5V, VOUT=1.6V, IOUT=6A, using equation (19), the result of input RMS current is 2.80A. For higher efficiency, low ESR capacitors are recommended. One Sanyo TPD series POSCAP 6TPD220M 6V 220uF with 12m is chosen as input bulk capacitor.
where R2 is part of the compensator, and the value of R1 value can be set by voltage divider. Choose R2=10k, to set the output voltage at
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Power MOSFETs Selection
The NX2114 requires two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In this design example, two Fairchild FDS6294 are used. They have the following parameters: VDS=30V, ID =13A, RDSON =14.4m,QGATE =10nC. There are three factors causing the MOSFET power loss: conduction loss, switching loss and gate driver loss. Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits. It is proportional to frequency and is defined as: dependent.
Soft Start, Enable and shut Down
The NX2114 has a digital start up. It is based on digital counter with 1024 cycles. For NX2114 with 300kHz operation, the start up time is about 3.5ms. For NX2114A with 600kHz operation, the start up time is about half of NX2114, 1.75mS. NX2114/NX2114A can be enabled or disabled by pulling COMP pin below 0.3V. The function is illustrated in the following diagram. During the normal operation, the lowest COMP voltage is clamped to be about 700mV , the COMP voltage is higher than 0.3V. If external switch with 10 Rdson or less to pull down COMP pin, when COMP is below 0.3V, the digital soft start will be reset to zero. All the drivers will be off. The synchronous buck is shut off. When external switch is released, and COMP is above 0.3V, a soft start will initiates and system starts from the beginning.
Pgate = (QHGATE x VHGS + QLGATE x VLGS ) x FS
...(20)
where QHGATE is the high side MOSFETs gate charge, QLGATE is the low side MOSFETs gate charge, VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. According to equation (20), PGATE =0.03W. This power dissipation should not exceed maximum power dissipation of the driver device. Conduction loss is simply defined as:
PH C O N = I O U T 2 x D x R D S ( O N ) x K PL C O N = I O U T 2 x (1 - D ) x R D S (O N ) x K P T O T A L = PH C O N + PL C O N
...(21)
OFF ON
2114 Shut down FB Compensation Network comp 0.6 1.3V Clamp
0.3V
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K equals to 1.43 at 125 C according to FDS6294 datasheet. Using equation (21), the result of PTOTAL is 0.75W. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated.
o
Figure 14 - Enable and Shut down NX2114 by pulling down COMP pin.
Feedback Under Voltage Shut Down
NX2114 relies on the Feedback Under Voltage Lock Out (FB UVLO ) to provide short circuit protection. Basically, NX2114 has a comparator compare the feedback voltage with the FB UVLO threshold 0.4V.
PSW
1 = x VIN x IOUT x TSW x FS 2
...(22)
where IOUT is output current, TSW is swithing time,and FS is switching frequency. Swithing loss PSW is frequency
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During the normal operation, if the output is short, the feedback voltage will be lower than 0.4V and comparator will change the state. After certain internal delay, both high side and low side driver will be turned off. The output will be latched. The normal operation should be achieved by removing the short and recycle the VCC. age Lock Out comparator is disabled. After half of start up time, the Feedback UVLO comparator is enabled. The FB UVLO threshold is set to be half of voltage at the positive input of error amplifier. With this set up, if the output is short before soft start, the Feedback UVLO comparator can catch it and turn off the driver. The short circuit operation waveform during normal operation and during the soft start are shown as follows. During the normal operation, Feedback UVLO will take the role. But during the soft start, due to the input voltage dropping, UVLO Vcc will take the role, hiccup happens. The Feedback UVLO can provide short circuit protection under certain conditions. However, since feedback does not have accurate information of current, this protection only provides certain level of over current protection. MOSFET should design such that it can survive with high pulse current for a short period of time. Figure 15 - Operation waveforms during short condition.
Layout Considerations
The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small sig-
CH3-bus voltage 5V/DIV
CH2-Vcc voltage 5V/DIV
nal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input
CH1-Fb voltage 0.5V/DIV
CH4-output current 10A/DIV
Figure 16 - Operation waveform with start up at short. During the start up, the output voltage is discharged to zero by the synchronous FET. FB voltage starts increase from zero when digital start block operates. Before half of the start up time, the Feedback Under VoltRev. 4.0 06/20/06
capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic 15
NX2114/2114A
cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function.
Rev. 4.0 06/20/06
16
NX2114/2114A
TYPICAL APPLICATION
Single Supply 5V Input
Vin +5V
C4 33uF C3
33uF C6 1uF 5
L2 1uH R3 10 1 C5 1uF Cin 2 x (470uF,60mohm)
D1 MBR0530T1
Vcc
7 C2 8.2nF C1 150pF R4 7k 6
BST
C7 0.1uF 2 M1 L1 1.5uH
NX2114
Comp
Hdrv SW Ldrv
8
Fb Gnd
3
4
M2
Co 4 x (330uF,80mohm)
Vout +2.5V,10A
R2 4.7 k 1%
R1 10 k 1%
Figure 17 - Application of NX2114 for 5V input and 2.5V output with electrolytic capacitors
Vin +5V
C4 22uF C6 1uF 5 R3 10 D1 MBR0530T1 1 L2 1uH C5 1uF
Cin 3 x 22uF X7R
C3 22uF
Vcc
7 C2 330pF C1 4.7pF R4 120 k 6
BST
NX2114A
Comp
Hdrv SW Ldrv
2
C7 0.1uF
M1 L1 3.3uH
8 Co 10 x 22uF X7R
Vout +1.2V,4A
Fb
4
M2
Gnd
3
R2 20 k 1%
R1 10 k 1% R3 787 C3 820pF
Figure 18 - Application of NX2114 A for 5V input and 1.2V output with ceramic output capacitors
Rev. 4.0 06/20/06
17
NX2114/2114A
TYPICAL APPLICATIONS(CONT')
Dual power supply (+5V BIAS,+12V BUS)
Vin +12V
C3 33uF L2 1uH
C5 1uF
Cin 2 x (47uF,60mohm)
D1 MBR0530T1
Vin +5V
R8 1k R5 10 k R7 5 k 2N3904 2N3904 R6 680 C1 270pF C6 1uF 7 C2 15nF R4 3.74 k 6 5 1
Vcc
BST
C4 0.1uF 2 M1 L1 1.5uH
NX2114
Comp
Hdrv SW Ldrv
8
Fb Gnd
3
4
M2
Co 2 x (680uF,41mohm)
Vout +3.3V,10A
R2 3.24 k 1%
R1 10.2 k 1%
Figure 19 -Application of NX2114 for 5V bias and 12V input bus
Single power supply (+11V to +24V BUS)
Vin +11~25V
C4 33uF R5 3k 2N3904 L2 1uH
C5 1uF
Cin 2 x (47uF,60mohm)
R6 10k TL431 R7 10 k 7 C2 2.7nF C1 220pF R4 15k 6 C6 2.2uF 5 1
D1 MBR0530T1
Vcc
BST
C7 0.1uF 2 M1 L1 5uH
NX2114
Comp
Hdrv SW Ldrv
8
Fb Gnd
3
4
M2
Co 2 x (680uF,41mohm)
Vout +1.6V,5A
R2 10 k 1%
R1 10 k 1% R3 787 C3 1nF
Figure 20 -Application of NX2114 for high input bus application
Rev. 4.0 06/20/06
18
NX2114/2114A
SOIC8 PACKAGE OUTLINE DIMENSIONS
Rev. 4.0 06/20/06
19
NX2114/2114A
Rev. 4.0 06/20/06
20

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