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| CY2XP41 Crystal to LVPECL Clock Generator Features Functional Description The CY2XP41 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate high performance clock frequencies for DVD-R applications. It uses Cypress's low noise VCO technology to achieve less than 1 ps typical RMS phase jitter, that meets application jitter requirements. The CY2XP41 has a crystal oscillator interface input and one LVPECL output pair. One LVPECL output pair External crystal frequency: 25.0 MHz Selectable Output Frequency: 62.5 MHz or 75 MHz Low RMS phase jitter at 75 MHz, using 25 MHz crystal (1.5 MHz-10 MHz): 0.27 ps (typical) Low RMS phase jitter at 62.5 MHz, using 25 MHz crystal (1.5 MHz-10 MHz): 0.38 ps (typical) Pb-free 8-Pin TSSOP package Supply voltage: 3.3V Commercial Temperature Range Logic Block Diagram XIN External Crystal XOUT FS Crystal Oscillator PLL CLK CLK# Cypress Semiconductor Corporation Document #: 001-48923 Rev. *A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised June 12, 2008 [+] Feedback CY2XP41 Pinouts Figure 1. Pin Diagram - 8 Pin TSSOP VDD VSS XOUT XIN 1 2 3 4 8 7 6 5 VDD CLK CLK# FS Table 1. Pin Definitions - 8 Pin TSSOP Pin 1, 8 2 3, 4 5 6,7 Name VDD VSS XOUT, XIN FS CLK#, CLK Power Power XTAL output and input LVCMOS/LVTTL input LVPECL output Type Ground Parallel resonant crystal interface Frequency Select Input, See "Frequency Table" on page 3 Differential Clock Output Description 3.3V power supply. All supply current flows through pin 1 Document #: 001-48923 Rev. *A Page 2 of 8 [+] Feedback CY2XP41 Frequency Table Input Input Xtal Frequency (MHz) 25 25 FS 0 1 Output Frequency (MHz) 62.5 75.0 Absolute Maximum Conditions Parameter VDD VIN[1.] TS TJ ESDHBM UL-94 JA[2] Description Supply Voltage Input Voltage, DC Temperature, Storage Temperature, Junction ESD Protection (Human Body Model) JEDEC STD 22-A114-B Flammability Rating Thermal Resistance, Junction to Ambient At 1/8 in. 0 m/s airflow 1 m/s airflow 2.5 m/s airflow 2000 V-0 100 91 87 C/W Relative to VSS Non Functional Condition Min -0.5 -0.5 -65 Max 4.4 VDD + 0.5 150 135 Unit V V C C V Operating Conditions Parameter VDD TA TPU 3.3V Supply Voltage Ambient Temperature, Commercial Power up time for all VDD to reach minimum specified voltage (ensure power ramps are monotonic) Description Min 3.135 0 0.05 Max 3.465 70 500 Unit V C ms Electrical Characteristics for Input Parameter VIL VIH IIL IIH CIN Description Input Low Voltage Input High Voltage Input Low Current Input High Current Input Capacitance FS = VSS FS = VDD Test Conditions Min - 0.7*VDD -50 - Typ - - - - 15 Max 0.3*VDD - - 115 Unit V V A A pF DC Electrical Characteristics for Power Supplies Parameter IDD[3] Description Power Supply Current with output terminated Min - Typ - Max 180 Unit mA Note 1. The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metallization. No vias are included in the model. 3. IDD includes ~16 mA of current that is dissipated externally in the output termination resistors. Document #: 001-48923 Rev. *A Page 3 of 8 [+] Feedback CY2XP41 DC Electrical Characteristics for LVPECL Output Parameter VCM VPP Description Common-Mode Voltage (CLK + CLK#) / 2, defined in Figure 5 on page 5, using Figure 2 on page 5 circuit. Differential Peak Output Voltage, defined in Figure 5 on page 5, using Figure 2 on page 5 circuit. Min 175 350 Typ - 780 Max 2000 850 Unit mV mV Crystal Characteristics Parameter Mode of Oscillation F ESR CL CS DL Frequency Equivalent Series Resistance Crystal Load Capacitance Shunt Capacitance Crystal Drive Level - - - - - Description Min Typ Fundamental 25 - 10 - - - 50 - 7 300 MHz pF pF W Max Unit AC Characteristics Parameter FOUT TR/TF TJitter() TDC Description Output Frequency Output Rise/Fall time RMS Phase Jitter (Random) Duty Cycle Defined in Figure 5 on page 5 75 MHz, (1.5 MHz - 10 MHz filter), 3.3V 62.5 MHz, (1.5 MHz - 10 MHz filter), 3.3V Defined in Figure 4 on page 5 Test Conditions Min 62.5 - - - 45 Typ - 350 0.27 0.38 - Max 75.0 - - - 55 Unit MHz ps ps ps % Document #: 001-48923 Rev. *A Page 4 of 8 [+] Feedback CY2XP41 Measurement Definitions Figure 2. Output Load AC Test Circuit 3.3V 110 CLK CLK# Z=50 Z=50 62 3.3V 110 Measurement Point 62 2pF 2pF Figure 3. RMS Phase Jitter Noise Power Phase Noise Phase Noise Mask 40dB/Decade 20dB/Decade 1.5MHz 10MHz Offset Frequency RMS Jitter = vArea Under the Masked Phase Noise Plot Figure 4. Output Duty Cycle CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Figure 5. Output Rise and Fall Time and Peak-Peak Voltage Swing CLK 80% VPP CLK# 20% TR VSS TF VCM Document #: 001-48923 Rev. *A Page 5 of 8 [+] Feedback CY2XP41 Crystal Input Interface The CY2XP41 is characterized with 10 pF parallel resonant crystals. The capacitor values shown in Figure 7. are determined using a 25 MHz 10 pF parallel resonant crystal and are chosen to minimize the ppm error. Cypress recommends the following C1 and C2 values: C1 = C2 = 6.8pF. Figure 7. Crystal Input Interface Application Information Power Supply Filtering Techniques As in any high speed analog circuitry, noise at the power supply pins degrades performance. To achieve optimum jitter performance, good power supply isolation practices are advised. Figure 6. shows a typical filtering scheme. Since all of the current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. A 0.01 or 0.1 F ceramic chip capacitor is also located close to this pin to provide a short and low impedance AC path to ground. A ~5 to 10 F tantalum capacitor is also located in the vicinity of this device. Figure 6. Power Supply Filtering V DD (Pin 8) 3.3V 0.1F 0.01 F 10F XIN External Crystal C1 XOUT C2 VDD (Pin 1) Termination for 3.3V LVPECL Output CLK and CLK# are pull up drivers that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources are used for functionality. Matched impedance techniques are used to maximize operating frequency and minimize signal distortion. Figure 2 on page 5 shows a termination scheme that is recommended as a guideline. Other suitable clock layouts exist and it is recommended that the board designers simulate to guarantee compatibility across all printed circuit and process variations. Cypress recommends the following RU and RD values: RU=110 and RD=62. This is a 40 load, which is used to achieve the specified common mode and peak-to-peak voltage swing. For optimal signal integrity, 40 traces are recommended. Document #: 001-48923 Rev. *A Page 6 of 8 [+] Feedback CY2XP41 Ordering Information Part Number CY2XP41ZXC CY2XP41ZXCT 8-Pin TSSOP 8-Pin TSSOP-Tape and Reel Package Type Product Flow Commercial, 0C to 70C Commercial, 0C to 70C Package Drawing and Dimensions Figure 8. 8-Pin Thin Shrunk Small Outline Package (4.40mm Body) Z8 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 8 0.19[0.007] 0.30[0.012] 0.65[0.025] BSC. 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0-8 0.076[0.003] 0.85[0.033] 0.95[0.037] 2.90[0.114] 3.10[0.122] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85093-*A Document #: 001-48923 Rev. *A Page 7 of 8 [+] Feedback CY2XP41 Document History Page Document Title: CY2XP41 Crystal to LVPECL Clock Generator Document Number: 001-48923 REV. ** *A ECN NO. 2669117 2718433 Submission Date 03/05/09 06/12/09 Orig. of Change XHT/CXQ/ KVM WWZ/HMT New data sheet No change. Submit to ECN for product launch. Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-48923 Rev. *A Revised June 12, 2008 Page 8 of 8 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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