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PRELIMINARY DEVICE SPECIFICATION
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS BiCMOS PECL CLOCK SERIAL INTERFACE CIRCUITS HIGH PERFORMANCE GENERATOR GENERAL DESCRIPTION
S2042/S2043 S2042/S2043
FEATURES
* Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards * S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference * S2043 receiver PLL configured for clock and data recovery * 1062, 531 and 266 Mb/s operation * 10- or 20-bit parallel TTL compatible interface * 1 watt typical power dissipation for chipset * +3.3/+5V power supply * Low-jitter serial PECL compatible interface * Lock detect * Local loopback * 10mm x 10mm 52 PQFP package * Fibre Channel framing performed by receiver * Continuous downstream clocking from receiver * TTL compatible outputs possible with +5V I/O power supply
The S2042 and S2043 transmitter and receiver pair are designed to perform high-speed serial data transmission over fiber optic or coaxial cable interfaces conforming to the requirements of the ANSI X3T11 Fibre Channel specification. The chipset is selectable to 1062, 531 or 266 Mbit/s data rates with associated 10- or 20-bit data word. The chipset performs parallel-to-serial and serial-toparallel conversion and framing for block-encoded data. The S2042 on-chip PLL synthesizes the highspeed clock from a low-speed reference. The S2043 on-chip PLL synchronizes directly to incoming digital signals to receive the data stream. The transmitter and receiver each support differential PECL-compatible I/O for fiber optic component interfaces, to minimize crosstalk and maximize data integrity. Local loopback allows for system diagnostics. The TTL I/O section can operate from either a +3.3V or a +5V power supply. With a 3.3V power supply the chipset dissipates only 1W typically. Figure 1 shows a typical network configuration incorporating the chipset. The chipset is compatible with AMCC's S2036 Open Fiber Control (OFC) device.
APPLICATIONS
High-speed data communications * Supercomputer/Mainframe * Workstation * Switched networks * Proprietary extended backplanes * Mass storage devices/RAID drives
Figure 1. System Block Diagram
S2036 Open Fiber Control (OFC)
Fibre Channel Controller
S2042 TX
Optical TX
Optical RX
S2043 RX
S2043 RX
Optical RX
Optical TX
S2042 TX
Fibre Channel Controller
S2036 Open Fiber Control (OFC)
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S2042/S2043 OVERVIEW
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Loopback Local loopback is supported by the chipset, and provides a capability for performing offline testing of the interface to ensure the integrity of the serial channel before enabling the transmission medium. It also allows for system diagnostics.
The S2042 transmitter and S2043 receiver provide serialization and deserialization functions for blockencoded data to implement a Fibre Channel interface. Operation of the S2042/S2043 chips is straightforward, as depicted in Figure 2. The sequence of operations is as follows: Transmitter 1. 10/20-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver 1. Clock and data recovery from serial input 2. Serial-to-parallel conversion 3. Frame detection 4. 10/20-bit parallel output The 10/20-bit parallel data handled by the S2042 and S2043 devices should be from a DC-balanced encoding scheme, such as the 8B/10B transmission code, in which information to be transmitted is encoded 8 bits at a time into 10-bit transmission characters. Internal clocking and control functions are transparent to the user. Details of data timing can be seen in Figure 5. A lock detect feature is provided on the receiver, which indicates that the PLL is locked (synchronized) to the reference clock or the data stream.
Figure 2. Fibre Channel Interface Diagram
Parallel Data In TCLK S2042 Transmitter Parallel Data Out Serial Data S2043 Receiver RCLK Sync RefClk Loopback
Loopback RefClk
Lock Detect
S2042 TRANSMITTER FUNCTIONAL DESCRIPTION
The S2042 transmitter accepts parallel input data and serializes it for transmission over fiber optic or coaxial cable media. The chip is fully compatible with the ANSI X3T11 Fibre Channel standard, and supports the Fibre Channel standard's data rates of 1062, 531 and 266 Mbit/sec. The parallel input data word can be either 10 bits or 20 bits wide, depending upon DWS pin selection. A block diagram showing the basic chip operation is shown in Figure 3.
Figure 3. S2042 Functional Block Diagram
OE0 OE1
10 20 10 D Q 10
D(0..19)
2:1 TX TY SHIFT REGISTER
DIVIDE-BY-2 TEST DWS CONTROL LOGIC
TLX TLY
DIVIDE-BY-2 REFCLK REFSEL RATESEL PLL CLOCK MULTIPLIER F0 = F1 X 10/20
TCLK TCLKN
2
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HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Parallel/Serial Conversion The parallel-to-serial converter takes in 10-bit or 20bit wide data from the input latch and converts it to a serial data stream. Parallel data is latched into the transmitter on the positive going edge of REFCLK. The data is then clocked synchronous to the clock synthesis unit serial clock into the serial output shift register. The shift register is clocked by the internally generated bit clock which is 10 times the REFCLK input frequency. The state of the serial outputs is controlled by the output enable pins, OE0 and OE1. D10 is transmitted first in 10-bit mode. D0 is transmitted first in 20-bit mode. Table 2 shows the mapping of the parallel data to the 8B/10B codes. 10-Bit/20-Bit Mode The S2042 operates with either 10-bit or 20-bit parallel data inputs. Word width is selectable via the DWS pin. In 10-bit mode, D10-D19 are used and D0-D9 are ignored. Reference Clock Input
S2042/S2043
The reference clock input (REFCLK) must be supplied with a single-ended AC coupled crystal clock source with 100 PPM tolerance to assure that the transmitted data meets the Fibre Channel frequency limits. The internal serial clock is frequency locked to the reference clock. The word rate clock (TCLK, TCLKN) output frequency is determined by the selected operating speed and word width. Refer to Table 1 for TCLK/TCLKN clock frequencies.
Table 1. Transmitter Operating Modes
Reference TCLK/TCLKN Clock Word Data Rate Width Frequency Frequency (MHz) (MHz) RATESEL DWS REFSEL (Mbits/sec) (Bits) 0 0 1 1 Open 1 0 1 0 1 1 0 1 0 1 1062.5 1062.5 531.25 531.25 265.625 10 20 10 20 10 106.25 53.125 53.125 26.5625 26.5625 53.125 53.125 53.125 26.5625 26.5625
Table 2. Data Mapping to 8b/10b Alphabetic Representation
First Data Byte
TX[00:19] or RX[00:19] 8b/10b alphabetic representation
Second Data Byte 7 g 8 h 9 j 10 a 11 12 13 b c d 14 15 e i 16 f 17 g 18 19 h j
0 a
1 b
2 c
3 d
4 e
5 i
6 f
First bit transmitted in 20-bit mode
First bit transmitted in 10-bit mode
Figure 4. S2043 Functional Block Diagram
LOCK_REF RATESEL REFCLK REFSEL
D
LOCKDETN SHIFT REGISTER
RX RY RLX RLY LPEN SYNCEN DWS
2:1
PLL CLOCK RECOVERY
BITCLK D Q 20
D(0..19)
CONTROL LOGIC
SYNC DETECT LOGIC
SYNC RCLK RCLKN
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S2042/S2043
Figure 5. Functional Waveform
S 2 0 4 2
REFCLK (Input) PARALLEL DATA BUS (Input)
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
K28.5, Byte 1 of Data
Byte 2, 3 of Data
Byte 4, 5 of Data
Byte 6, 7 of Data
Byte 8, 9 of Data
Byte 10, Byte 12, Byte 14,15 11 of Data 13 of Data of Data
K28.5 Byte 16 of Data
SERIAL DATA
K28.5 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 K28.5 D16
S 2 0 4 3
RCLK (Output) SYNC (Output) PARALLEL DATA BUS (Output)
K28.5, Byte 1 of Data
Byte 2, 3 of Data
Byte 4, 5 of Data
Byte 6, 7 of Data
Byte 8, 9 of Data
Byte 10, Byte 12, Byte 14,15 11 of Data 13 of Data of Data
Table 3. Data Mapping to 8b/10b Alphabetic Representation
First Data Byte
TX[00:19] or RX[00:19] 8b/10b alphabetic representation
Second Data Byte 7 g 8 h 9 j 10 a 11 12 13 b c d 14 15 e i 16 f 17 g 18 19 h j
0 a
1 b
2 c
3 d
4 e
5 i
6 f
First bit received in 20-bit mode
First bit received in 10-bit mode
S2043 RECEIVER FUNCTIONAL DESCRIPTION
The S2043 receiver is designed to implement the ANSI X3T11 Fibre Channel specification receiver functions. A block diagram showing the basic chip function is provided in Figure 4. Whenever a signal is present, the S2043 attempts to achieve synchronization on both bit and transmission-word boundaries of the received encoded bit stream. Received data from the incoming bit stream is provided on the device's parallel data outputs. The S2043 accepts serial encoded data from a fiber optic or coaxial cable interface. The serial input stream is the result of the serialization of 8B/10B encoded data by an FC compatible transmitter. Clock recovery is performed on-chip, with the output data presented to the Fibre Channel transmission layer as 10- or 20-bit parallel data. The chip is programmable to operate at the Fibre Channel specified operating frequencies of 1062, 531 and 266 Mbit/s. Serial/Parallel Conversion Serial data is received on the RX, RY pins. The PLL clock recovery circuit will lock to the data stream if the clock to be recovered is within 100 PPM of the internally generated bit rate clock. The recovered clock is
used to retime the input data stream. The data is then clocked into the serial to parallel output registers on the low going edge of RCLK. In 1062 Mbit/ sec, 10-bit mode, data is clocked out on the falling edge of RCLK and RCLKN.The parallel data out can be either 10 or 20 bits wide determined by the state of the DWS pin. The word clock (RCLK) is synchronized to the incoming data stream word boundary by the detection of the fiber channel K28.5 synchronization pattern (0011111010, positive running disparity). 10-Bit/20-Bit Mode The S2043 will operate with either 10-bit or 20-bit parallel data outputs. This option is selectable via the DWS pin. See Table 4. In 10-bit mode, D10-D19 are used and D0-D9 are driven to the logic high state. Reference Clock Input The reference clock input must be supplied with a singleended AC coupled crystal clock source at 100 PPM tolerance. See Table 4 for reference clock frequencies. Framing The S2043 provides SYNC character recognition and data word alignment of the TTL level compatible output data bus. In systems where the SYNC detect function is undesired, a LOW on the SYNCEN input disables the SYNC function and the data will be "un-framed".
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HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 6. Loopback Interface Diagram
Data In OE0, OE1 S2042 Fibre Channel Transmitter S2043 Fibre Channel Receiver Data Out CLK
S2042/S2043
Table 4. Receiver Operating Modes
Reference Clock RCLK/RCLKN Word Data Rate Width Frequency Frequency (MHz) (MHz) RATESEL DWS REFSEL (Mbits/sec) (Bits) 0 0 1 0 1 0 1 1 0 1 0 1 1062.5 1062.5 531.25 531.25 265.625 10 20 10 20 10 106.25 53.125 53.125 26.5625 26.5625 53.125 53.125 53.125 26.5625 26.5625
Local Loopback
Local Loopback
1 1 Open
Data Out CLK
S2043 Fibre Channel Receiver
S2042 Fibre Channel Transmitter
Data In OE0, OE1
Start-Up Procedure The clock recovery PLL requires an initilization procedure to correctly achieve lock on the serial data inputs. At power-up or loss of lock, the PLL must first acquire frequency lock to the local reference clock. This can be accomplished in three ways: 1) The -LOCK_REF pin can be connected to a 10 ms reset signal to initialize the PLL. 2) By guaranteeing that no data is seen at the serial data inputs for a minimum of 10 ms upon powerup. 3) The S2043 can be put into the loopback mode and the loopback outputs of the S2042 must be quiescent for a minimum of 10 ms after power-up. Other Operating Modes Loopback Local loopback requires a S2042 and a S2043 as shown in the Figure 6. When enabled, serial data from the S2042 transmitter is sent to the S2043 receiver, where the clock is extracted and the data is deserialized. The parallel data is then sent to the subsystem for verification. This loopback mode provides the capability to perform offline testing of the interface to guarantee the integrity of the serial channel before enabling the transmission medium. It also allows system diagnostics. Operating Frequency Range The S2042 and S2043 are optimized for operation at the Fibre Channel rates of 266, 531 and 1062 Mbit/s. Operation at other than Fibre channel rates is possible if the rate falls within 10% of the nominal rate. REFCLK must be selected to be within 100 ppm of the desired byte or word clock rate. Test Modes The TEST pin on the S2042 and the SYNCEN pin on the S2043 provide a PLL bypass mode that can be used for operating the digital area of the chip. In this mode, clock signals are input through the reference clock pins. This can be used for testing the device during the manufacturing process or during an offline self-test. Sync detection is always enabled in test mode.
When framing is disabled by low SYNCEN, the S2043 simply achieves bit synchronization within 250 bit times and begins to deliver parallel output data words whenever it has received full transmission words. No attempt is made to synchronize on any particular incoming character. The SYNCEN input should be static during operation (i.e. connected to VCC or GND). The S2043 will not maintain the existing byte synchronization when SYNCEN transitions from the active to inactive state. The SYNC output signal will go high whenever a K28.5 character (positive disparity) is present on the parallel data outputs. The SYNC output signal will be low at all other times. This is true whether the S2043 is operating in 10-bit mode or in 20-bit mode. In 20bit mode, the K28.5 byte will always be placed in the MSB (D0-D9). In 10-bit mode, the K28.5 will be clocked with the RCLKN output. Lock Detect The S2043 lock detect function indicates the state of the phase-locked loop (PLL) clock recovery unit. The PLL will indicate lock within 250 bit times after the start of receiving serial data inputs. If the serial data inputs have an instantaneous phase jump (from a serial switch, for example) the PLL will not indicate an out-of-lock state, but will recover the correct phase alignment within 250 bit times. If a run length of 64 bits is exceeded, or if the transition density is less than 12%, the loop will be declared out of lock and will attempt to re-acquire bit synchronization. When lock is lost, the PLL will shift from the serial input data to the reference clock, so that correct frequency downstream clocking will be maintained. In any transfer of PLL control from the serial data to the reference clock, the RCLK/RCLKN output remains phase continuous and glitch free, assuring the integrity of downstream clocking.
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S2042/S2043
S2042 Pin Assignment and Descriptions
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Pin Name
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TEST
Level
TTL
I/O
I
Pin #
50 49 48 47 44 43 42 41 38 37 36 35 31 30 29 28 25 24 23 22 20
Description
Accepts parallel input data. Data is clocked in on the rising edge of REFCLK. In 20-bit mode, D0 is transmitted first. In 10-bit mode, D10-19 are used, D0-D9 are ignored, and D10 is transmitted first.
Static MultiLevel TTL TTL
I
Multilevel input used for factory testing. When not connected, REFCLK replaces the internal bit clock to facilitate factory testing. In normal use, this input is wired to ground. The level on this pin selects the parallel data bus width. When LOW, a 20-bit parallel bus width is selected, and D(0-19) are active. When HIGH, a 10-bit parallel data bus is selected, D(1019) are active and D(0-9) are not used. (See Table 1.) A rising edge will reset the part (used for test). (Externally capacitively coupled.) A crystal-controlled reference clock for the PLL clock multiplier. The frequency of REFCLK is set by the REFSEL pin. (See Table 1.) Differential TTL word rate clock true and complement. See Table 1 for frequency. Differential PECL outputs that transmit the serial data and drive 75W or 50W termination to Vcc-2V. Enabled by OE0. TX is the positive output, and TY is the negative output. Differential PECL outputs that are functionally equivalent to TX and TY. They are intended to be used for loopback testing. Enabled by OE1.
DWS
I
19
REFCLK
PECL
I
16
TCLK TCLKN TY TX TLX TLY
Diff. TTL Diff. PECL Diff. PECL
O
12 11 9 8 5 4
O
O
6
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HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042 Pin Assignment and Descriptions (Continued)
S2042/S2043
Pin Name
OE0 OE1
Level
Static TTL TTL
I/O
I I
Pin #
2 1 18
Description
Active low output-enable control for TX/TY outputs. TX/TY will go to the logic low state when disabled. Active low output-enable control for TLX/TLY outputs. TLX/TLY will go to the logic low state when disabled. Multilevel input used to select the reference clock frequency. (See Table 1.)
REFSEL
Static MultiTTL
I
RATESEL TTL ECLVCC TTLGND TTLVCC ECLIOVCC ECLIOVEE AVCC AVE E ECLVEE +3.3V GND +3.3V/ +5V +3.3V GND +3.3V GND GND
I
15
Multilevel input used to select the operating speed of the transmitter. (See Table 1.)
- - - - - - - -
21, 39, 45 14 17 3, 10 6, 7 27, 32 2 6, 3 3 13, 34 , 40, 46, 51, 52
Core +3.3V TTL Ground TTL Power Supply (+5V if TTL) PECL I/O Power Supply PECL I/O Power Supply Analog Power Supply Analog Ground Core Ground
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S2042/S2043
S2043 Pin Assignment and Descriptions
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Pin Name
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LOCKDETN
Level
TTL
I/O
O
Pin #
45 43 42 40 38 37 35 34 32 31 29 28 25 24 22 21 18 17 15 14 52
Description
Parallel data outputs. The width of the parallel data bus is selected by the state of the DWS pin. Parallel data on this bus is clocked out on the falling edge of RCLK in 20-bit mode and on both the falling edges of RCLK and RCLKN in 1062.5 Mbit/sec, 10-bit mode. In 20-bit mode, D0 is the first bit received. In 10-bit mode, D10-D19 are used and D0-D9 are driven to the high state. In 10-bit mode, D10 is the first bit received.
TTL
O
When LOW, LOCKDETN indicates that the PLL is locked to the incoming data stream. When HIGH, it provides a system flag indicating that the PLL is locked to the local reference clock. When HIGH, LPEN selects the loopback differential serial input pins. When LOW, LPEN selects RX and RY (normal operation). The level on this pin selects the parallel data bus width. When LOW, a 20-bit parallel bus width is selected, and D(0-19) are active. When HIGH, a 10-bit parallel data bus is selected, D(1019) are active and D(0-9) will go HIGH. (See Table 4.) A rising edge will reset the internal counters (used for test). Parallel data is clocked out on the falling edge of RCLK/RCLKN (see Timing Diagrams in Figures 15-18). After a sync word is detected, the period of the current RCLK and RCLKN is stretched to align with the word boundary. (See Table 4 for frequency.) (Externally capacitively coupled.) A free-running crystalcontrolled reference clock for the PLL clock multiplier. The frequency of REFCLK is set by the REFSEL pin. (See Table 4.) Upon detection of a valid sync symbol, this output goes high for one RCLK period. When sync is active, the sync symbol shall be present on the parallel data bus bits D0-D9 in 20-bit mode and D10-D19 in 10-bit mode. (Externally capacitively coupled.) The serial loopback data inputs. RLX is the positive input, and RLY is the negative input. (Externally capacitively coupled.) The received serial data inputs. RX is the positive input, and RY is the negative input.
LPEN DWS
TTL Static TTL
I I
8 4
RCLK RCLKN
Diff. TTL
O
49 48
REFCLK
Analog
I
2
SYNC
TTL
O
51
RLX RLY RX RY
Diff. PECL Diff. PECL
I
11 12 9 10
I
8
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HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2043 Pin Assignment and Descriptions (Continued)
S2042/S2043
Pin Name
SYNCEN
Level
Static MultiLevel TTL
I/O
I
Pin #
3
Description
(Multilevel.) When HIGH, enables sync detection. Detection of the sync pattern (K28.5:0011111010, positive running disparity) will enable the word boundary for the data to follow. When open (not connected), REFCLK replaces internal bit clock to facilitate factory testing. In this mode of operation, sync detection is always enabled. When LOW, data is treated as unframed data. (Multilevel.) Input used to select the reference clock frequency. (See Table 4.)
REFSEL
Static MultiLevel TTL Static MultiLevel TTL TTL +3.3V GND +3.3V/ +5V +3.3V GND GND
I
30
RATESEL
I
20
(Multilevel.) Input used to select the operating speed of the receiver. (See Table 4.)
LOCK_REF ECLVCC TTLGND TTLVCC AVCC AVEE ECLVEE
I - - - - - -
50 13, 27, 39 16, 33, 41, 46 19, 23, 36, 44 7 5, 6 1, 26, 47
When LOW, forces the PLL to lock to the REFCLK input and ignore the serial data inputs. Core Power Supply TTL Ground TTL Power Supply (+5V if TTL) Analog Power Supply Analog Ground Core Ground
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S2042/S2043
Figure 7. 52 PQFP Pinouts
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
52 51 50 49 48 47 46 45 44 43 42 41 40
52 51 50 49 48 47 46 45 44 43 42 41 40
LOCKDETN SYNC LCK_REF RCLK RCLKN ECLVEE TTLGND D19 TTLVCC D18 D17 TTLGND D16
ECLVEE ECLVEE D19 D18 D17 D16 ECLVEE ECLVCC D15 D14 D13 D12 ECLVEE
14 15 16 17 18 19 20 21 22 23 24 25 26
TTLVCC= +5V or +3.3V AVCC= +3.3V ECLVCC= +3.3V ECLIOVCC = +3.3V ECLIOVEE = 0V TTLGND= 0V ECLVEE= 0V AVEE= 0V
TTLGND RATESEL REFCLK TTLVCC REFSEL DWS TEST ECLVCC D0 D1 D2 D3 AVEE
10
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D0 D1 TTLGND D2 D3 TTLVCC RATESEL D4 D5 TTLVCC D6 D7 ECLVEE
14 15 16 17 18 19 20 21 22 23 24 25 26
OE1 OE0 ECLIOVCC TLY TLX ECLIOVEE ECLIOVEE TX TY ECLIOVCC TCLKN TCLK ECLVEE
1 2 3 4 5 6 7 8 9 10 11 12 13
S2042
TOP VIEW
39 38 37 36 35 34 33 32 31 30 29 28 27
ECLVCC D11 D10 D9 D8 ECLVEE AVEE AVCC D7 D6 D5 D4 AVCC
ECLVEE REFCLK SYNCEN DWS AVEE AVEE AVCC LPEN RX RY RLX RLY ECLVCC
1 2 3 4 5 6 7 8 9 10 11 12 13
S2043
TOP VIEW
39 38 37 36 35 34 33 32 31 30 29 28 27
ECLVCC D15 D14 TTLVCC D13 D12 TTLGND D11 D10 REFSEL D9 D8 ECLVCC
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 8. 52 PQFP Package
S2042/S2043
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S2042/S2043
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Absolute Maximum Ratings
PARAMETER Case Temperature under Bias Junction Temperature under Bias Storage Temperature Voltage on VCC with Repect to GND Voltage on any TTL Input Pin Voltage on any PECL Input Pin TTL Output Sink Current TTL Output Source Current High Speed PECL Output Source Current Static Discharge Voltage 500 MIN -55 -55 -65 -0.5 -0.5 0 TYP MAX 125 150 150 +7.0 +5.5V VCC 8 8 50 UNIT C C C V V V mA mA mA V
Recommended Operating Conditions
PARAMETER Ambient Temperature under Bias Junction Temperature under Bias Voltage on TTLVCC with Respect to GND 5V Operation 3.3V Operation Voltage on any TTL Input Pin Voltage on ECLVCC with respect to GND Voltage on any PECL Input Pin MIN 0 TYP MAX 70 130 UNIT C C
4.75 3.13 0 3.13 ECLVCC -2.0V
5.0 3.3
5.25 3.47 TTLVCC
V V V V V
3.3
3.47 ECLVCC
Reference Clock Requirements
Parameters
FT FT TD1-2 TRCR, TRCF --
Description
Frequency Tolerance S2042 Frequency Tolerance S2043 Symmetry REFCLK Rise and Fall Time Random Jitter
Min
-100 -100 40 --
Max
+100 +100 60 2
Units
ppm ppm % ns ps
Conditions
-- -- Duty Cycle at 50% pt. 20 - 80% Peak-to-Peak
12
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HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042 DC Characteristics
Parameters
VOH
S2042/S2043
Description
Output HIGH Voltage (TTL) - 3.3V Power Supply - 3.3V Power Supply - 5V Power Supply Output LOW Voltage (TTL) - 3.3V Power Supply - 5V Power Supply Input HIGH Voltage (TTL) Input LOW Voltage (TTL) Input HIGH Current (TTL) Input LOW Current (TTL) Supply Current Power Dissipation
Single-ended REFCLK input swing
Min
2.1 2.2 2.7
Typ
Max
Units
V V V
Conditions
VCC = min, IOH = -2.4mA VCC = min, IOH = -.1mA VCC = min, IOH = -1mA VCC = min, IOL = 2.4mA VCC = min, IOL = 4mA IH 1mA at VIH = 5.5V -- VIN = 2.4V VIN = 0.5V Outputs open, VCC = VCC max Outputs open, VCC = VCC max AC coupled 50 to VCC -2.0V
VOL
.5 .5 2.0 0 -- -500 -- -- -- -- 123 .406 440 600 -- -- 5.5 0.8 50 -50 160 .554 1300 1600
V V V V A A mA W mV mV
VIH VIL IIH IIL ICC PD VINCLK VOUT
Serial Output Voltage Swing
S2043 DC Characteristics
Parameters
VOH
Description
Output HIGH Voltage (TTL) - 3.3V Power Supply - 3.3V Power Supply - 5V Power Supply Output LOW Voltage (TTL) - 3.3V Power Supply - 5V Power Supply Input HIGH Voltage (TTL) Input LOW Voltage (TTL) Input HIGH Current (TTL) Input LOW Current (TTL) Supply Current - 10-Bit Mode - 20-Bit Mode Power Dissipation
- 3.3V Supply, 10-Bit Mode - 3.3V Supply, 20-Bit Mode - 5V Supply, 10-Bit Mode - 5V Supply, 20-Bit Mode
Single-ended REFCLK input swing
Min
2.1 2.2 2.7
Typ
Max
Units
V V V
Conditions
VCC = min, IOH = -2.4mA VCC = min, IOH = -.1mA VCC = min, IOH = -1mA VCC = min, IOL = 2.4mA VCC = min, IOL = 8mA IH 1mA at VIH = 5.5V -- VIN = 2.4V VIN = 0.5V Outputs open, VCC = VCC max Outputs open, VCC = VCC max Outputs open, VCC = VCC max Outputs open, VCC = VCC max Outputs open, VCC = VCC max Outputs open, VCC = VCC max AC coupled
VOL
.5 .5 2.0 0 -- -500 -- -- -- -- 187 194 .617 .640 .728 .778 440 100 -- 5.5 0.8 50 -50 256 267 .887 .925 1.08 1.142 1300 1300
V V V V A A mA mA W W W W mV mV
VIH VIL IIH IIL ICC
PD
VINCLK VDIFF
Min. differential input voltage swing for differential PECL inputs
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S2042/S2043
Table 5. AC Characteristics
Parameters
T1 T2 T3 T4 T5 TCR , TCF TSDR , TSDF T6 TDC
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Description
REFCLK to TCLK Data setup w.r.t. REFCLK Data hold w.r.t. REFCLK Data setup w.r.t. TCLK Data hold w.r.t. TCLK TCLK rise and fall time Serial data rise and fall TCLK to TCLKN Skew TCLK, TCLKN Duty Cycle
Min
1.0 1.0 2.0 5 1 -- -- -- 40
Max
4.0 -- --
Units
ns ns ns ns ns
Conditions
-- -- --
5.0 300 1 60
ns ps ns %
10% to 90%, tested on a sample basis. 20% to 80%, tested on a sample basis. Tested on a sample basis. --
Transmitter Output Jitter Allocation
TJRMS TDJ Serial data output random jitter (RMS) Serial data output deterministic jitter (p-p) -- -- 20 100 ps ps RMS, tested on a sample basis. Measured with 1010 pattern. Peak-to-peak, tested on a sample basis. Measured with IDLE pattern.
Note: All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V). All TTL AC measurements are assumed to have the output load of 10pF.
Table 6. S2043 Receiver Timing
Parameters
T3 T4 T5 T6
Description
RCLK to RCLKN skew Data set-up time Data hold time Data set-up time
Min
-- 3.0 1.5 2.5
Max
1 -- -- --
Units
ns ns ns ns
Conditions
Tested on a sample basis. 1062 Mbit/sec, 10-bit mode. 1062 Mbit/sec, 10-bit mode. 1062, 531 Mbit/sec, 20-bit mode. 531, 266 Mbit/sec, 20-bit mode. 1062, 531 Mbit/sec, 20-bit mode. 531, 266 Mbit/sec, 20-bit mode. 10% to 90%, tested on a sample basis. 10% to 90%, tested on a sample basis. 20% to 80%.
8B/10B IDLE pattern sample basis
T7
Data hold time
7.5
--
ns
TRCR , TRCF TDR , TDF TSDR , TSDF TLOCK Duty Cycle Input Jitter Tolerance
RCLK rise and fall time Data Output rise and fall time Serial data input rise and fall Data acquisition lock time @ <1.0625Gb/s RCLK/RCLKN Duty Cycle Input data eye opening allocation at receiver input for BER 1E-12
-- -- -- -- 40% 30%
5.0 5.0 300 2.4 60% --
ns ns ps s
bit time
As specified in Fibre Channel FC-PH standard eye diagram jitter mask.
Note: All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V). All TTL AC measurements are assumed to have the output load of 10pF.
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Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 9. Transmitter Timing Diagram (531, 266 Mbits/sec, 10-bit mode)
S2042/S2043
REFCLK
10 BIT DATA (D10-D19)
T2 T3 T4 T5
TCLKN
T1 T6
TCLK SERIAL DATA OUT
11 D10 12 13 14 15 16 17 18 D19 D10 11 12 13 14 15 16 17 18 D19
Figure 10. Transmitter Timing Diagram (531, 266 Mbits/sec, 20-bit mode)
REFCLK
T2 T3
20 BIT DATA
T4 T5
TCLKN
T1 T6
TCLK SERIAL DATA OUT
1 D0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 D19
Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333
15
S2042/S2043
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 11. Transmitter Timing Diagram (1062 Mbits/sec, 10-bit mode)
REFCLK (106.25 MHz)
10 BIT DATA
T2 T3 T4 T5
TCLKN (53.125 MHz)
T1 T6
TCLK (53.125 MHz) SERIAL DATA OUT
11 D10 12 13 14 15 16 17 18 D19 D10 11 12 13 14 15 16 17 18 D19
Figure 12. Transmitter Timing Diagram (1062 Mbits/sec, 20-bit mode)
REFCLK (53.125 MHz)
T2 T3
20 BIT DATA
T4 T5
TCLKN (53.125 MHz)
T1 T6
TCLK (53.125 MHz) SERIAL DATA OUT
1 D0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 D19
16
Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 13. Receiver Timing Diagram (531, 266 Mbits/sec, 10-bit mode)
SERIAL DATA IN REFCLK RCLKN
1.4V 11 D10 12 13 14 15 16 17 D19 18 11 12 13 14 15 16 17 D19 18
S2042/S2043
D10
RCLK 10 BIT DATA K28.5 DATA
T3 2.0V .8V
SYNC
T4
T5
T4
T5
Figure 14. Receiver Timing Diagram (531 Mbits/sec, 20-bit mode)
SERIAL DATA IN REFCLK RCLK
1 D0 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17
D19 18
RCLKN 20 BIT DATA and SYNC
T6 T7
T3
Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333
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S2042/S2043
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 15. Receiver Timing Diagram (1062 Mbits/sec, 10-bit mode)
11 D10 12 13 14 15 16 17 D19 18 11 12 13 14 15 16 17 D19 18
SERIAL DATA IN REFCLK (106.25 MHz) RCLKN (53.125 MHz)
D10
1.4V
RCLK (53.125 MHz) 10 BIT DATA K28.5 DATA
T3 2.0V .8V
SYNC
T4
T5
T4
T5
Figure 16. Receiver Timing Diagram (1062 Mbits/sec, 20-bit mode)
SERIAL DATA IN REFCLK (53.125 MHz) RCLK (53.125 MHz)
1 D0 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17
D19 18
RCLKN (53.125 MHz) 20 BIT DATA and SYNC
T6 T7
T3
18
Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 17. Serial Input Rise and Fall Time
80% 50% 20% 80% 50% 20%
S2042/S2043
ACQUISITION TIME
With the input eye diagram shown in Figure 21, the S2043 will recover data with a 10-9 BER within 50 bit times after an instantaneous phase shift of the incoming data.
Tr
Tf
Figure 18. Serial Output Load
Figure 21. Acquisition Time Eye Diagram
1.3
50 VDD - 2.0V
Normalized Amplitude
1.0 0.8 0.7 0.5 0.3 0.2 0 -0.2 0 .10 .30 .40 .60 .70 .90 1.0
Figure 19.TTL Input and Output Rise and Fall Time
90% 50% 10% 90% 50% 10%
Tr
Tf
Normalized Time
Figure 20. Receiver Input Eye Diagram Jitter Mask
Bit Time
Amplitude
30%
Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333
19
S2042/S2043
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Ordering Information
GRADE
S - commercial
TRANSMITTER
2042
PACKAGE
B - 52 PQFP
SPEED GRADE
10 - 1062, 531, 266 Mbit/s
GRADE
S - commercial
RECEIVER
2043
PACKAGE
B - 52 PQFP
SPEED GRADE
10 - 1062, 531, 266 Mbit/s
X
XXXX
X
Package
-
XX
Speed Grade
Grade Part number
Example:
S2042B-05 -- S2042 in a 52 PQFP package operating at 531 or 266 Mbit/sec rates.
Applied Micro Circuits Corporation * 6195 Lusk Blvd., San Diego, CA 92121 Phone: (619) 450-9333 Fax: (619) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1997 Applied Micro Circuits Corporation June 2, 1997
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Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333

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