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Device Features
Fully Qualified Bluetooth System Bluetooth v1.1 and v1.2 Specification Compliant 1.8V core, 1.8 to 3.6V I/O Ultra Low Power Consumption Excellent Compatibility with Cellular Telephones Minimum External Components Integrated 1.8V Regulator Dual UART Ports (BC313141A only) Available in UART and USB Versions Built-In Self-Test Reduces Production Test Times RoHS Compliant
_aiEceEPJolj=pm
Single Chip Bluetooth(R) v1.2 System
Production Information Data Sheet for BC313141A (UART) and BC313143A (USB) November 2006
_aiEceEPJolj=pm Product Data Sheet
General Description
_aiEceEPJolj=pm is a single chip radio and baseband chip for Bluetooth wireless technology 2.4GHz systems. It is implemented in 0.18m CMOS technology. The 4Mbit ROM is metal programmable, which enables an eight week turn-around from approval of firmware to production samples.
Applications
Cellular Handsets Personal Digital Assistants Digital cameras and other high volume consumer products Space critical applications
RAM
SPI
BlueCore3-ROM CSP has been designed to reduce the number of external components required, which ensures production costs are minimised. The device incorporates auto-calibration and built-in self-test (BIST) routines to simplify development, type approval and production test. All hardware and device firmware is fully compliant with the Bluetooth specification v1.2.
Baseband DSP RF IN RF OUT 2.4 GHz Radio MCU I/O
UART/USB
PIO
ROM
PCM
XTAL
BlueCore3-ROM CSP System Architecture
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Contents
Contents
Device Features..................................................................................................................................................... 1 Status Information ................................................................................................................................................ 7 1 2 Key Features .................................................................................................................................................. 8 CSP Package Information ............................................................................................................................. 9 2.1 BC313141AXX-IXF and BC313143AXX-IXF Pinout Diagram ................................................................. 9 2.2 BC313141AXX-IXF Device Terminal Functions .................................................................................... 10 2.3 BC313143AXX-IXF Device Terminal Functions .................................................................................... 13 3 4 Electrical Characteristics ............................................................................................................................ 16 Radio Characteristics .................................................................................................................................. 20 4.1 Temperature +20C ............................................................................................................................... 20 4.1.1 Transmitter ................................................................................................................................. 20 4.1.2 Receiver ..................................................................................................................................... 22 4.2 Temperature -40C................................................................................................................................ 24 4.2.1 Transmitter ................................................................................................................................. 24 4.2.2 Receiver ..................................................................................................................................... 24 4.3 Temperature -25C................................................................................................................................ 25 4.3.1 Transmitter ................................................................................................................................. 25 4.3.2 Receiver ..................................................................................................................................... 25 4.4 Temperature +85C ............................................................................................................................... 26 4.4.1 Transmitter ................................................................................................................................. 26 4.4.2 Receiver ..................................................................................................................................... 26 4.5 Temperature +105C ............................................................................................................................. 27 4.5.1 Transmitter ................................................................................................................................. 27 4.5.2 Receiver ..................................................................................................................................... 27 4.6 Power Consumption .............................................................................................................................. 28 5 6 Device Diagram ............................................................................................................................................ 30 Description of Functional Blocks ............................................................................................................... 31 6.1 RF Receiver........................................................................................................................................... 31 6.1.1 Low Noise Amplifier ................................................................................................................... 31 6.1.2 Analogue to Digital Converter .................................................................................................... 31 6.2 RF Transmitter....................................................................................................................................... 31 6.2.1 IQ Modulator .............................................................................................................................. 31 6.2.2 Power Amplifier .......................................................................................................................... 31 6.3 RF Synthesiser ...................................................................................................................................... 31 6.4 Clock Input and Generation ................................................................................................................... 31 6.5 Baseband and Logic .............................................................................................................................. 32 6.5.1 Memory Management Unit ......................................................................................................... 32 6.5.2 Burst Mode Controller ................................................................................................................ 32 6.5.3 Physical Layer Hardware Engine DSP....................................................................................... 32 6.5.4 RAM ........................................................................................................................................... 32 6.5.5 ROM........................................................................................................................................... 32 6.5.6 USB (BC313143A only) ............................................................................................................. 32 6.5.7 Synchronous Serial Interface ..................................................................................................... 33 6.5.8 UART (BC313141A only) ........................................................................................................... 33 6.5.9 Audio PCM Interface .................................................................................................................. 33 6.6 Microcontroller ....................................................................................................................................... 33 6.6.1 Programmable I/O...................................................................................................................... 33 CSR Bluetooth Software Stacks ................................................................................................................. 34 7.1 BlueCore HCI Stack .............................................................................................................................. 34 7.1.1 Key Features of the HCI Stack - Standard Bluetooth Functionality ........................................... 35 7.1.2 Key Features of the HCI Stack - Extra Functionality .................................................................. 36 7.2 BlueCore RFCOMM Stack..................................................................................................................... 37 7.2.1 Key Features of the BlueCore3-ROM CSP RFCOMM Stack ..................................................... 38 Production Information (c) Cambridge Silicon Radio Limited 2005-2006
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Contents
7.3 BCHS Software ..................................................................................................................................... 39 7.4 Additional Software for Other Embedded Applications .......................................................................... 39 7.5 CSR Development Systems .................................................................................................................. 39 8 Device Terminal Descriptions..................................................................................................................... 40 8.1 RF Ports ................................................................................................................................................ 40 8.1.1 TX_A and TX_B ......................................................................................................................... 40 8.1.2 Transmitter S-Parameters .......................................................................................................... 41 8.1.3 Transmit Port Impedances ......................................................................................................... 42 8.1.4 Receiver S-Parameters.............................................................................................................. 45 8.1.5 Receive Port Impedances .......................................................................................................... 46 8.2 External Reference Clock Input (XTAL_IN) ........................................................................................... 47 8.2.1 External Mode ............................................................................................................................ 47 8.2.2 XTAL_IN Impedance in External Mode ...................................................................................... 47 8.2.3 Clock Timing Accuracy............................................................................................................... 48 8.2.4 Clock Start-Up Delay.................................................................................................................. 48 8.2.5 Input Frequencies and PS Key Settings..................................................................................... 49 8.3 Crystal Oscillator (XTAL_IN, XTAL_OUT) ............................................................................................. 50 8.3.1 XTAL Mode ................................................................................................................................ 50 8.3.2 Load Capacitance ...................................................................................................................... 51 8.3.3 Frequency Trim .......................................................................................................................... 51 8.3.4 Transconductance Driver Model ................................................................................................ 52 8.3.5 Negative Resistance Model ....................................................................................................... 52 8.3.6 Crystal PS Key Settings ............................................................................................................. 52 8.3.7 Crystal Oscillator Characteristics ............................................................................................... 53 8.4 UART Interface (BC313141A only)........................................................................................................ 56 8.4.1 UART Bypass............................................................................................................................. 58 8.4.2 UART Configuration while RESET is Active............................................................................... 58 8.4.3 UART Bypass Mode................................................................................................................... 58 8.4.4 Current Consumption in UART Bypass Mode ............................................................................ 58 8.5 USB Interface (BC313143A only) .......................................................................................................... 59 8.5.1 USB Data Connections .............................................................................................................. 59 8.5.2 USB Pull-Up Resistor................................................................................................................. 59 8.5.3 Power Supply ............................................................................................................................. 59 8.5.4 Self Powered Mode.................................................................................................................... 60 8.5.5 Bus Powered Mode.................................................................................................................... 61 8.5.6 Suspend Current ........................................................................................................................ 62 8.5.7 Detach and Wake_Up Signalling................................................................................................ 62 8.5.8 USB Driver ................................................................................................................................. 62 8.5.9 USB 1.1 Compliance.................................................................................................................. 63 8.5.10 USB 2.0 Compatibility ................................................................................................................ 63 8.6 Serial Peripheral Interface ..................................................................................................................... 64 8.6.1 Instruction Cycle......................................................................................................................... 64 8.6.2 Writing to BlueCore3-ROM CSP ................................................................................................ 65 8.6.3 Reading from BlueCore3-ROM CSP.......................................................................................... 65 8.6.4 Multi Slave Operation................................................................................................................. 65 8.7 PCM CODEC Interface.......................................................................................................................... 66 8.7.1 PCM Interface Master/Slave ...................................................................................................... 67 8.7.2 Long Frame Sync....................................................................................................................... 68 8.7.3 Short Frame Sync ...................................................................................................................... 68 8.7.4 Multi Slot Operation.................................................................................................................... 69 8.7.5 GCI Interface.............................................................................................................................. 69 8.7.6 Slots and Sample Formats ......................................................................................................... 70 8.7.7 Additional Features .................................................................................................................... 70 8.7.8 PCM Timing Information ............................................................................................................ 71 8.7.9 PCM Slave Timing ..................................................................................................................... 73 8.7.10 PCM_CLK and PCM_SYNC Generation.................................................................................... 74 8.7.11 PCM Configuration..................................................................................................................... 75 8.8 I/O Parallel Ports ................................................................................................................................... 77 8.9 TCXO Enable OR Function ................................................................................................................... 78 8.10 RESETB ................................................................................................................................................ 79
_aiEceEPJolj=pm Product Data Sheet
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Contents
9
8.10.1 Pin States on Reset ................................................................................................................... 79 8.10.2 Status after Reset ...................................................................................................................... 80 8.11 Power Supply ........................................................................................................................................ 81 8.11.1 Voltage Regulator ...................................................................................................................... 81 8.11.2 Sequencing ................................................................................................................................ 81 8.11.3 Sensitivity to Disturbances ......................................................................................................... 81 Application Schematic................................................................................................................................. 82 9.1 BC313141AXX (UART) CSP Package .................................................................................................. 82 9.2 BC313143AXX (USB) CSP Package .................................................................................................... 83
10 PCB Design and Assembly Considerations .............................................................................................. 84 10.1 3.8mm x 3.4mm CSP 42-Ball Package ................................................................................................. 84 11 Package Dimensions ................................................................................................................................... 85 11.1 BC313141AXX-IXF and BC313143AXX-IXF CSP 42-Ball Package...................................................... 85 12 Tape and Reel Information .......................................................................................................................... 86 12.1 Tape Information ................................................................................................................................... 86 12.1.1 WLCSP Tape Orientation........................................................................................................... 86 12.1.2 Package Tape Dimensions ........................................................................................................ 87 12.2 Reel Information .................................................................................................................................... 88 13 Solder Profile................................................................................................................................................ 89 13.1 Typical Solder Re-flow Profile for Devices with Lead-Free Solder Balls ................................................ 89 14 Ordering Information ................................................................................................................................... 90 14.1 BlueCore3-ROM CSP............................................................................................................................ 90 15 Contact Information ..................................................................................................................................... 91 16 Document References ................................................................................................................................. 92 Terms and Definitions ........................................................................................................................................ 93 Document History ............................................................................................................................................... 95 List of Figures Figure 2.1: BlueCore3-ROM CSP Package (BC313141AXX-IXF and BC313143AXX-IXF) ................................... 9 Figure 5.1: BlueCore3-ROM CSP Device Diagram for CSP Package .................................................................. 30 Figure 7.1: BlueCore HCI Stack ............................................................................................................................ 34 Figure 7.2: BlueCore RFCOMM Stack .................................................................................................................. 37 Figure 8.1: Common Differential RF Input and Output Ports (Class 2) ................................................................. 40 Figure 8.2: RF Input/Output Diagram .................................................................................................................... 40 Figure 8.3: TX_A Output at Power Setting 35 ....................................................................................................... 42 Figure 8.4: TX_A Output at Power Setting 50 ....................................................................................................... 42 Figure 8.5: TX_A Output at Power Setting 63 ....................................................................................................... 43 Figure 8.6: TX_B Output at Power Setting 35 ....................................................................................................... 43 Figure 8.7: TX_B Output at Power Setting 50 ....................................................................................................... 44 Figure 8.8: TX_B Output at Power Setting 63 ....................................................................................................... 44 Figure 8.9: RX_A Balanced Receive Input Impedance ......................................................................................... 46 Figure 8.10: RX_B Balanced Receive Input Impedance ....................................................................................... 46 Figure 8.11: TCXO Clock Accuracy ...................................................................................................................... 48 Figure 8.12: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting......................................... 48 Figure 8.13: Crystal Driver Circuit ......................................................................................................................... 50 Figure 8.14: Crystal Equivalent Circuit .................................................................................................................. 50 Figure 8.15: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency............................. 53 Figure 8.16: Crystal Driver Transconductance vs. Driver Level Register Setting .................................................. 54 Figure 8.17: Crystal Driver Negative Resistance as a Function of Drive Level Setting ......................................... 55
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Contents
Figure 8.18: Universal Asynchronous Receiver .................................................................................................... 56 Figure 8.19: Break Signal...................................................................................................................................... 57 Figure 8.20: UART Bypass Architecture ............................................................................................................... 58 Figure 8.21: USB Connections for Self Powered Mode ........................................................................................ 60 Figure 8.22: USB Connections for Bus Powered Mode ........................................................................................ 61 Figure 8.23: USB_DETACH and USB_WAKE_UP Signal .................................................................................... 62 Figure 8.24: Write Operation ................................................................................................................................. 65 Figure 8.25: Read Operation................................................................................................................................. 65 Figure 8.26: BlueCore3-ROM CSP as PCM Interface Master............................................................................... 67
_aiEceEPJolj=pm Product Data Sheet
Figure 8.27: BlueCore3-ROM CSP as PCM Interface Slave................................................................................. 67 Figure 8.28: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................... 68 Figure 8.29: Short Frame Sync (Shown with 16-bit Sample) ................................................................................ 68 Figure 8.30: Multi Slot Operation with Two Slots and 8-bit Companded Samples ................................................ 69 Figure 8.31: GCI Interface..................................................................................................................................... 69 Figure 8.32: 16-Bit Slot Length and Sample Formats ........................................................................................... 70 Figure 8.33: PCM Master Timing Long Frame Sync ............................................................................................. 72 Figure 8.34: PCM Master Timing Short Frame Sync............................................................................................. 72 Figure 8.35: PCM Slave Timing Long Frame Sync ............................................................................................... 73 Figure 8.36: PCM Slave Timing Short Frame Sync............................................................................................... 74 Figure 8.37: Example TXCO Enable OR Function ................................................................................................ 78 Figure 9.1: Application Circuit for CSP Package ................................................................................................... 82 Figure 9.2: Application Circuit for CSP Package ................................................................................................... 83 Figure 12.1: BlueCore3-ROM CSP Package Dimensions..................................................................................... 85 Figure 13.1: CSP Tape and Reel Orientation........................................................................................................ 86 Figure 13.2: Package Tape Dimensions ............................................................................................................... 87 Figure 13.3: Tape Dimensions .............................................................................................................................. 87 Figure 13.4: Reel Dimensions ............................................................................................................................... 88 Figure 14.1: Typical Lead-Free Re-flow Solder Profile.......................................................................................... 89
List of Tables Table 8.1: Transmit Mode S-Parameters .............................................................................................................. 41 Table 8.2: Receive Mode S-Parameters ............................................................................................................... 45 Table 8.3: External Clock Specifications ............................................................................................................... 47 Table 8.4: PS Key Values for CDMA/3G phone TCXO Frequencies .................................................................... 49 Table 8.5: Crystal Oscillator Specification............................................................................................................. 52 Table 8.6: Possible UART Settings ....................................................................................................................... 56 Table 8.7: Standard Baud Rates ........................................................................................................................... 57 Table 8.8: USB Interface Component Values ....................................................................................................... 61 Table 8.9: Instruction Cycle for an SPI Transaction .............................................................................................. 64 Table 8.10: PCM Master Timing............................................................................................................................ 71 Table 8.11: PCM Slave Timing.............................................................................................................................. 73 Table 8.12: PSKEY_PCM_CONFIG32 Description............................................................................................... 75 Table 8.13: PSKEY_PCM_LOW_JITTER_CONFIG Description .......................................................................... 76 Table 8.14: Pin States of BlueCore3-ROM CSP on Reset.................................................................................... 79 Table 13.1: Reel Dimensions ................................................................................................................................ 88
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Contents
List of Equations Equation 8.1: Load Capacitance ........................................................................................................................... 51 Equation 8.2: Trim Capacitance ............................................................................................................................ 51 Equation 8.3: Frequency Trim ............................................................................................................................... 51 Equation 8.4: Pullability......................................................................................................................................... 51 Equation 8.5: Transconductance Required for Oscillation .................................................................................... 52 Equation 8.6: Equivalent Negative Resistance ..................................................................................................... 52 Equation 8.7: Baud Rate ....................................................................................................................................... 57 Equation 8.8: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock ............................ 74 Equation 8.9: PCM_SYNC Frequency Relative to PCM_CLK .............................................................................. 74
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Key Features
Status Information
The status of this Data Sheet is Production Information. CSR Product Data Sheets progress according to the following format: Advance Information Information for designers concerning CSR product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice. Pre-Production Information Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All electrical specifications may be changed by CSR without notice. Production Information Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications. Production Data Sheets supersede all previous document versions.
_aiEceEPJolj=pm Product Data Sheet
RoHS Compliance BlueCore3-ROM devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). Trademarks, Patents and Licenses Unless otherwise stated, words and logos marked with TM or (R) are trademarks registered or owned by Cambridge Silicon Radio Limited or its affiliates. Bluetooth(R) and the Bluetooth logos are trademarks owned by Bluetooth SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have been trademarked by their respective owners. Windows(R), Windows 98TM, Windows 2000TM, Windows XPTM and Windows NTTM are registered trademarks of the Microsoft Corporation. OMAPTM is a trademark of Texas Instruments Inc.
The publication of this information does not imply that any license is granted under any patent or other rights owned by Cambridge Silicon Radio Limited. CSR reserves the right to make technical changes to its products as part of its development programme. While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors. CSR's products are not authorised for use in life-support or safety-critical applications.
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Key Features
1
Key Features
Baseband and Software
Internal programmed 4Mbit ROM for complete system solution 32kbyte on-chip RAM allows full speed Bluetooth data transfer, mixed voice and data, plus full seven slave Piconet operation Dedicated logic for forward error correction, header error control, access code correlation, demodulation, cyclic redundancy check, encryption bit stream generation, whitening and transmit pulse shaping. Supports all Bluetooth 1.2 features including eSCO Transcoders for A-law, -law and linear voice from host and A-law, -law and CVSD voice over air Common TX/RX terminals simplifies external matching; eliminates external antenna switch BIST minimises production test time. No external trimming is required in production Full RF reference designs are available Bluetooth v1.2 specification compliant
Radio
_aiEceEPJolj=pm Product Data Sheet
Transmitter
+6dBm RF transmit power with level control from on-chip 6-bit DAC over a dynamic range >30dB Class 2 and Class 3 support without the need for an external power amplifier or TX/RX switch
Receiver
Integrated channel filters Digital demodulator for improved sensitivity and co-channel rejection Real time digitised RSSI available on HCI interface Fast AGC for enhanced dynamic range
Physical Interfaces
Synchronous serial interface up to 4M Baud for system debugging UART interface with programmable Baud rate up to 1.5M Baud with an optional bypass mode (BC313141A only) Full speed USB interface supports OHCI and UHCI host interfaces. Compliant with USB v2.0 (BC3131143A only) Synchronous bi-directional serial programmable audio interface
Synthesiser
Fully integrated synthesizer requires no external VCO varactor diode, resonator or loop filter Compatible with crystals between 8 and 40MHz (in multiples of 250kHz) or an external clock Accepts 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz TCXO frequencies for GSM and CDMA devices with either sinusoidal or logic level signals
Bluetooth Stack Running on an Internal Microcontroller
CSR's Bluetooth protocol stack runs on-chip in a variety of configurations: Standard HCI (UART or USB) Fully embedded to RFCOMM Customer specific builds with embedded application code
Auxiliary Features
Crystal oscillator with built-in digital trimming Power management includes digital shut down and wake up commands with an integrated low power oscillator for ultra-low Park/Sniff/Hold mode `Clock request' output to control an external clock source Device can run in low power modes from an external 32KHz clock signal Auto Baud Rate setting for different TCXO frequencies Auto Baud Rate setting for different TCXO frequencies On-chip low dropout linear regulator, producing 1.8V output from 2.2-4.2V input Power-on-reset cell detects low supply voltage Arbitrary sequencing of power supplies is permitted
Package Options
42-ball CSP 3.8 x 3.4 x 0.7mm 0.5mm pitch
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CSP Package Information
2
2.1
CSP Package Information
BC313141AXX-IXF and BC313143AXX-IXF Pinout Diagram
_aiEceEPJolj=pm Product Data Sheet
Figure 2.1: BlueCore3-ROM CSP Package (BC313141AXX-IXF and BC313143AXX-IXF)
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CSP Package Information
2.2
Radio TX_A TX_B
BC313141AXX-IXF Device Terminal Functions
Ball D1 E1 Pad Type Analogue Analogue Description Transmitter output/Switched Receiver input Complement of TX_A
Synthesiser and Oscillator XTAL_IN XTAL_OUT
Ball A1 A3
Pad Type Analogue Analogue
Description
_aiEceEPJolj=pm Product Data Sheet
For crystal or external clock input Drive for crystal
PCM Interface PCM_OUT PCM_IN PCM_SYNC PCM_CLK
Ball D5 B7 C5 B6
Pad Type CMOS output, tri-state with weak internal pull-down CMOS input, with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down
Description Synchronous data output Synchronous data input Synchronous data sync Synchronous data clock
UART UART_TX UART_RX UART_RTS UART_CTS
Ball D4 B5 A7 C4
Pad Type CMOS output, tri-state with weak internal pull-up CMOS input with weak internal pull-down CMOS output, tri-state with weak internal pull-up CMOS input with weak internal pull-down
Description UART data output active high UART data input active high UART request to send active low UART clear to send active low
Test and Debug RESETB SPI_CSB SPI_CLK SPI_MOSI SPI_MISO TEST_EN
Ball E6 F6 F5 F4 F7 F3
Pad Type CMOS input with weak internal pull-up CMOS input with weak internal pull-up CMOS input with weak internal pull-down CMOS input with weak internal pull-down CMOS output, tri-state with weak internal pull-down CMOS input with strong internal pull-down
Description Reset if low. Input debounced so must be low for >5ms to cause a reset Chip select for Synchronous Serial Interface active low Serial Peripheral Interface clock Serial Peripheral Interface data input Serial Peripheral Interface data output For test purposes only (leave unconnected)
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CSP Package Information
PIO Port PIO[0]
Ball D3
Pad Type Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional Bi-directional
Description Programmable input/output line
PIO[1]
C3
Programmable input/output line
PIO[2]
E3
Programmable input/output line
_aiEceEPJolj=pm Product Data Sheet
PIO[3]
F2
Programmable input/output line
PIO[4]
E5
Programmable input/output line
PIO[5]
E4
Programmable input/output line
PIO[6]
D7
Programmable input/output line
PIO[7] AIO[0] AIO[2]
D6 C2 A5
Programmable input/output line Programmable input/output line Programmable input/output line
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CSP Package Information
Power Supplies and Control VREG_IN VDD_USB VDD_PIO VDD_PADS VDD_CORE VDD_VCO VDD_RADIO VDD_ANA VSS_DIG VSS_PIO VSS_PADS VSS_VCO VSS_RADIO VSS_ANA
Ball A2 B4 F1 E7 C6 B1 C1 A4 C7 E2 A6 B2 D2 B3
Pad Type Regulator input VDD VDD VDD VDD VDD VDD VDD/Regulator output VSS VSS VSS VSS VSS VSS
Description Regulator input Positive supply for UART ports Positive supply for PIO [3:0] Positive supply for all other digital input/output ports
_aiEceEPJolj=pm Product Data Sheet
Positive supply for internal digital circuitry Positive supply for VCO and synthesiser circuitry Positive supply for RF circuitry Positive supply for analogue circuitry and 1.8V regulated output Ground connection for internal digital circuitry and digital ports Ground connection for digital ports Ground connection for digital ports Ground connections for VCO and synthesiser Ground connections for RF circuitry Ground connections for analogue circuitry
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CSP Package Information
2.3
Radio TX_A TX_B
BC313143AXX-IXF Device Terminal Functions
Ball D1 E1 Pad Type Analogue Analogue Description Transmitter output/Switched Receiver input Complement of TX_A
Synthesiser and Oscillator XTAL_IN XTAL_OUT
Ball A1 A3
Pad Type Analogue Analogue
Description
_aiEceEPJolj=pm Product Data Sheet
For crystal or external clock input Drive for crystal
PCM Interface PCM_OUT PCM_IN PCM_SYNC PCM_CLK
Ball D5 B7 C5 B6
Pad Type CMOS output, tri-state with weak internal pull-down CMOS input, with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down
Description Synchronous data output Synchronous data input Synchronous data sync Synchronous data clock
UART and USB UART_TX UART_RX USB_DP USB_DN
Ball D4 B5 C4 A7
Pad Type CMOS output, tri-state with weak internal pull-up CMOS input with weak internal pull-down Bi-directional Bi-directional
Description UART data output active high UART data input active high USB data plus with selectable internal 1.5k pull-up resistor USB data minus
Test and Debug RESETB SPI_CSB SPI_CLK SPI_MOSI SPI_MISO TEST_EN
Ball E6 F6 F5 F4 F7 F3
Pad Type CMOS input with weak internal pull-up CMOS input with weak internal pull-up CMOS input with weak internal pull-down CMOS input with weak internal pull-down CMOS output, tri-state with weak internal pull-down CMOS input with strong internal pull-down
Description Reset if low. Input debounced so must be low for >5ms to cause a reset Chip select for Synchronous Serial Interface active low Serial Peripheral Interface clock Serial Peripheral Interface data input Serial Peripheral Interface data output For test purposes only (leave unconnected)
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CSP Package Information
PIO Port PIO[0]
Ball D3
Pad Type Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional Bi-directional
Description Programmable input/output line
PIO[1]
C3
Programmable input/output line
PIO[2]
E3
Programmable input/output line
_aiEceEPJolj=pm Product Data Sheet
PIO[3]
F2
Programmable input/output line
PIO[4]
E5
Programmable input/output line
PIO[5]
E4
Programmable input/output line
PIO[6]
D7
Programmable input/output line
PIO[7] AIO[0] AIO[2]
D6 C2 A5
Programmable input/output line Programmable input/output line Programmable input/output line
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CSP Package Information
Power Supplies and Control VREG_IN VDD_USB VDD_PIO VDD_PADS VDD_CORE VDD_VCO VDD_RADIO VDD_ANA VSS_DIG VSS_PIO VSS_PADS VSS_VCO VSS_RADIO VSS_ANA
Ball A2 B4 F1 E7 C6 B1 C1 A4 C7 E2 A6 B2 D2 B3
Pad Type Regulator input VDD VDD VDD VDD VDD VDD VDD/Regulator output VSS VSS VSS VSS VSS VSS
Description Regulator input Positive supply for UART ports Positive supply for PIO [3:0] Positive supply for all other digital input/output ports
_aiEceEPJolj=pm Product Data Sheet
Positive supply for internal digital circuitry Positive supply for VCO and synthesiser circuitry Positive supply for RF circuitry Positive supply for analogue circuitry and 1.8V regulated output Ground connection for internal digital circuitry and digital ports Ground connection for digital ports Ground connection for digital ports Ground connections for VCO and synthesiser Ground connections for RF circuitry Ground connections for analogue circuitry
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Electrical Characteristics
3
Electrical Characteristics
Minimum -40C -0.40V -0.40V -0.40V VSS-0.4V Maximum 150C 2.20V 3.70V 5.60V VDD+0.4V
Absolute Maximum Ratings Rating Storage Temperature Supply Voltage: VDD_RADIO, VDD_VCO, VDD_ANA, and VDD_CORE Supply Voltage: VDD_PADS, VDD_PIO, VDD_USB Supply Voltage: VREG_IN Other Terminal Voltages Recommended Operating Conditions Operating Condition Operating Temperature Range Guaranteed RF performance range Supply Voltage: VDD_RADIO, VDD_VCO, VDD_ANA, and VDD_CORE Supply Voltage: VDD_PADS, VDD_PIO, VDD_USB Supply Voltage: VREG_IN
Note:
(1)
_aiEceEPJolj=pm Product Data Sheet
Minimum -40C -40C 1.70V 1.70V 2.20V
Maximum 105C 105C 1.90V 3.60V 4.20V(1)
The device will operate without damage with VREG_IN as high as 5.6V, however the RF performance is not guaranteed above 4.20V.
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Electrical Characteristics
Input/Output Terminal Characteristics Linear Regulator Normal Operation Output Voltage (Iload = 70mA / Vreg_IN = 3.0V) Temperature Coefficient Output Noise
(1)(2)
Minimum
Typical
Maximum
Unit
1.70 -250 70 5 25
1.78 35
1.85 250 1 50 50 4.2(6) 350 50
V ppm/C mV rms mV/A s mA A V mV A
_aiEceEPJolj=pm Product Data Sheet
Load Regulation (Iload < 100 mA) Settling Time
(1)(3)
Output current: Input Voltage
Maximum output current Minimum load current
Dropout Voltage (Iload = 70 mA) Quiescent Current (excluding Ioad, Iload < 1mA) Low Power Mode(4) Quiescent Current (excluding Ioad, Iload < 100A) Disabled Mode
(5)
4
7
10
A
Quiescent Current
Notes:
(1) (2) (3) (4) (5)
1.5
2.5
3.5
A
Regulator output connected to 47nF pure and 4.7F 2.2 ESR capacitors Frequency range 100Hz to 100kHz 1mA to 70mA pulsed load Low power mode is entered and exited automatically when the chip enters/leaves Deep Sleep mode Regulator is disabled when VREG_EN is pulled low. It is also disabled when VREG_IN is either open circuit or driven to the same voltage as VDD_ANA Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to damage the rest of BlueCore3, but output regulation and other specifications are no longer guaranteed at input voltages in excess of 4.2V.
(6)
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Electrical Characteristics
Input/Output Terminal Characteristics (Continued) Digital Terminals Input Voltage Levels VIL input logic level low VIH input logic level high Output Voltage Levels VOL output logic level low, (lO = 4.0mA), VDD=3.0V VOL output logic level low, (lO = 4.0mA), VDD=1.8V VOH output logic level high, (lO = -4.0mA), VDD=3.0V VOH output logic level high, (lO = -4.0mA), VDD=1.8V Input and Tri-State Current with: Strong pull-up Strong pull-down Weak pull-up Weak pull-down I/O pad leakage current CI Input Capacitance USB Terminals Input threshold VIL input logic level low VIH input logic level high Input leakage current VSS_USB< VIN< VDD_USB(1) CI Input capacitance Output Voltage levels To correctly terminated USB Cable VOL output logic level low VOH output logic level high 0.0 2.8 0.2 VDD_USB V V -1 2.5 1 10.0 A pF 0.57VDD_USB 0.3VDD_USB V V -100 10 -5 0.5 -1 1.0 Minimum -20 20 -1 1 0 Typical -10 100 -0.5 5 1 5.0 Maximum A A A A A pF Unit VDD-0.2 VDD-0.4 0.2 0.4 V V V V VDD=3.0V VDD=1.8V -0.4 -0.4 0.7VDD 0.8 0.4 VDD+0.4 V V V Minimum Typical Maximum Unit
_aiEceEPJolj=pm Product Data Sheet
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Electrical Characteristics
Crystal Oscillator Crystal frequency (2) Digital trim range Trim step size
(3) (3)
Minimum 8.0 5.0 2.0 870
Typical 6.2 0.1 1500
Maximum 40.0 8.0 2400
Unit MHz pF pF mS
Transconductance Negative resistance(4) External Clock
_aiEceEPJolj=pm Product Data Sheet
Input frequency(5) Clock input level(6) Allowable jitter XTAL_IN input impedance XTAL_IN input capacitance Power-on reset VDD_CORE falling threshold VDD_CORE rising threshold Hysteresis
Notes:
8.0 0.4 -
10 4
40.0 VDD_ANA 15 -
MHz V pk-pk ps rms k pF
1.40 1.50 0.05
1.50 1.60 0.10
1.60 1.70 0.15
V V V
VDD_CORE, VDD_RADIO, VDD_VCO and VDD_ANA are at 1.8V unless shown otherwise VDD_PADS, VDD_PIO and VDD_USB are at 3.0V unless shown otherwise The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative
(1) (2) (3)
Internal USB pull-up disabled Integer multiple of 250kHz The difference between the internal capacitance at minimum and maximum settings of the internal digital trim XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF Clock input can be any frequency between 8 and 40MHz in steps of 250kHz + CDMA/3G TCXO frequencies of 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz Clock input can either be sinusoidal or square wave if the peaks of the signal are below VSS_ANA or above VDD_ANA a DC blocking capacitor is required between the signal and XTAL_IN
(4) (5)
(6)
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Radio Characteristics
4
Radio Characteristics
BlueCore3-ROM CSP meets the Bluetooth specification v1.2 when used in a suitable application circuit between -40C and +105C. Tx output is guaranteed to be unconditionally stable over the guaranteed temperature range.
4.1 4.1.1
Temperature +20C Transmitter
_aiEceEPJolj=pm Product Data Sheet
Radio Characteristics VDD = 1.8V
Temperature = +20C Min Typ 5.0 1.0 2 35 0.5 780 -35 -45 -55 165 140 0.91 6 8 8 9 -40 -50 Max Bluetooth Specification -6 to +4(3) 16 1000 -20 -40 -40 140Maximum RF transmit power(1)(2) Variation in RF power over temperature range with compensation enabled ()(4) Variation in RF power over temperature range with (4) compensation disabled () RF power control range RF power range control resolution
(5)
(6)(7)
20dB bandwidth for modulated carrier Adjacent channel transmit power F=F0 2MHz Adjacent channel transmit power F=F0 3MHz(6)(7) Adjacent channel transmit power F=F0>3MHz f1avg "Maximum Modulation" f2max "Minimum Modulation" f2avg / f1avg Initial carrier frequency tolerance Drift Rate Drift (single slot packet) Drift (five slot packet) 2
nd rd (6)(7)
-
Harmonic content
3 Harmonic content
Note
(1)
BlueCore3-ROM CSP firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits. Measurement made using a PSKEY_LC_MAX_TX_POWER setting corresponds to a PSKEY_LC_POWER_TABLE power table entry of 63. Class 2 RF transmit power range, Bluetooth specification v1.2. To some extent these parameters are dependent on the matching circuit used, and its behaviour over temperature. Therefore these parameters may be beyond CSR's direct control. Resolution guaranteed over the range -5dB to -25dB relative to maximum power for Tx Level >20. Measured at F0 = 2441MHz. Up to three exceptions are allowed in v1.2 of the Bluetooth specification. BlueCore3-ROM CSP is guaranteed to meet the ACP performance as specified by the Bluetooth specification v1.2.
(2)
(3) (4)
(5) (6) (7)
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Radio Characteristics
Radio Characteristics
VDD = 1.8V Frequency (GHz) 0.869 - 0.894(1) 0.869 - 0.894
(2) (1) (3)
Temperature = +20C (Continued) Min Typ -135 -134 -137 -140 -141 -134 -136 -135 -132 -135 Max Cellular Band GSM 850 CDMA 850 GSM 900 GPS Unit
Emitted power in cellular bands measured at the unbalanced port of the balun. Output power 4dBm
0.925 - 0.960 1.570 - 1.580
_aiEceEPJolj=pm Product Data Sheet
1.805 - 1.880(1) 1.930 - 1.990
(4)
GSM 1800 / DCS 1800 PCS 1900 GSM 1900 CDMA 1900 W-CDMA 2000 W-CDMA 2000
dBm /Hz
1.930 - 1.990(1) 1.930 - 1.990 2.110 - 2.170 2.110 - 2.170
Notes:
(1) (2) (3) (4) (5) (2) (2) (5)
Integrated in 200kHz bandwidth and then normalised to a 1Hz bandwidth. Integrated in 1.2MHz bandwidth and then normalised to a 1Hz bandwidth. Integrated in 1MHz bandwidth. and then normalised to a 1Hz bandwidth Integrated in 30kHz bandwidth and then normalised to a 1Hz bandwidth. Integrated in 5MHz bandwidth and then normalised to a 1Hz bandwidth.
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Radio Characteristics
4.1.2
Receiver
VDD = 1.8V Temperature = +20C Min Min (1) (2) (1) (2) (1) (2) (1) (2) (1) (2)
Radio Characteristics
Frequency (GHz) Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER Frequency (MHz) Continuous power required to block Bluetooth reception (for sensitivity of -67dBm with 0.1% BER) measured at the unbalanced port of the balun. C/I co-channel Adjacent channel selectivity C/I F=F0 +1MHz Adjacent channel selectivity C/I F=F0 -1MHz Adjacent channel selectivity C/I F=F0 +2MHz Adjacent channel selectivity C/I F=F0 -2MHz Adjacent channel selectivity C/I FF0 -5MHz Adjacent channel selectivity C/I F=FImage(1) (2) Spurious output level (4)
Notes:
(1)
Typ -82 -85 -83 >10 Typ >0 >-10 >-12 >3 8 -3 -4 -35 -21 -44 -43 -23 -34 -160
Max Max -
Bluetooth Specification
Unit
2.402 2.441 2.480
-70 -20 Bluetooth Specification -10 -27 -27 -10 11 0 0 -30 -20 -40 -40 -9 -39 -
dBm
_aiEceEPJolj=pm Product Data Sheet
dBm Unit
30 - 2000 2000 - 2400 2500 - 3000 3000 - 3300
dBm
dB dB dB dB dB dB dB dB dBm dBm/Hz
-
Adjacent channel selectivity C/I FF0 +3MHz
(1) (2)
Maximum level of intermodulation interferers (3)
Up to five exceptions are allowed in v1.2 of the Bluetooth specification. BlueCore3-ROM CSP is guaranteed to meet the C/I performance as specified by the Bluetooth specification v1.2. Measured at F0 = 2441MHz Measured at f1-f2 = 5MHz. Measurement is performed in accordance with Bluetooth RF test RCV/CA/05/c. i.e. wanted signal at -64dBm Measured at the unbalanced port of the balun. Integrated in 100kHz bandwidth and then normalized to 1Hz. Actual figure is typically below -160dBm/Hz except for peaks of -57dBm at 1.6GHz, -48dBm inband at 2.4GHz and -60dBm at 3.2GHz
(2) (3)
(4)
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Radio Characteristics
Radio Characteristics
VDD = 1.8V Frequency (GHz)
Temperature = +20C (Continued) Min Typ >4(1) -8 1 >4 >4 -8 -10 >0 -13 0 >4 >4 -13 -16 Max Cellular Band GSM 850 CDMA GSM 900 GSM 1800 / DCS 1800 GSM 1900 / PCS 1900 CDMA 1900 W-CDMA 2000 GSM 850 CDMA GSM 900 GSM 1800 / DCS 1800 GSM 1900 / PCS 1900 CDMA 1900 W-CDMA 2000 dBm dBm Unit
Continuous power in cellular bands required to block Bluetooth reception (for sensitivity of -67dBm with 0.1% BER) measured at the unbalanced port of the balun.
0.824 - 0.849 0.824 - 0.849 0.880 - 0.915 1.710 - 1.785 1.850 - 1.910 1.850 - 1.910 1.920 - 1.980 0.824 - 0.849
_aiEceEPJolj=pm Product Data Sheet
Continuous power in cellular bands required to block Bluetooth reception (for sensitivity of -72dBm with 0.1% BER) measured at the unbalanced port of the balun.
0.824 - 0.849 0.880 - 0.915 1.710 - 1.785 1.850 - 1.910 1.850 - 1.910 1.920 - 1.980
Note:
(1)
0dBm if fBLOCKING <0.831GHz
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Radio Characteristics
4.2 4.2.1
Temperature -40C Transmitter
VDD = 1.8V Temperature = -40C Min Typ 5.5 35 0.5 780 -35 -41 165 135 0.85 10 8 8 10 Max Bluetooth Specification -6 to +4(2) 16 1000 -20 -40 140Radio Characteristics
Maximum RF transmit power(1) RF power control range RF power range control resolution 20dB bandwidth for modulated carrier Adjacent channel transmit power F=F0 2MHz(3) (4) Adjacent channel transmit power F=F0 3MHz f1avg "Maximum Modulation" f2max "Minimum Modulation" f2avg / f1avg Initial carrier frequency tolerance Drift Rate Drift (single slot packet) Drift (five slot packet)
Notes:
(1) (3) (4)
-
_aiEceEPJolj=pm Product Data Sheet
BlueCore3-ROM CSP firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measured at F0 = 2441MHz Up to three exceptions are allowed in v1.2 of the Bluetooth specification
(2) (3) (4)
4.2.2
Receiver
VDD = 1.8V Temperature = -40C Frequency (GHz) Min Typ -82.5 -85.5 -84 >10 Max -20 dBm -70 dBm Bluetooth Specification Unit
Radio Characteristics
Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER
2.402 2.441 2.480
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Radio Characteristics
4.3 4.3.1
Temperature -25C Transmitter
VDD = 1.8V Temperature = -25C Min Typ 5.5 35 0.5 780 -35 -45 165 135 0.87 8 8 7 8 Max Bluetooth Specification -6 to +4(2) 16 1000 -20 -40 140Radio Characteristics
Maximum RF transmit power(1) RF power control range RF power range control resolution 20dB bandwidth for modulated carrier Adjacent channel transmit power F=F0 2MHz(3) (4) Adjacent channel transmit power F=F0 3MHz f1avg "Maximum Modulation" f2max "Minimum Modulation" f2avg / f1avg Initial carrier frequency tolerance Drift Rate Drift (single slot packet) Drift (five slot packet)
Notes:
(1) (3) (4)
-
_aiEceEPJolj=pm Product Data Sheet
BlueCore3-ROM CSP firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measured at F0 = 2441MHz Up to three exceptions are allowed in v1.2 of the Bluetooth specification
(2) (3) (4)
4.3.2
Receiver
VDD = 1.8V Temperature = -25C Frequency (GHz) Min Typ -82.5 -85.5 -83.5 >10 Max -20 dBm -70 dBm Bluetooth Specification Unit
Radio Characteristics
Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER
2.402 2.441 2.480
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Radio Characteristics
4.4 4.4.1
Temperature +85C Transmitter
VDD = 1.8V Temperature = +85C Min Typ 3 35 0.5 800 -40 -45 165 130 0.90 10 8 11 10 Max Bluetooth Specification -6 to +4(2) 16 1000 -20 -40 140Radio Characteristics
Maximum RF transmit power(1) RF power control range RF power range control resolution 20dB bandwidth for modulated carrier Adjacent channel transmit power F=F0 2MHz(3) (4) Adjacent channel transmit power F=F0 3MHz f1avg "Maximum Modulation" f2max "Minimum Modulation" f2avg / f1avg Initial carrier frequency tolerance Drift Rate Drift (single slot packet) Drift (five slot packet)
Notes:
(1) (3) (4)
-
_aiEceEPJolj=pm Product Data Sheet
BlueCore3-ROM CSP firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measured at F0 = 2441MHz Up to three exceptions are allowed in v1.2 of the Bluetooth specification
(2) (3) (4)
4.4.2
Receiver
VDD = 1.8V Temperature = +85C Frequency (GHz) Min Typ -80.5 -82.5 -81.5 >10 Max -20 dBm -70 dBm Bluetooth Specification Unit
Radio Characteristics
Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER
2.402 2.441 2.480
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Radio Characteristics
4.5 4.5.1
Temperature +105C Transmitter
VDD = 1.8V Temperature = +105C Min Typ 1 35 0.5 820 -40 -45 165 130 0.87 15 9 12 12 Max Bluetooth Specification -6 to +4(2) 16 1000 -20 -40 140Radio Characteristics
Maximum RF transmit power(1) RF power control range RF power range control resolution 20dB bandwidth for modulated carrier Adjacent channel transmit power F=F0 2MHz(3) (4) Adjacent channel transmit power F=F0 3MHz f1avg "Maximum Modulation" f2max "Minimum Modulation" f2avg / f1avg Initial carrier frequency tolerance Drift Rate Drift (single slot packet) Drift (five slot packet)
Notes:
(1) (3) (4)
-
_aiEceEPJolj=pm Product Data Sheet
BlueCore3-ROM CSP firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits. Class 2 RF transmit power range, Bluetooth specification v1.2 Measured at F0 = 2441MHz. Up to three exceptions are allowed in v1.2 of the Bluetooth specification.
(2) (3) (4)
4.5.2
Receiver
VDD = 1.8V Temperature = +105C Frequency (GHz) Min Typ -79 -81 -79.5 >10 Max -20 dBm -70 dBm Bluetooth Specification Unit
Radio Characteristics
Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER
2.402 2.441 2.480
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Radio Characteristics
4.6
Power Consumption
Connection Type Master Master Slave Slave Master Master Slave Slave Master Master Master Master Master Slave Slave Slave Slave Slave Slave UART Rate (kbps) 115.2 115.2 115.2 115.2 115.2 115.2 921.6 921.6 921.6 921.6 38.4 38.4 38.4 38.4 38.4 38.4 38.4 38.4 38.4 38.4 38.4 38.4 Average 0.37 0.68 6.46 11.73 13.90 17.19 6.49 32.91 13.87 30.59 1.59 0.20 34.00 17.33 17.00 1.60 0.24 0.18 34.02 20.94 16.80 29 50 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A
Operation Mode Page scan Inquiry and page scan ACL No traffic ACL With file transfer ACL No traffic ACL With file transfer ACL No traffic ACL With file transfer ACL No traffic ACL With file transfer ACL 40ms sniff ACL 1.28s sniff SCO HV1 SCO HV3 SCO HV3 30ms sniff ACL 40ms sniff ACL 1.28s sniff Parked 1.28s beacon SCO HV1 SCO HV3 SCO HV3 30ms sniff Standby Host connection Reset (RESETB low)
Notes:
_aiEceEPJolj=pm Product Data Sheet
Firmware used: 17.11.
(1)
Low power mode on the linear regulator is entered and exited automatically when the chip enters/leaves Deep Sleep mode. For more information about the electrical characteristics of the linear regulator, see Electrical Characteristics in this document.
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Radio Characteristics
Typical Peak Current @ -20C to +85C Device Activity/State Peak current during cold boot Peak Tx current Master Peak Rx current Master Peak Tx current Slave Peak Rx current Slave Conditions Firmware REG_IN, VDD_PIO, VDD_PADS Host Interface Baud Rate Clock Source Output Power HCI 17.11 3.15V UART 115200 26MHz crystal 0dBm Current (mA) 50.7 42.8 35.1 43.5 39.4
_aiEceEPJolj=pm Product Data Sheet
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5
VDD_PIO
VDD_PIO
VDD_RADIO RESETB TEST_EN VDD_USB VDD_PADS VDD_CORE VDD_ANA VREG Out USB RAM USB_DN (USB Only Device)
VDD_VCO
VREG_IN
XTAL_OUT
XTAL_IN
_aiEceEPJolj=pm Product Data Sheet
BC313143ACS-ds-001Pi
In
Baseband and Logic
USB_DP (USB Only Device) Burst Mode Controller ROM SPI_CSB SPI_CLK SPI_MOSI SPI_MISO UART_TX ADC Memory Management Unit UART UART_RX UART_RTS (UART Only Device) UART_CTS (UART Only Device) PCM_OUT Audio PCM Interface PCM_IN PCM_SYNC PCM_CLK Physical Layer Hardware Engine
PIO[0]/RXEN
Clock Generation
Memory Mapped Control Status Synchronous Serial Interface
IQ DEMOD Demodulator
Device Diagram
LNA
RSSI
RF Receiver
IQ MOD DAC
TX_A
PA
TX_B
RF Transmitter Microcontroller
+45 -45 /N/N+1 Fref Interrupt Controller Tune Loop Filter RF Synthesiser
PIO[2] PIO[3] PIO[4] PIO[5] PIO[6] PIO[7] RISC Microcontroller Programmable I/O
Figure 5.1: BlueCore3-ROM CSP Device Diagram for CSP Package
Event Timer AIO AIO[2] AIO[0] VSS_PIO VSS_DIG VSS_VCO VSS_ANA VSS_PADS
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PIO[1]/TXEN
RF Synthesiser
VSS_RADIO
Device Diagram
Page 30 of 95
Description of Functional Blocks
6
6.1
Description of Functional Blocks
RF Receiver
The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be integrated on to the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input allows the radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband Code Division Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a digital Frequency Shift Keying (FSK) discriminator means that no discriminator tank is needed and its excellent performance in the presence of noise allows BlueCore3-ROM CSP to exceed the Bluetooth requirements for co-channel and adjacent channel rejection.
_aiEceEPJolj=pm Product Data Sheet
6.1.1
Low Noise Amplifier
The LNA operates in differential mode and is used for Class 2 operation.
6.1.2
Analogue to Digital Converter
The Analogue to Digital Converter (ADC) is used to implement fast Automatic Gain Control (AGC). The ADC samples the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the dynamic range of the receiver, improving performance in interference limited environments.
6.2 6.2.1
RF Transmitter IQ Modulator
The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot which results in a controlled modulation index. A digital baseband transmit filter provides the required spectral shaping.
6.2.2
Power Amplifier
The internal Power Amplifier (PA) has a maximum output power of +6dBm allowing BlueCore3-ROM CSP to be used in Class 2 and Class 3 radios without an external RF PA.
6.3
RF Synthesiser
The radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled Oscillator (VCO) screening can, varactor tuning diodes or LC resonators. The synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the Bluetooth specification V1.2.
6.4
Clock Input and Generation
The reference clock for the system is generated from a TCXO or crystal input between 8MHz and 40MHz. All internal reference clocks are generated using a phase locked loop, which is locked to the external reference frequency.
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Description of Functional Blocks
6.5 6.5.1
Baseband and Logic Memory Management Unit
The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data which is in transit between the host and the air or vice versa. The dynamic allocation of memory ensures efficient use of the available Random Access Memory (RAM) and is performed by hardware MMU to minimise the overheads on the processor during data/voice transfers.
6.5.2
Burst Mode Controller
_aiEceEPJolj=pm Product Data Sheet
During radio transmission the Burst Mode Controller (BMC) constructs a packet from header information previously loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During radio reception, the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor during transmission and reception.
6.5.3
Physical Layer Hardware Engine DSP
Dedicated logic is used to perform the following: Forward error correction Header error control Cyclic redundancy check Encryption Data whitening Access code correlation Audio transcoding The following voice data translations and operations are performed by firmware: A-law/-law/linear voice data (from host) A-law/-law/Continuously Variable Slope Delta (CVSD) (over the air) Voice interpolation for lost packets Rate mismatches The hardware supports all optional and mandatory features of Bluetooth v1.2 including AFH and eSCO.
6.5.4
RAM
32Kbytes of on-chip RAM is provided and is shared between the ring buffers used to hold voice/data for each active connection and the general purpose memory required by the Bluetooth stack.
6.5.5
ROM
4Mbits of metal programmable ROM is provided for system firmware implementation.
6.5.6
USB (BC313143A only)
This is a full speed Universal Serial Bus (USB) interface for communicating with other compatible digital devices. BlueCore3-ROM CSP acts as a USB peripheral, responding to requests from a master host controller such as a PC.
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Description of Functional Blocks
6.5.7
Synchronous Serial Interface
This is a synchronous serial port interface (SPI) for interfacing with other digital devices. The SPI port can be used for system debugging.
6.5.8
UART (BC313141A only)
This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other serial devices.
6.5.9
Audio PCM Interface
_aiEceEPJolj=pm Product Data Sheet
The Audio Pulse Code Modulation (PCM) Interface supports continuous transmission and reception of PCM encoded audio data over Bluetooth.
6.6
Microcontroller
The microcontroller, interrupt controller and event timer run the Bluetooth software stack and control the radio and host interfaces. A 16-bit Reduced Instruction Set Computer (RISC) microcontroller is used for low power consumption and efficient use of memory.
6.6.1
Programmable I/O
BlueCore3-ROM CSP has a total of 10 (8 digital and 2 analogue) programmable I/O terminals. These are controlled by firmware running on the device.
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CSR Bluetooth Software Stacks
7
CSR Bluetooth Software Stacks
BlueCore3-ROM CSP is supplied with Bluetooth v1.2 compliant stack firmware which runs on the internal RISC microcontroller. The BlueCore3-ROM CSP software architecture allows Bluetooth processing and the application program to be shared in different ways between the internal RISC microcontroller and an external host processor (if any). The upper layers of the Bluetooth stack (above HCI) can be run either on-chip or on the host processor.
7.1
BlueCore HCI Stack
Internal ROM HCI LM LC
_aiEceEPJolj=pm Product Data Sheet
32KB RAM
Baseband MCU
USB Host UART Host I/O Radio
PCM I/O
Figure 7.1: BlueCore HCI Stack In this implementation the internal processor runs the Bluetooth stack up to the Host Controller Interface (HCI). The Host processor must provide all upper layers including the applications.
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CSR Bluetooth Software Stacks
7.1.1
Key Features of the HCI Stack - Standard Bluetooth Functionality
New Bluetooth v1.2 Mandatory Functionality Adaptive Frequency Hopping (AFH) Faster Connections Flow and Flush Timeout LMP Improvements Parameter Ranges Optional v1.2 functionality supported Extended SCO (eSCO), eV3 +CRC, eV4, eV5 Scatter mode LMP Absence Masks ,Quality of service and SCO handle L2CAP flow and error control Synchronisation Standard Bluetooth Functionality The firmware has been written against the Bluetooth Core Specification v1.2. Bluetooth components: Baseband (including LC) LM HCI Standard USB v2.0 and UART (H5) HCI Transport Layers All standard radio packet types Full Bluetooth data rate, up to 723.2kbps asymmetric(1) Operation with up to seven active slaves (1) Maximum number of simultaneous active ACL connections: 7(2) Maximum number of simultaneous active SCO connections: 3(2) Operation with up to three SCO links, routed to one or more slaves Scatternet 2.5 operation All standard SCO voice coding, plus "transparent SCO" Standard operating modes: page, inquiry, page-scan and inquiry-scan All standard pairing, authentication, link key and encryption operations Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including "Forced Hold" Dynamic control of peers' transmit power via LMP Master/slave switch Broadcast Channel quality driven data rate All standard Bluetooth Test Modes
Notes:
(1) (2)
_aiEceEPJolj=pm Product Data Sheet
Maximum allowed by Bluetooth specification v1.2 Supports all combinations of active ACL and SCO channels, per Bluetooth specification v1.2
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CSR Bluetooth Software Stacks
The firmware's supported Bluetooth features are detailed in the standard Protocol Implementation Conformance Statement (PICS) documents, available from www.csr.com.
7.1.2
Key Features of the HCI Stack - Extra Functionality
The firmware extends the standard Bluetooth functionality with the following features: Supports BlueCore Serial Protocol (BCSP) - a proprietary, reliable alternative to the standard Bluetooth UART Host Transport. Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set, called BCCMD (BlueCore Command), provides:
_aiEceEPJolj=pm Product Data Sheet
Access to the chip's general-purpose PIO port The negotiated effective encryption key length on established Bluetooth links Access to the firmware's random number generator Controls to set the default and maximum transmit powers. These can help minimise interference between overlapping, fixed-location piconet Dynamic UART configuration Radio transmitter enable/disable (a simple command connects to a dedicated hardware switch that determines whether the radio can transmit) The firmware can read the voltage on a pair of the chip's external pins. This is normally used to build a battery monitor, using either VM or host code. A block of BCCMD commands provides access to the chip's "persistent store" configuration database (PS). The database sets the device's Bluetooth address, Class of Device, radio (transmit class) configuration, SCO routing, LM, USB and DFU constants, etc. A UART break condition can be used in three ways: 1.1. Presenting a UART break condition to the chip can force the chip to perform a hardware reboot 1.2. Presenting a break condition at boot time can hold the chip in a low power state, preventing normal initialisation while the condition exists 1.3. With H5, the firmware can be configured to send a break to the host before sending data (normally used to wake the host from a Deep Sleep state) A block of "radio test" or BIST commands allows direct control of the chip's radio. This aids the development of modules' radio designs, and can be used to support Bluetooth qualification. Virtual Machine (VM). The firmware provides the VM environment in which to run application-specific code. Although the VM is mainly used with BlueLab and "RFCOMM builds" (alternative firmware builds providing L2CAP, SDP and RFCOMM), the VM can be used with this build to perform simple tasks such as flashing LEDs via the chip's PIO port. Hardware low power modes: shallow sleep and deep sleep. The chip drops into modes that significantly reduce power consumption when the software goes idle. SCO channels are normally routed over HCI over BCSP, H5 or USB. However, up to three SCO channels can be routed over the chip's single PCM port at the same time as routing any other SCO channels over HCI. Co-operative existence with 802.11b chipsets Always refer to the Firmware Release Note for the specific functionality of a particular build.
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CSR Bluetooth Software Stacks
7.2
BlueCore RFCOMM Stack
RFCOMM Internal ROM L2CAP HCI LM LC SDP
_aiEceEPJolj=pm Product Data Sheet
32KB RAM
Baseband MCU
USB Host UART Host I/O Radio
PCM I/O
Figure 7.2: BlueCore RFCOMM Stack In this version of the firmware the upper layers of the Bluetooth stack up to RFCOMM are run on-chip. This reduces host-side software and hardware requirements at the expense of some of the power and flexibility of the HCI only stack.
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CSR Bluetooth Software Stacks
7.2.1
Key Features of the BlueCore3-ROM CSP RFCOMM Stack
Interfaces to Host RFCOMM, an RS-232 serial cable emulation protocol SDP, a service database look-up protocol Connectivity Maximum number of active slaves: 3 Maximum number of simultaneous active ACL connections: 3 Maximum number of simultaneous active SCO connections: 3 Data Rate: up to 350Kb/s Security Full support for all Bluetooth security features up to and including strong (128-bit) encryption. Power Saving Full support for all Bluetooth power saving modes (Park, Sniff and Hold). Data Integrity CQDDR increases the effective data rate in noisy environments. RSSI used to minimise interference to other radio devices using the ISM band.
_aiEceEPJolj=pm Product Data Sheet
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CSR Bluetooth Software Stacks
7.3
BCHS Software
BlueCore Embedded Host Software is designed to enable CSR customers to implement Bluetooth functionality into embedded products quickly, cheaply and with low risk. BCHS is developed to work with CSR's family of BlueCore IC's. BCHS is intended for embedded products that have a host processor for running BCHS and the Bluetooth application e.g. a mobile phone or a PDA. BCHS together with the BlueCore IC with embedded Bluetooth core stack (L2CAP, RFCOMM and SDP) is a complete Bluetooth system solution from RF to profiles. BCHS includes most of the Bluetooth intelligence and gives the user a simple API. This makes it possible to develop a Bluetooth product without in-depth Bluetooth knowledge. The BlueCore Embedded Host Software contains three elements: Example Drivers (BCSP and proxies) Bluetooth Profile Managers Example Applications The profiles are qualified which makes the qualification of the final product very easy. BCHS is delivered with source code (ANSI C). With BCHS also come example applications in ANSI C, which makes the process of writing the application easier.
_aiEceEPJolj=pm Product Data Sheet
7.4
Additional Software for Other Embedded Applications
When the upper layers of the Bluetooth protocol stack are run as firmware on BlueCore3-ROM CSP, a UART software driver is supplied that presents the L2CAP, RFCOMM and Service Discovery (SDP) APIs to higher Bluetooth stack layers running on the host. The code is provided as `C' source or object code.
7.5
CSR Development Systems
CSR's BlueLab and Casira development kits are available to allow the evaluation of the BlueCore3 hardware and software, and as toolkits for developing on-chip and host software.
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Device Terminal Descriptions
8
8.1
Device Terminal Descriptions
RF Ports
The BlueCore3-ROM CSP has common differential RF input and output ports as shown in Figure 8.1, the internal common connections between the transmitter and receiver are described in Section 8.1.1 and shown in. The operational mode is determined by setting the PS Key PSKEY_TXRX_PIO_CONTROL (0x209).
BlueCore3-ROM CSP
_aiEceEPJolj=pm Product Data Sheet
From RF Transmitter To RF Receiver
TX_A RF Switch 1.8pF Balun
From RF Transmitter To RF Receiver
TX_B RF Switch 1.8pF
Figure 8.1: Common Differential RF Input and Output Ports (Class 2)
8.1.1
TX_A and TX_B
TX_A and TX_B are balanced RF ports which are used for both transmitting and receiving. Selection of transmit or receive mode is under software control. The TX measurements in the following section refer to the device being put into transmit modes and the RX measurements refer to the device being put into receive modes.
BlueCore3-ROM CSP
RF Switch
TX_A
Transmitter
_RADIO VSS
RF Switch
_B TX
Receiver
Figure 8.2: RF Input/Output Diagram Production Information (c) Cambridge Silicon Radio Limited 2005-2006
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Device Terminal Descriptions
8.1.2
Transmitter S-Parameters
Port 1: TX_A Port 2: TX_B Temperature: +20C Power Level: 63 GHZ S MP R 50
_aiEceEPJolj=pm Product Data Sheet
Freq (MHz)
S11 Mag. Ang. Mag.
S21 Ang. Mag.
S12 Ang. Mag.
S22 Ang.
2.4 2.41 2.42 2.43 2.44 2.45 2.46 2.47 2.48 2.49 2.5
0.778992 0.778216 0.77645 0.774543 0.774082 0.772337 0.776561 0.773134 0.787564 0.770775 0.771305
-110.502 -110.488 -110.507 -110.59 -110.644 -110.798 -110.974 -110.998 -110.922 -111.086 -111.27
0.089221 0.08835 0.087776 0.086733 0.085721 0.08466 0.085574 0.085125 0.101769 0.085522 0.084643
53.090667 53.138275 53.082489 53.190804 52.978288 53.826097 55.47352 53.860453 56.756751 54.24436 54.319244
0.095407 0.096211 0.097171 0.098066 0.097855 0.099093 0.096084 0.10329 0.081487 0.103871 0.102864
76.015437 74.898228 73.823056 72.806983 71.945326 71.402956 68.284531 70.063979 69.515479 66.737566 65.651072
0.765223 0.765626 0.765605 0.765635 0.76746 0.770942 0.775047 0.772324 0.749537 0.771541 0.772812
-111.621238 -111.955226 -112.259735 -112.625792 -113.100529 -113.31683 -113.456241 -113.702371 -114.239531 -114.281514 -114.523037
Table 8.1: Transmit Mode S-Parameters
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Device Terminal Descriptions
8.1.3
Transmit Port Impedances
_aiEceEPJolj=pm Product Data Sheet
Figure 8.3: TX_A Output at Power Setting 35
Figure 8.4: TX_A Output at Power Setting 50 Production Information (c) Cambridge Silicon Radio Limited 2005-2006
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Device Terminal Descriptions
_aiEceEPJolj=pm Product Data Sheet
Figure 8.5: TX_A Output at Power Setting 63
Figure 8.6: TX_B Output at Power Setting 35
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_aiEceEPJolj=pm Product Data Sheet
Figure 8.7: TX_B Output at Power Setting 50
Figure 8.8: TX_B Output at Power Setting 63
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Device Terminal Descriptions
8.1.4
Receiver S-Parameters
Port 1: TX_A Port 2: TX_B Temperature: +20C GHZ S MP R 50
Freq (MHz) S11 Mag. Ang. Mag. S21 Ang. Mag. S12 Ang. Mag. S22 Ang.
_aiEceEPJolj=pm Product Data Sheet
2.4 2.41 2.42 2.43 2.44 2.45 2.46 2.47 2.48 2.49 2.5
0.731957 0.728306 0.722299 0.714729 0.711343 0.704912 0.70591 0.700536 0.708689 0.689339 0.686515
-83.6007 -84.3174 -85.0836 -86.0815 -87.0754 -88.0926 -89.2094 -90.2489 -91.3032 -92.4534 -93.7781
0.098114 0.097465 0.096811 0.095667 0.094944 0.094097 0.094708 0.094607 0.106625 0.093223 0.092186
59.46505 59.09911 58.55238 58.12089 57.52449 57.71248 58.64331 57.00482 59.86385 56.44381 56.24232
0.130935 0.132772 0.13363 0.134139 0.134045 0.136614 0.136792 0.14231 0.126132 0.143789 0.143386
74.86366 72.84295 71.09473 69.54935 68.11455 66.62563 63.42167 63.94967 60.06994 60.1473 58.2896
0.651799 0.646684 0.641781 0.636354 0.63506 0.634593 0.633279 0.626289 0.604609 0.619555 0.619004
-88.5651 -89.7553 -90.827 -92.0823 -93.5674 -94.7098 -95.8576 -97.0576 -98.3874 -99.3865 -100.649
Table 8.2: Receive Mode S-Parameters
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Device Terminal Descriptions
8.1.5
Receive Port Impedances
_aiEceEPJolj=pm Product Data Sheet
Figure 8.9: RX_A Balanced Receive Input Impedance
Figure 8.10: RX_B Balanced Receive Input Impedance
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Device Terminal Descriptions
8.2
External Reference Clock Input (XTAL_IN)
The BlueCore3-ROM CSP RF local oscillator and internal digital clocks are derived from the reference clock at the BlueCore3-ROM CSP XTAL_IN input. This reference may be either an external clock or from a crystal connected between XTAL_IN and XTAL_OUT. The crystal mode is described in Section 8.3.
8.2.1
External Mode
BlueCore3-ROM CSP can be configured to accept an external reference clock (from another device, such as TCXO) at XTAL_IN by connecting XTAL_OUT to ground. The external clock can either be a digital level square wave or sinusoidal and this may be directly coupled to XTAL_IN without the need for additional components. If the peaks of the reference clock are below VSS_ANA or above VDD_ANA, it must be driven through a DC blocking capacitor (~33pF) connected to XTAL_IN. A digital level reference clock gives superior noise immunity as the high slew rate clock edges have lower voltage to phase conversion. The external clock signal should meet the specifications in Table 8.3:
Min Typ Max
_aiEceEPJolj=pm Product Data Sheet
Frequency Duty cycle
(1)
7.5MHz 20:80 400mV pk-pk
16MHz 50:50 -
40MHz 80:20 15ps rms VDD_ANA(2)(3)
Edge Jitter (At Zero Crossing) Signal Level
Table 8.3: External Clock Specifications
Notes:
(1) (2) (3)
The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies VDD_ANA is 1.8V nominal If the external clock is driven through a DC blocking capacitor then maximum allowable amplitude is reduced from VDD_ANA to 800mV pk-pk
8.2.2
XTAL_IN Impedance in External Mode
The impedance of the XTAL_IN will not change significantly between operating modes, typically 10fF. When transitioning from deep sleep to an active state a spike of up to 1pC may be measured. For this reason it is recommended that a buffered clock input be used.
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Device Terminal Descriptions
8.2.3
Clock Timing Accuracy
As Figure 8.11 indicates, the 250ppm timing accuracy on the external clock is required 7ms after the assertion of the system clock request line. This is to guarantee that the firmware can maintain timing accuracy in accordance with the Bluetooth v1.2 specification. Radio activity may occur after 11ms, therefore at this point, the timing accuracy of the external clock source must be within 20ppm.
_aiEceEPJolj=pm Product Data Sheet
Figure 8.11: TCXO Clock Accuracy
8.2.4
Clock Start-Up Delay
BlueCore3-ROM CSP hardware incorporates an automatic 5ms delay after the assertion of the system clock request signal before running firmware. This is suitable for most applications using an external clock source. However, there may be scenarios where the clock cannot be guaranteed to either exist or be stable after this period. Under these conditions, BlueCore3-ROM CSP firmware provides a software function which will extend the system clock request signal by a period stored in PSKEY_CLOCK_STARTUP_DELAY. This value is set in milliseconds from 5-31ms. This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still keeping the current consumption of BlueCore3-ROM CSP as low as possible. BlueCore3-ROM CSP will consume about 2mA of current for the duration of PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.
Actual Allowable Clock Presence Delay on XTAL_IN vs. PSKey Setting
30.0
25.0
20.0
D elay (m s)
15.0
10.0
5.0
0.0 0.0 5.0 10.0 15.0 PSKEY_CLOCK_STARTUP_DELAY 20.0 25.0 30.0
Figure 8.12: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting
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Device Terminal Descriptions
8.2.5
Input Frequencies and PS Key Settings
BlueCore3-ROM CSP should be configured to operate with the chosen reference frequency. This is accomplished by setting the PS Key PSKEY_ANA_FREQ (0x1fe) for all frequencies with an integer multiple of 250KHz. The input frequency default setting in BlueCore3-ROM CSP is 26MHz. The following CDMA/3G TCXO frequencies are also catered for: 7.68, 14.4, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz.
Reference Crystal Frequency (MHz) PSKEY_ANA_FREQ (0x1fe) (Units of 1kHz)
_aiEceEPJolj=pm Product Data Sheet
7.68 14.40 15.36 16.20 16.80 19.20 19.44 19.68 19.80 38.40 n x 250kHz +26.00 Default
7680 14400 15360 16200 16800 19200 19440 19680 19800 38400 26000
Table 8.4: PS Key Values for CDMA/3G phone TCXO Frequencies
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Device Terminal Descriptions
8.3
Crystal Oscillator (XTAL_IN, XTAL_OUT)
The BlueCore3-ROM CSP RF local oscillator and internal digital clocks are derived from the reference clock at the BlueCore3-ROM CSP XTAL_IN input. This reference may be either an external clock or from a crystal connected between XTAL_IN and XTAL_OUT. The external reference clock mode is described in Section 8.1.
8.3.1
XTAL Mode
BlueCore3-ROM CSP contains a crystal driver circuit. This operates with an external crystal and capacitors to form a Pierce oscillator.
_aiEceEPJolj=pm Product Data Sheet
gm BlueCore3-ROM CSP
-
Ctrim
Cint
Ctrim
Ct2
Ct1
Figure 8.13: Crystal Driver Circuit
Figure 8.14 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant frequency. It forms a resonant circuit with its load capacitors.
Cm Lm Rm
Co
Figure 8.14: Crystal Equivalent Circuit
The resonant frequency may be trimmed with the crystal load capacitance. BlueCore3-ROM CSP contains variable internal capacitors to provide a fine trim. The BlueCore3-ROM CSP driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a current at XTAL_OUT. The value of transconductance is variable and may be set for optimum performance.
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XTAL_OUT
XTAL_IN
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Device Terminal Descriptions
8.3.2
Load Capacitance
For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is defined for the crystal. This is the total capacitance across the crystal viewed from its terminals. BlueCore3-ROM CSP provides some of this load with the capacitors Ctrim and Cint. The remainder should be from the external capacitors labelled Ct1 and Ct2. Ct1 should be three times the value of Ct2 for best noise performance. This maximises the signal swing, hence slew rate at XTAL_IN, to which all on chip clocks are referred. Crystal load capacitance, Cl is calculated with the following equation: Cl = Cint + C trim C C + t1 t 2 2 C t1 + C t 2
_aiEceEPJolj=pm Product Data Sheet
Equation 8.1: Load Capacitance
Where:
Ctrim = 3.4pF nominal (Mid range setting) Cint = 1.5pF
Note:
Cint does not include the crystal internal self capacitance, it is the driver self capacitance
8.3.3
Frequency Trim
BlueCore3-ROM CSP enables frequency adjustments to be made. This feature is typically used to remove initial tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the crystal load capacitance with on chip trim capacitors, Ctrim. The value of Ctrim is set by a 6-bit word in the Persistent Store Key PSKEY_ANA_FTRIM (0x1f6). Its value is calculated thus: Ctrim = 110 fF x PSKEY_ANA_FTRIM
Equation 8.2: Trim Capacitance
There are two Ctrim capacitors, which are both connected to ground. When viewed from the crystal terminals, they appear in series so each least significant bit (LSB) increment of frequency trim presents a load across the crystal of 55fF. The frequency trim is described by Equation 8.3:
(Fx ) = pullability x 55 x 10 -3 (ppm / LSB ) Fx Equation 8.3: Frequency Trim
Where Fx is the crystal frequency and pullability is a crystal parameter with units of ppm/pF. Total trim range is 63 times the value above. If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 8.4:
Cm (Fx ) = Fx (C) 4(Cl + C0 )2
Equation 8.4: Pullability
Where:
C0 = Crystal self capacitance (shunt capacitance) Cm = Crystal motional capacitance (series branch capacitance in crystal model). See Figure 8.14.
Note:
It is a Bluetooth requirement that the frequency is always within 20ppm. The trim range should be sufficient to pull the crystal within 5ppm of the exact frequency. This leaves a margin of 15ppm for frequency drift with ageing and temperature. A crystal with an ageing and temperature drift specification of better than 15ppm is required.
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Device Terminal Descriptions
8.3.4
Transconductance Driver Model
The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to one terminal generates a voltage at the other. The transconductance amplifier in BlueCore3-ROM CSP uses the voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the circuit will oscillate if the transconductance, transimpedance product is greater than unity. For sufficient oscillation amplitude, the product should be greater than 3. The transconductance required for oscillation is defined by the following relationship:
gm >
(2Fx ) Rm ((C0 + Cint )(Ct1 + Ct 2 + 2Ctrim ) + (Ct1 + Ctrim )(Ct 2 + Ctrim ))2
2
3(Ct1 +Ctrim )(Ct 2 + Ctrim )
_aiEceEPJolj=pm Product Data Sheet
Equation 8.5: Transconductance Required for Oscillation
BlueCore3-ROM CSP guarantees a transconductance value of at least 2mA/V at maximum drive level.
Notes:
More drive strength is required for higher frequency crystals, higher loss crystals (larger Rm) or higher capacitance loading. Optimum drive level is attained when the level at XTAL_IN is approximately 1V pkpk. The drive level is determined by the crystal driver transconductance, by setting the Persistent Store KEY_XTAL_LVL (0x241).
8.3.5
Negative Resistance Model
An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element. The driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of the negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the BlueCore3-ROM CSP crystal driver circuit is based on a transimpedance amplifier, an equivalent negative resistance may be calculated for it with the following formula in Equation 8.6:
Rneg > gm (2Fx ) (C0 + Cint )((Ct1 + Ct 2 + 2Ctrim ) + (Ct1 + Ctrim )(Ct 2 + Ctrim ))2
2
3(Ct1 +Ctrim )(Ct 2 + Ctrim )
Equation 8.6: Equivalent Negative Resistance
This formula shows the negative resistance of the BlueCore3-ROM CSP driver as a function of its drive strength. The value of the driver negative resistance may be easily measured by placing an additional resistance in series with the crystal. The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of the oscillator.
Min Typ Max
Frequency Initial Tolerance Pullability
8MHz -
16MHz 25ppm 20ppm/pF
40MHz -
Table 8.5: Crystal Oscillator Specification
8.3.6
Crystal PS Key Settings
See tables in Section 8.2.5.
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Device Terminal Descriptions
8.3.7
Crystal Oscillator Characteristics
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
1000.0
_aiEceEPJolj=pm Product Data Sheet
Max Xtal Rm Value (ESR), (Ohm)
100.0
10.0 2.5 3.5 4.5 5.5 6.5 7.5 Load Capacitance (pF) 8.5 9.5 10.5 11.5 12.5
8 MHz 20 MHz 32 MHz
12 MHz 24 MHz
16 MHz 28 MHz
Figure 8.15: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
Note:
Graph shows results for BlueCore3-ROM CSP crystal driver at maximum drive level.
Conditions:
Ctrim = 3.4pF centre value Crystal Co = 2pF Transconductance setting = 2mA/V Loop gain = 3 Ct1/Ct2 = 3
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BlueCore3-ROM XTAL Driver Characteristics
0.007
0.006
0.005 Transconductance (S)
0.004
_aiEceEPJolj=pm Product Data Sheet
0.003
0.002
0.001
0.000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PSKEY_XTAL_LVL
Gm Typical Gm Minimum Gm Maximum
Figure 8.16: Crystal Driver Transconductance vs. Driver Level Register Setting
Note:
Drive level is set by Persistent Store Key PSKEY_XTAL_LVL (0x241).
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Device Terminal Descriptions
Negative Resistance for 16 MHz Xtal
10000
Max -ve Resistance ()
1000
_aiEceEPJolj=pm Product Data Sheet
100
10 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 Drive Level Setting
Typical Minimum Maximum
Figure 8.17: Crystal Driver Negative Resistance as a Function of Drive Level Setting
Crystal parameters:
Crystal frequency 16MHz (Please refer to your software build release note for frequencies supported); Crystal C0 = 0.75pF
Circuit parameters:
Ctrim = 8pF, maximum value Ct1,Ct2 = 5pF (3.9pF plus 1.1 pF stray) (Crystal total load capacitance 8.5pF)
Note:
This is for a specific crystal and load capacitance.
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Device Terminal Descriptions
8.4
UART Interface (BC313141A only)
BlueCore3-ROM CSP Universal Asynchronous Receiver Transmitter (UART) interface provides a simple mechanism for communicating with other serial devices using the RS232 standard (1).
BlueCore3-ROM CSP
UART_TX UART_RX UART_RTS UART_CTS
_aiEceEPJolj=pm Product Data Sheet
Figure 8.18: Universal Asynchronous Receiver
Four signals are used to implement the UART function, as shown in Figure 8.18. When BlueCore3-ROM CSP is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control where both are active low indicators. All UART connections are implemented using CMOS technology and have signalling levels of 0V and VDD_PADS. UART configuration parameters, such as Baud rate and packet format, are set using BlueCore3-ROM CSP software.
Notes:
In order to communicate with the UART at its maximum data rate using a standard PC, an accelerated serial port adapter card is required for the PC.
(1)
Uses RS232 protocol but voltage levels are 0V to VDD_USB, (requires external RS232 transceiver chip)
Parameter Possible Values
Baud Rate Flow Control Parity
Minimum Maximum
1200 Baud (2%Error) 9600 Baud (1%Error) 1.5MBaud (1%Error) RTS/CTS or None None, Odd or Even 1 or 2 8
Number of Stop Bits Bits per channel
Table 8.6: Possible UART Settings
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Device Terminal Descriptions
The UART interface is capable of resetting BlueCore3-ROM CSP upon reception of a break signal. A Break is identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 8.19. If tBRK is longer than the value, defined by the PS Key PSKEY_HOST_IO_UART_RESET_TIMEOUT, (0x1a4), a reset will occur. This feature allows a host to initialise the system to a known state. BlueCore3-ROM CSP can also emit a Break character that may be used to wake the Host.
t UART RX
BRK
Figure 8.19: Break Signal
_aiEceEPJolj=pm Product Data Sheet
Note:
The DFU boot loader must be loaded into the Flash device before the UART or USB interfaces can be used. This initial flash programming can be done via the SPI. Table 8.7 shows a list of commonly used Baud rates and their associated values for the Persistent Store Key PSKEY_UART_BAUD_RATE (0x204). There is no requirement to use these standard values. Any Baud rate within the supported range can be set in the Persistent Store Key according to the formula in Equation 8.7.
Baud Rate = PSKEY_UART _BAUD_RATE 0.004096
Equation 8.7: Baud Rate
Persistent Store Value Baud Rate Hex Dec Error
1200 2400 4800 9600 19200 38400 57600 76800 115200 230400 460800 921600 1382400
0x0005 0x000a 0x0014 0x0027 0x004f 0x009d 0x00ec 0x013b 0x01d8 0x03b0 0x075f 0x0ebf 0x161e
5 10 20 39 79 157 236 315 472 944 1887 3775 5662
1.73% 1.73% 1.73% -0.82% 0.45% -0.18% 0.03% 0.14% 0.03% 0.03% -0.02% 0.00% -0.01%
Table 8.7: Standard Baud Rates
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8.4.1
UART Bypass
RESET RXD CTS RTS TXD UART_TX UART_RTS UART_CTS UART_RX PIO4 PIO5 PIO6 PIO7 TX RTS CTS RX
Host Processor
UART
Another Device
_aiEceEPJolj=pm Product Data Sheet
BlueCore3-ROM CSP
Test Interface
Figure 8.20: UART Bypass Architecture
8.4.2
UART Configuration while RESET is Active
The UART interface for BlueCore3-ROM CSP while the chip is being held in reset is tri-state. This will allow the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to this bus must tri-state when BlueCore3-ROM CSP reset is de-asserted and the firmware begins to run.
8.4.3
UART Bypass Mode
Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on BlueCore3-ROM CSP can be used. The default state of BlueCore3-ROM CSP after reset is de-asserted is for the host UART bus to be connected to the BlueCore3-ROM CSP UART, thereby allowing communication to BlueCore3-ROM CSP via the UART. In order to apply the UART bypass mode, a BCCMD command will be issued to BlueCore3-ROM CSP upon this, it will switch the bypass to PIO[7:4] as shown in Figure 8.20. Once the bypass mode has been invoked, BlueCore3-ROM CSP will enter the deep sleep state indefinitely. In order to re-establish communication with BlueCore3-ROM CSP, the chip must be reset so that the default configuration takes affect. It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is invoked. Therefore it is not possible to have active Bluetooth links while operating the bypass mode.
8.4.4
Current Consumption in UART Bypass Mode
The current consumption for a device in UART Bypass Mode is equal to the values quoted for a device in standby mode.
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8.5
USB Interface (BC313143A only)
BlueCore3-ROM CSP devices contain a full speed (12Mbits/s) USB interface that is capable of driving a USB cable directly. No external USB transceiver is required. The device operates as a USB peripheral, responding to requests from a master host controller such as a PC. Both the OHCI and the UHCI standards are supported. The set of USB endpoints implemented can behave as specified in the USB section of the Bluetooth specification v1.2 or alternatively can appear as a set of endpoints appropriate to USB audio devices such as speakers. As USB is a Master/Slave oriented system (in common with other USB peripherals), BlueCore3-ROM CSP only supports USB Slave operation.
_aiEceEPJolj=pm Product Data Sheet
8.5.1
USB Data Connections
The USB data lines emerge as pins USB_DP and USB_DN. These terminals are connected to the internal USB I/O buffers of the BlueCore3-ROM CSP and therefore have a low output impedance. To match the connection to the characteristic impedance of the USB cable, resistors must be placed in series with USB_DP / USB_DN and the cable.
8.5.2
USB Pull-Up Resistor
BlueCore3-ROM CSP features an internal USB pull-up resistor. This pulls the USB_DP pin weakly high when BlueCore3-ROM CSP is ready to enumerate. It signals to the PC that it is a full speed (12Mbit/s) USB device. The USB internal pull-up is implemented as a current source, and is compliant with Section 7.1.5 of the USB specification v1.2. The internal pull-up pulls USB_DP high to at least 2.8V when loaded with a 15k 5% pull-down resistor (in the hub/host) when VDD_PADS=3.1V. This presents a Thevenin resistance to the host of at least 900. Alternatively, an external 1.5k pull-up resistor can be placed between a PIO line and D+ on the USB cable. The firmware must be alerted to which mode is used by setting PS Key PSKEY_USB_PIO_PULLUP appropriately. The default setting uses the internal pull-up resistor.
8.5.3
Power Supply
The USB specification dictates that the minimum output high voltage for USB data lines is 2.8V. To safely meet the USB specification, the voltage on the VDD_USB supply terminals must be an absolute minimum of 3.1V. CSR recommends 3.3V for optimal USB signal quality.
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8.5.4
Self Powered Mode
In self powered mode, the circuit is powered from its own power supply and not from the VBUS (5V) line of the USB cable. It draws only a small leakage current (below 0.5mA) from VBUS on the USB cable. This is the easier mode for which to design for, as the design is not limited by the power that can be drawn from the USB hub or root port. However, it requires that VBUS be connected to BlueCore3-ROM CSP via a resistor network (Rvb1 and Rvb2), so BlueCore3-ROM CSP can detect when VBUS is powered up. BlueCore3-ROM CSP will not pull USB_DP high when VBUS is off. Self powered USB designs (powered from a battery or PSU) must ensure that a PIO line is allocated for USB pull-up purposes. A 1.5K 5% pull-up resistor between USB_DP and the selected PIO line should be fitted to the design. Failure to fit this resistor may result in the design failing to be USB compliant in self powered mode. The internal pull-up in BlueCore is only suitable for bus powered USB devices i.e. dongles.
_aiEceEPJolj=pm Product Data Sheet
BlueCore3-ROM CSP
PIO USB_DP
1.5K 5% Rs D+ Rs DRvb1 VBUS Rvb2
USB_DN USB_ON
GND
Figure 8.21: USB Connections for Self Powered Mode
The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting PSKEY_USB_PIO_VBUS to the corresponding pin number.
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8.5.5
Bus Powered Mode
In bus powered mode the application circuit draws its current from the 5V VBUS supply on the USB cable. BlueCore3-ROM CSP negotiates with the PC during the USB enumeration stage about how much current it is allowed to consume. For Class 2 Bluetooth applications, CSR recommends that the regulator used to derive 3.3V from VBUS is rated at 100mA average current and should be able to handle peaks of 120mA without foldback or limiting. In bus powered mode, BlueCore3-ROM CSP requests 100mA during enumeration. When selecting a regulator, be aware that VBUS may go as low as 4.4V. The inrush current (when charging reservoir and supply decoupling capacitors) is limited by the USB specification (see USB specification v1.1, Section 7.2.4.1). Some applications may require soft start circuitry to limit inrush current if more than 10F is present between VBUS and GND. The 5V VBUS line emerging from a PC is often electrically noisy. As well as regulation down to 3.3V and 1.8V, applications should include careful filtering of the 5V line to attenuate noise that is above the voltage regulator bandwidth. Excessive noise on the 1.8V supply to the analogue supply pins of BlueCore3-ROM CSP will result in reduced receive sensitivity and a distorted RF transmit signal.
BlueCore3-ROM CSP Rs USB_DP Rs USB_DN Rvb1 USB_ON VBUS DD+
_aiEceEPJolj=pm Product Data Sheet
GND
Voltage Regulator
Figure 8.22: USB Connections for Bus Powered Mode
Note:
USB_ON is shared with BlueCore3-ROM CSP PIO terminals
Identifier Value Function
Rs Rvb1 Rvb2
27 nominal 22k 5% 47k 5%
Impedance matching to USB cable VBUS ON sense divider VBUS ON sense divider
Table 8.8: USB Interface Component Values
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8.5.6
Suspend Current
All USB devices must permit the USB controller to place them in a USB Suspend mode. While in USB Suspend, bus powered devices must not draw more than 0.5mA from USB VBUS (self powered devices may draw more than 0.5mA from their own supply). This current draw requirement prevents operation of the radio by bus powered devices during USB Suspend. The voltage regulator circuit itself should draw only a small quiescent current (typically less than 100A) to ensure adherence to the suspend current requirement of the USB specification. This is not normally a problem with modern regulators. Ensure that external LEDs and/or amplifiers can be turned off by BlueCore3-ROM CSP. The entire circuit must be able to enter the suspend mode. (For more details on USB Suspend, see separate CSR documentation).
_aiEceEPJolj=pm Product Data Sheet
8.5.7
Detach and Wake_Up Signalling
BlueCore3-ROM CSP can provide out-of-band signalling to a host controller by using the control lines called `USB_DETACH' and `USB_WAKE_UP'. These are outside the USB specification (no wires exist for them inside the USB cable), but can be useful when embedding BlueCore3-ROM CSP into a circuit where no external USB is visible to the user. Both control lines are shared with PIO pins and can be assigned to any PIO pin by setting the PS Keys PSKEY_USB_PIO_DETACH and PSKEY_USB_PIO_WAKEUP to the selected PIO number. USB_DETACH is an input which, when asserted high, causes BlueCore3-ROM CSP to put USB_DN and USB_DP in a high impedance state and turned off the pull-up resistor on DP. This detaches the device from the bus and is logically equivalent to unplugging the device. When USB_DETACH is taken low, BlueCore3-ROM CSP will connect back to USB and await enumeration by the USB host. USB_WAKE_UP is an active high output (used only when USB_DETACH is active) to wake up the host and allow USB communication to recommence. It replaces the function of the software USB WAKE_UP message (which runs over the USB cable), and cannot be sent while BlueCore3-ROM CSP is effectively disconnected from the bus.
10ms max 10ms max
USB_DETACH 10ms max No max
USB_WAKE_UP
Port_Impedance USB_DP USB_DN USB_PULL_UP Disconnected
Figure 8.23: USB_DETACH and USB_WAKE_UP Signal
8.5.8
USB Driver
A USB Bluetooth device driver is required to provide a software interface between BlueCore3-ROM CSP and Bluetooth software running on the host computer. Suitable drivers are available from www.csrsupport.com.
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8.5.9
USB 1.1 Compliance
BlueCore3-ROM CSP is qualified to the USB specification v1.1, details of which are available from http://www.usb.org. The specification contains valuable information on aspects such as PCB track impedance, supply inrush current and product labelling. Although BlueCore3-ROM CSP meets the USB specification, CSR cannot guarantee that an application circuit designed around the chip is USB compliant. The choice of application circuit, component choice and PCB layout all affect USB signal quality and electrical characteristics. The information in this document is intended as a guide and should be read in association with the USB specification, with particular attention being given to Chapter 7. Independent USB qualification must be sought before an application is deemed USB compliant and can bear the USB logo. Such qualification can be obtained from a USB plugfest or from an independent USB test house. Terminals USB_DP and USB_DN adhere to the USB specification 2.0 (Chapter 7) electrical requirements.
_aiEceEPJolj=pm Product Data Sheet
8.5.10 USB 2.0 Compatibility
BlueCore3-ROM CSP is compatible with USB v2.0 host controllers; under these circumstances the two ends agree the mutually acceptable rate of 12Mbits/s according to the USB v2.0 specification.
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8.6
Serial Peripheral Interface
BlueCore3-ROM CSP uses 16-bit data and 16-bit address serial peripheral interface, where transactions may occur when the internal processor is running or is stopped. This section details the considerations required when interfacing to BlueCore3-ROM CSP via the four dedicated serial peripheral interface terminals. Data may be written or read one word at a time or the auto increment feature may be used to access blocks.
8.6.1
Instruction Cycle
The BlueCore3-ROM CSP is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. The instruction cycle for a SPI transaction is shown in Table 8.9. 1 2 3 4 5 Reset the SPI interface Write the command word Write the address Write or read data words Termination Hold SPI_CSB high for two SPI_CLK cycles Take SPI_CSB low and clock in the 8 bit command Clock in the 16-bit address word Clock in or out 16-bit data word(s) Take SPI_CSB high
Table 8.9: Instruction Cycle for an SPI Transaction
_aiEceEPJolj=pm Product Data Sheet
With the exception of reset, SPI_CSB must be held low during the transaction. Data on SPI_MOSI is clocked into the BlueCore3-ROM CSP on the rising edge of the clock line SPI_CLK. When reading, BlueCore3-ROM CSP will reply to the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides the clock on SPI_CLK. The transaction is terminated by taking SPI_CSB high. Sending a command word and the address of a register for every time it is to be read or written is a significant overhead, especially when large amounts of data are to be transferred. To overcome this BlueCore3-ROM CSP offers increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CSB is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or read.
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8.6.2
Writing to BlueCore3-ROM CSP
To write to BlueCore3-ROM CSP, the 8-bit write command (00000010) is sent first (C[7:0]) followed by a 16-bit address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the location set by the address (A). Thereafter for each subsequent 16-bits clocked in, the address (A) is incremented and the data written to consecutive locations until the transaction terminates when SPI_CSB is taken high.
Reset Write_Command SPI_CSB Address(A) Data(A) Data(A+1) etc
End of Cycle
_aiEceEPJolj=pm Product Data Sheet
SPI_CLK
SPI_MOSI
C7
C6
C1
C0
A15
A14
A1
A0
D15
D14
D1
D0
D15
D14
D1
D0
D15
D14
D1
D0
Don't Care
SPI_MISO
Processor State
MISO Not Defined During Write
Processor State
Figure 8.24: Write Operation
8.6.3
Reading from BlueCore3-ROM CSP
Reading from BlueCore3-ROM CSP is similar to writing to it. An 8-bit read command (00000011) is sent first (C[7:0]), followed by the address of the location to be read (A[15:0]). BlueCore3-ROM CSP then outputs on SPI_MISO a check word during T[15:0] followed by the 16-bit contents of the addressed location during bits D[15:0]. The check word is composed of {command, address [15:8]}. The check word may be used to confirm a read operation to a memory location. This overcomes the problems encountered with typical serial peripheral interface slaves, whereby it is impossible to determine whether the data returned by a read operation is valid data or the result of the slave device not responding. If SPI_CSB is kept low, data from consecutive locations is read out on SPI_MISO for each subsequent 16 clocks, until the transaction terminates when SPI_CSB is taken high.
Reset Read_Command SPI_CSB Address(A) Check_Word Data(A) Data(A+1) etc End of Cycle
SPI_CLK
SPI_MOSI
C7
C6
C1
C0 A15 A14
A1
A0
Don't Care
SPI_MISO
Processor State
MISO Not Defined During Address
T15 T14
T1
T0
D15 D14
D1
D0 D15 D14
D1
D0
D15 D14
D1
D0
Processor State
Figure 8.25: Read Operation
8.6.4
Multi Slave Operation
BlueCore3-ROM CSP should not be connected in a multi slave arrangement by simple parallel connection of slave MISO lines. When BlueCore3-ROM CSP is deselected (SPI_CSB = 1), the SPI_MISO line does not float, instead, BlueCore3-ROM CSP outputs 0 if the processor is running or 1 if it is stopped.
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8.7
PCM CODEC Interface
Pulse Code Modulation (PCM) is a standard method used to digitise human voice patterns for transmission over digital communication channels. Through its PCM interface, BlueCore3-ROM CSP has hardware support for continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset applications. BlueCore3-ROM CSP offers a bi directional digital audio interface that routes directly into the baseband layer of the on chip firmware. It does not pass through the HCI protocol layer. Hardware on BlueCore3-ROM CSP allows the data to be sent to and received from a SCO connection. Up to three SCO connections can be supported by the PCM interface at any one time(1). BlueCore3-ROM CSP can operate as the PCM interface Master generating an output clock of 128, 256 or 512kHz. When configured as PCM interface slave it can operate with an input clock up to 2048kHz. BlueCore3-ROM CSP is compatible with a variety of clock formats, including Long Frame Sync, Short Frame Sync and GCI timing environments. It supports 13 or 16-bit linear, 8-bit -law or A-law companded sample formats at 8ksamples/s and can receive and transmit on any selection of three of the first four slots following PCM_SYNC. The PCM configuration options are enabled by setting the PS Key PS KEY_PCM_CONFIG (0x1b3). BlueCore3-ROM CSP interfaces directly to PCM audio devices including the following: Qualcomm MSM 3000 series and MSM 5000 series CDMA baseband devices OKI MSM7705 four channel A-law and -law CODEC Motorola MC145481 8-bit A-law and -law CODEC Motorola MC145483 13-bit linear CODEC STW 5093 and 5094 14-bit linear CODECs BlueCore3-ROM CSP is also compatible with the Motorola SSITM interface
Note:
(1)
_aiEceEPJolj=pm Product Data Sheet
Subject to firmware support, contact CSR for current status.
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8.7.1
PCM Interface Master/Slave
When configured as the Master of the PCM interface, BlueCore3-ROM CSP generates PCM_CLK and PCM_SYNC.
BlueCore3-ROM CSP
PCM_OUT
_aiEceEPJolj=pm Product Data Sheet
PCM_IN PCM_CLK PCM_SYNC 128/256/512kHz 8kHz
Figure 8.26: BlueCore3-ROM CSP as PCM Interface Master
When configured as the Slave of the PCM interface, BlueCore3-ROM accepts PCM_CLK rates up to 2048kHz.
BlueCore3-ROM CSP
PCM_OUT PCM_IN PCM_CLK PCM_SYNC Upto 2048kHz 8kHz
Figure 8.27: BlueCore3-ROM CSP as PCM Interface Slave
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8.7.2
Long Frame Sync
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When BlueCore3-ROM CSP is configured as PCM Master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long. When BlueCore3-ROM CSP is configured as PCM Slave, PCM_SYNC may be from two consecutive falling edges of PCM_CLK to half the PCM_SYNC rate, i.e. 62.5s long.
PCM_SYNC
_aiEceEPJolj=pm Product Data Sheet
PCM_CLK
PCM_OUT
1
2
3
4
5
6
7
8
PCM_IN
Undefined
1
2
3
4
5
6
7
8
Undefined
Figure 8.28: Long Frame Sync (Shown with 8-bit Companded Sample)
BlueCore3-ROM CSP samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge.
8.7.3
Short Frame Sync
In Short Frame Sync the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always one clock cycle long.
PCM_SYNC
PCM_CLK
PCM_OUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
PCM_IN
Undefined
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Undefined
Figure 8.29: Short Frame Sync (Shown with 16-bit Sample)
As with Long Frame Sync, BlueCore3-ROM CSP samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge.
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8.7.4
Multi Slot Operation
More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO connections can be carried over any of the first four slots.
LONG_PCM_SYNC Or SHORT_PCM_SYNC
_aiEceEPJolj=pm Product Data Sheet
PCM_CLK
PCM_OUT
1
2
3
4
5
6
78
1
2
3
4
5
6
7
8
PCM_IN
Do Not Care 1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8 Do Not Care
Figure 8.30: Multi Slot Operation with Two Slots and 8-bit Companded Samples
8.7.5
GCI Interface
BlueCore3-ROM CSP is compatible with the General Circuit Interface, a standard synchronous 2B+D ISDN timing interface. The two 64Kbps B channels can be accessed when this mode is configured.
PCM_SYNC
PCM_CLK
PCM_OUT
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
PCM_IN
Do Not C a re
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Do Not C a re
B1 Channel
B2 Channel
Figure 8.31: GCI Interface
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With BlueCore3-ROM CSP in Slave mode, the frequency of PCM_CLK can be up to 4.096MHz.
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8.7.6
Slots and Sample Formats
BlueCore3-ROM CSP can receive and transmit on any selection of the first four slots following each sync pulse. Slot durations can be either 8 or 16 clock cycles. Duration's of 8 clock cycles may only be used with 8-bit sample formats. Durations of 16 clocks may be used with 8, 13 or 16-bit sample formats. BlueCore3-ROM CSP supports 13-bit linear, 16-bit linear and 8-bit -law or A-law sample formats. The sample rate is 8ksamples/s. The bit order may be little or big endian. When 16-bit slots are used, the 3 or 8 unused bits in each slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with some Motorola CODECs.
Sign Extension PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
_aiEceEPJolj=pm Product Data Sheet
8-Bit Sample A 16-bit slot with 8-bit companded sample and sign extension selected.
8-Bit Sample PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Zeros Padding A 16-bit slot with 8-bit companded sample and zeros padding selected.
Sign Extension PCM_OUT 1 2 3 4 5 6 7 8 9 10 13-Bit Sample A 16-bit slot with 13-bit linear sample and sign extension selected. 11 12 13 14 15 16
13-Bit Sample PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Audio Gain A 16-bit slot with 13-bit linear sample and audio gain selected. 16
Figure 8.32: 16-Bit Slot Length and Sample Formats
8.7.7
Additional Features
BlueCore3-ROM CSP has a mute facility that forces PCM_OUT to be 0. In Master mode, PCM_SYNC may also be forced to 0 while keeping PCM_CLK running which some CODECS use to control power down.
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8.7.8
PCM Timing Information
Parameter
4MHz DDS generation. Selection of frequency is programmable, see Table 8.12
Symbol
Min
Typ
128
Max
Unit
-
256 512
-
kHz
fmclk
PCM_CLK frequency
48MHz DDS generation. Selection of frequency is programmable, see Table 8.13 and Section 8.7.10 4MHz DDS generation 4MHz DDS generation 48MHz DDS generation
2.9
-
kHz
_aiEceEPJolj=pm Product Data Sheet
tmclkh(1) tmclkl(1) tdmclksynch tdmclkpout tdmclklsyncl tdmclkhsyncl tdmclklpoutz tdmclkhpoutz tsupinclkl thpinclkl
PCM_SYNC frequency PCM_CLK high PCM_CLK low PCM_CLK jitter
980 730
8 21 -
kHz ns ns ns pk-pk ns ns ns ns ns ns ns ns
Delay time from PCM_CLK high to PCM_SYNC high Delay time from PCM_CLK high to valid PCM_OUT Delay time from PCM_CLK low to PCM_SYNC low (Long Frame Sync only) Delay time from PCM_CLK high to PCM_SYNC low Delay time from PCM_CLK low to PCM_OUT high impedance Delay time from PCM_CLK high to PCM_OUT high impedance Set-up time for PCM_IN valid to PCM_CLK low Hold time for PCM_CLK low to PCM_IN invalid
30 10
-
20 20 20 20 20 20 -
Table 8.10: PCM Master Timing
Note:
(1)
Assumes normal system clock operation. Figures will vary during low power modes, when system clock speeds are reduced.
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Device Terminal Descriptions
t t PCM_SYNC
dmclksynch
dmclklsyncl
t
dmclkhsyncl
f t PCM_CLK
mclkh
mlk
t
mclkl
_aiEceEPJolj=pm Product Data Sheet
t t PCM_OUT
dmclkpout
dmclklpoutz
t ,t
r
f
t LSB (MSB)
dmclkhpoutz
MSB (LSB)
t PCM_IN
supinclkl
t
hpinclkl
MSB (LSB)
LSB (MSB)
Figure 8.33: PCM Master Timing Long Frame Sync
t dmclksynch PCM_SYNC
t dmclkhsyncl
fmlk t mclkh PCM_CLK t mclkl
t dmclklpoutz t dmclkpout PCM_OUT MSB (LSB) tr ,t f LSB (MSB) t dmclkhpoutz
t supinclkl PCM_IN
t hpinclkl LSB (MSB)
MSB (LSB)
Figure 8.34: PCM Master Timing Short Frame Sync
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8.7.9
Symbol
fsclk fsclk tsclkl tsclkh thsclksynch tsusclksynch tdpout tdsclkhpout tdpoutz tsupinsclkl thpinsclkl
PCM Slave Timing
Parameter
PCM clock frequency (Slave mode: input) PCM clock frequency (GCI mode) PCM_CLK low time PCM_CLK high time Hold time from PCM_CLK low to PCM_SYNC high Set-up time for PCM_SYNC high to PCM_CLK low Delay time from PCM_SYNC or PCM_CLK whichever is later, to valid PCM_OUT data (Long Frame Sync only) Delay time from CLK high to PCM_OUT valid data Delay time from PCM_SYNC or PCM_CLK low, whichever is later, to PCM_OUT data line high impedance Set-up time for PCM_IN valid to CLK low Hold time for PCM_CLK low to PCM_IN invalid
Min
64 128 200 200 30 30 30 30
Typ
-
Max
2048 4096 20 20 20 -
Unit
kHz kHz ns ns ns ns ns ns ns ns ns
_aiEceEPJolj=pm Product Data Sheet
Table 8.11: PCM Slave Timing
f t PCM_CLK
sclkh
sclk
t
tsclkl
t PCM_SYNC
hsclksynch
t
susclksynch
t t PCM_OUT
dpout
dpoutz
t
dsclkhpout
t ,t
r
f
t
dpoutz
MSB (LSB)
LSB (MSB)
t PCM_IN
supinsclkl
t
hpinsclkl
MSB (LSB)
LSB (MSB)
Figure 8.35: PCM Slave Timing Long Frame Sync
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Device Terminal Descriptions
fsclk t sclkh PCM_CLK t tsclkl
t susclksynch PCM_SYNC
t hsclksynch
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t dsclkhpout PCM_OUT MSB (LSB)
tr ,t f LSB (MSB)
t dpoutz
t dpoutz
t supinsclkl PCM_IN
t hpinsclkl LSB (MSB)
MSB (LSB)
Figure 8.36: PCM Slave Timing Short Frame Sync
8.7.10 PCM_CLK and PCM_SYNC Generation
BlueCore3-ROM CSP has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is generating these signals by Direct Digital Synthesis (DDS) from BlueCore3-ROM CSP internal 4MHz clock (which is used in BlueCore3-ROM CSP). Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz. The second is generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock which allows a greater range of frequencies to be generated with low jitter but consumes more power. This second method is selected by setting bit `48M_PCM_CLK_GEN_EN' in PSKEY_PCM_CONFIG32.
Note:
The bit `SLAVE_MODE_EN' should also be set. When in this mode and with long frame sync, the length of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by `LONG_LENGTH_SYNC_EN' in PSKEY_PCM_CONFIG32. The Equation 8.8 describes PCM_CLK frequency when being generated using the internal 48MHz clock:
f= CNT _ RATE x 24MHz CNT _ LIMIT
Equation 8.8: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock
The frequency of PCM_SYNC relative to PCM_CLK can be set using following equation:
f= PCM _ CLK SYNC _ LIMIT x 8
Equation 8.9: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
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Device Terminal Descriptions
8.7.11 PCM Configuration
The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 and PSKEY_PCM_LOW_JITTER_CONFIG. The following tables detail these PS Keys. PSKEY_PCM_CONFIG32. The default for this key is 0x00800000 i.e. first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no tristating of PCM_OUT. PSKEY_PCM_LOW_JITTER_CONFIG is described in Table 8.13.
Name
SLAVE_MODE_EN
Bit Position
0 1
Description
Set to 0.
_aiEceEPJolj=pm Product Data Sheet
0 selects Master mode with internal generation of PCM_CLK and PCM_SYNC. 1 selects Slave mode requiring externally generated PCM_CLK and PCM_SYNC. This should be set to 1 if 48M_PCM_CLK_GEN_EN (bit 11) is set. 0 selects long frame sync (rising edge indicates start of frame), 1 selects short frame sync (falling edge indicates start of frame). Set to 0. 0 selects padding of 8 or 13-bit voice sample into a 16bit slot by inserting extra LSBs, 1 selects sign extension. When padding is selected with 13-bit voice sample, the 3 padding bits are the audio gain setting; with 8-bit samples the 8 padding bits are zeroes. 0 transmits and receives voice samples MSB first, 1 uses LSB first. 0 drives PCM_OUT continuously, 1 tri-states PCM_OUT immediately after the falling edge of PCM_CLK in the last bit of an active slot, assuming the next slot is not active. 0 tristates PCM_OUT immediately after the falling edge of PCM_CLK in the last bit of an active slot, assuming the next slot is also not active. 1 tristates PCM_OUT after the rising edge of PCM_CLK. 0 enables PCM_SYNC output when master, 1 suppresses PCM_SYNC whilst keeping PCM_CLK running. Some CODECS utilise this to enter a low power state. 1 enables GCI mode. 1 forces PCM_OUT to 0. 0 sets PCM_CLK and PCM_SYNC generation via DDS from internal 4 MHz clock, as for BlueCore3-ROM CSP. 1 sets PCM_CLK and PCM_SYNC generation via DDS from internal 48 MHz clock. 0 sets PCM_SYNC length to 8 PCM_CLK cycles and 1 sets length to 16 PCM_CLK cycles. Only applies for long frame sync and with 48M_PCM_CLK_GEN_EN set to 1. Set to 0b00000. Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz PCM_CLK frequency when master and 48M_PCM_CLK_GEN_EN (bit 11) is low. Default is `0001'. Ignored by firmware. Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit sample with 16 cycle slot duration or 8 (0b11) bit sample with 8 cycle slot duration.
SHORT_SYNC_EN
2
SIGN_EXTEND_EN
3 4
LSB_FIRST_EN TX_TRISTATE_EN
5 6
TX_TRISTATE_RISING_EDGE_EN
7
SYNC_SUPPRESS_EN
8
GCI_MODE_EN MUTE_EN 48M_PCM_CLK_GEN_EN
9 10 11
LONG_LENGTH_SYNC_EN
12
MASTER_CLK_RATE
[20:16] [22:21]
ACTIVE_SLOT SAMPLE_FORMAT
[26:23] [28:27]
Table 8.12: PSKEY_PCM_CONFIG32 Description Production Information (c) Cambridge Silicon Radio Limited 2005-2006
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Device Terminal Descriptions
Name
CNT_LIMIT CNT_RATE SYNC_LIMIT
Bit Position
[12:0] [23:16] [31:24]
Description
Sets PCM_CLK counter limit. Sets PCM_CLK count rate. Sets PCM_SYNC division relative to PCM_CLK.
Table 8.13: PSKEY_PCM_LOW_JITTER_CONFIG Description
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Device Terminal Descriptions
8.8
I/O Parallel Ports
Ten lines of programmable bi-directional input/outputs (I/O) are provided. PIO[3:0] are powered from VDD_PIO. PIO[7:4] are powered from VDD_PADS. AIO [2:0] are powered from VDD_USB. PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines are configured as inputs with weak pull-downs at reset. See section 2 CSP Package Information for details. Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or PIO[2] can be configured as a request line for an external clock source. This is useful when the clock to BlueCore3-ROM CSP is provided from a system application specific integrated circuit (ASIC). BlueCore3-ROM CSP has two general purpose analogue interface pins, AIO[0] and AIO[2]. These are used to access internal circuitry and control signals. One pin is allocated to decoupling for the on-chip bandgap reference voltage, the other two may be configured to provide additional functionality. Auxiliary functions available via these pins include an 8-bit ADC and an 8-bit DAC. Typically the ADC is used for battery voltage measurement. Signals selectable at these pins include the bandgap reference voltage and a variety of clock signals; 48, 24, 16, 8MHz and the XTAL clock frequency. When used with analogue signals the voltage range is constrained by the analogue supply voltage (1.8V). When configured to drive out digital level signals (clocks) generated from within the analogue part of the device, the output voltage level is determined by VDD_MEM (1.8V).
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Device Terminal Descriptions
8.9
TCXO Enable OR Function
An OR function exists for clock enable signals from a host controller and BlueCore3-ROM CSP where either device can turn on the clock without having to wake up the other device. PIO[3] can be used as the Host clock enable input and PIO[2] can be used as the OR output with the TCXO enable signal from BlueCore3-ROM CSP.
VDD
GSM System TCXO
CLK IN Enable CLK REQ OUT
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BlueCore System
CLK REQ IN/ PIO[3] CLK IN CLK REQ OUT/ PIO[2]
Figure 8.37: Example TXCO Enable OR Function
On reset and up to the time the PIO has been configured, PIO[2] will be tri-stated. Therefore, the developer must ensure that the circuitry connected to this pin is pulled via a 470k resistor to the appropriate power rail. This ensures that the TCXO is oscillating at start up.
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Device Terminal Descriptions
8.10
RESETB
BlueCore3-ROM CSP may be reset from several sources: RESETB pin, power on reset, a UART break character or via a software configured watchdog timer. The RESETB pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset will be performed between 1.5 and 4.0ms following RESETB being active. CSR recommends that RESETB is applied for a period greater than 5ms. The power on reset occurs when the VDD_CORE supply falls below typically 1.5V and is released when VDD_CORE rises above typically 1.6V. At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-stated. The PIOs have weak pull-downs. Following a reset, BlueCore3-ROM CSP assumes the maximum XTAL_IN frequency which ensures that the internal clocks run at a safe (low) frequency until BlueCore3-ROM CSP is configured for the actual XTAL_IN frequency. If no clock is present at XTAL_IN, the oscillator in BlueCore3-ROM CSP free runs, again at a safe frequency.
_aiEceEPJolj=pm Product Data Sheet
8.10.1 Pin States on Reset
Table 8.14 shows the pin states of BlueCore3-ROM CSP on reset.
Pin name
PIO[7:0] PCM_OUT PCM_IN PCM_SYNC PCM_CLK UART_TX UART_RX UART_RTS (BC313143A only) UART_CTS (BC313143A only) USB_DP (BC313141A only) USB_DN (BC313141A only) SPI_CSB SPI_CLK SPI_MOSI SPI_MISO AIO[2] RESET RESETB TEST_EN XTAL_IN XTAL_OUT
State: BlueCore3-ROM CSP
Input with weak pull-down Tri-stated with weak pull-down Input with weak pull-down Input with weak pull-down Input with weak pull-down Output tri-stated with weak pull-up Input with weak pull-down Output tri-stated with weak pull-up Input with weak pull-down Input with weak pull-down Input with weak pull-down Input with weak pull-up Input with weak pull-down Input with weak pull-down Output tri-stated with weak pull-down Output, driving low Input with weak pull-down Input with weak pull-up Input with strong pull-down High impedance, 250k to XTAL_OUT High impedance, 250k to XTAL_IN
Table 8.14: Pin States of BlueCore3-ROM CSP on Reset
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Device Terminal Descriptions
8.10.2 Status after Reset
The chip status after a reset is as follows: Warm Reset: Baud rate and RAM data remain available Cold Reset(1): Baud rate and RAM data not available
Note:
(1)
Cold Reset constitutes one of the following: Power cycle
_aiEceEPJolj=pm Product Data Sheet
System reset (firmware fault code) Reset signal, see Section 8.10
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Device Terminal Descriptions
8.11
Power Supply
8.11.1 Voltage Regulator
An on-chip linear voltage regulator can be used to power the 1.8V dependant supplies. It is advised that a smoothing circuit using a 2.2F low ESR capacitor and 2.2 resistor be placed on the output VDD_ANA. The regulator is switched into a low power mode when the device is sent into deep sleep mode. When the on-chip regulator is not required VDD_ANA is a 1.8V input and VREG_IN must be either open circuit or tied to VDD_ANA.
_aiEceEPJolj=pm Product Data Sheet
8.11.2 Sequencing
It is recommended that VDD_CORE, VDD_RADIO and VDD_VCO are powered at the same time, this is true when these supplies are powered from the internal regulator on BlueCore3-ROM CSP. The order of powering supplies for VDD_PIO, VDD_PADS and VDD_USB is not important. However, if VDD_CORE is not present all inputs have a weak pull-down irrespective of the reset state.
8.11.3 Sensitivity to Disturbances
It is recommended that if you are supplying BlueCore3-ROM CSP from an external voltage source that VDD_VCO, VDD_ANA and VDD_RADIO should have less than 10mV rms noise levels between 0 to 10MHz. Single tone frequencies are also to be avoided. A simple RC filter is recommended for VDD_CORE as this isoloates the power supply rails from on-chip transients. The transient response of the regulator is also important as at the start of a packet, power consumption will jump to the levels defined in average current consumption section. It is essential that the power rail recovers quickly, so the regulator should have a response time of 20s or less.
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Application Schematic
9
9.1
Application Schematic
BC313141AXX (UART) CSP Package
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Figure 9.1: Application Circuit for CSP Package
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Application Schematic
9.2
BC313143AXX (USB) CSP Package
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Figure 9.2: Application Circuit for CSP Package
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PCB Design and Assembly Considerations
10 PCB Design and Assembly Considerations
10.1 3.8mm x 3.4mm CSP 42-Ball Package
The following list details the recommendations to achieve maximum board-level reliability of the BlueCore3-ROM CSP 3.8mm x 3.4mm CSP 42-ball package: Non-solder mask defined (NSMD) lands - lands smaller than the solder mask aperture - are preferred, because of the greater accuracy of the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack initiation Ideally, via-in-pad technology should be employed to achieve truly NSMD lands. Where this is not possible, a maximum of one trace connected to each land is preferred and this trace should be as thin as possible - taking into consideration its current carrying and the radio frequency (RF) requirements 35 micron thick (1 oz.) copper lands are recommended rather than 17 micron thick (1/2 oz.), because this results in a greater standoff, which has been proven to provide greater reliability during thermal cycling Land diameter should be 275 microns +/-10 microns to achieve optimum reliability Solder paste is preferred to flux during the assembly process, as this adds to the final volume of solder in the joint, increasing its reliability Where possible, the lands should be finished with organic solderability preservative (OSP). Were a nickel gold plating finish is used, the gold thickness should be kept below 0.5 microns in order to prevent brittle gold/tin intermetallics forming in the solder CSP devices have been proven to be reliable. However, by their nature they are more susceptible to handling damage than plastic packaged devices. Care should be taken to optimise placement equipment settings for CSPs and care should be taken when handling PCBs with CSPs attached.
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Package Dimensions
11 Package Dimensions
11.1 BC313141AXX-IXF and BC313143AXX-IXF CSP 42-Ball Package
_aiEceEPJolj=pm Product Data Sheet
Figure 11.1: BlueCore3-ROM CSP Package Dimensions Production Information (c) Cambridge Silicon Radio Limited 2005-2006
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Tape and Reel Information
12 Tape and Reel Information
12.1 Tape Information 12.1.1 WLCSP Tape Orientation
Figure 12.1 shows the general orientation of the CSP package in the carrier tape.
_aiEceEPJolj=pm Product Data Sheet
Figure 12.1: CSP Tape and Reel Orientation
Where possible the Pin A1 marker will be placed at position 1. Where the aspect ratio of the CSP does not make this possible, the Pin 1 marker will be placed at position 2. For BlueCore3-ROM CSP the marker is in position 2.
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Tape and Reel Information
12.1.2 Package Tape Dimensions
The diagram shown in Figure 12.2 outlines the dimensions of the tape used for the various packages:
See Note 2 1.55 0.05
_aiEceEPJolj=pm Product Data Sheet
5.5 See Note 2
1. 10 sprocket hole pitch cumulative tolerance 0.1. 2. Pocket position relative to sprocket hole measured as true position of pocket , not pocket hole.
Figure 12.2: Package Tape Dimensions Package Type
3.8 x 3.4 x 0.7mm CSP
A1
4.01mm
B1
3.55mm
C1
8mm
D1
12mm
E1
0.87mm
Figure 12.3: Tape Dimensions
The cover tape has a total peel strength of 0.1N to 1.3N. The direction of the pull should be opposite the direction of the carrier tape such that the cover tape makes an angle of between 165 and 180 with the top of the carrier tape. The carrier and/or cover tape should be pulled with a velocity of 30010mm during peeling. Maximum component rotation inside the cavity is 10. The cavity pitch tolerance (dimension P1) is 0.1mm. The reel is made of high impact injection molded polystyrene. The carrier tape is made of polystyrene with carbon. The cover tape is made of antistatic polyester film and an antistatic heat activated adhesive coating.
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Tape and Reel Information
12.2
Reel Information
_aiEceEPJolj=pm Product Data Sheet
Figure 12.4: Reel Dimensions Package Type Tape Width A Max B Max D Min N Min W2 Max W3 Units Min
11.9
C
13.0 (+0.5/-0.2)
W1
12.4 (+2.0/-0.0)
Max
15.4 mm
CSP
12
330
1.5
20.2
50
18.4
Table 12.1: Reel Dimensions
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Solder Profile
13 Solder Profile
The soldering profile depends on various parameters necessitating a set up for each application. The data here is given only for guidance on solder re-flow. There are four zones: 1. 2.
Preheat Zone: This zone raises the temperature at a controlled rate, typically 1-2.5C/s. Equilibrium Zone: This zone brings the board to a uniform temperature and also activates the flux. The duration in this zone (typically 2-3 minutes) will need to be adjusted to optimise the out gassing of the flux. Reflow Zone: The peak temperature should be high enough to achieve good wetting but not so high as to cause component discoloration or damage. Excessive soldering time can lead to intermetallic growth which can result in a brittle joint. Cooling Zone: The cooling rate should be fast, to keep the solder grains small which will give a longer lasting joint. Typical rates will be 2-5C/s.
3.
_aiEceEPJolj=pm Product Data Sheet
4.
13.1 Typical Solder Re-flow Profile for Devices with Lead-Free Solder Balls
Composition of the solder ball: Sn 96.8%, Ag 2.6%, Cu 0.6% or Sn 95.5%, Ag 4.0%, Cu 0.5%.
Figure 13.1: Typical Lead-Free Re-flow Solder Profile
Key features of the profile: Initial Ramp = 1-2.5C/sec to 175C25C equilibrium Equilibrium time = 60 to 180 seconds Ramp to Maximum temperature (250C) = 3C/sec max. Time above liquidus temperature (217C): 45-90 seconds Device absolute maximum reflow temperature: 260C Devices will withstand the specified profile. Lead-free devices will withstand up to 3 reflows to a maximum temperature of 260C.
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Ordering Information
14 Ordering Information
14.1 BlueCore3-ROM CSP
Package Type
42-Ball CSP (Pb free) 42-Ball CSP (Pb free)
Interface Version
Order Number Shipment Method
Tape and reel Tape and reel BC313141AXX-IXF-E4
Size
UART Only (4 wire) USB and UART 3 wire UART (H5) and BCSP
Note:
3.8 x 3.4 x 0.7mm 3.8 x 4.0 x 0.7mm
_aiEceEPJolj=pm Product Data Sheet
Discontinued
XX denotes firmware type and firmware version status. These are determined on a customer and project basis. Minimum Order Quantity: 2kpcs Taped and Reeled
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Contact Information
15 Contact Information
_aiEceEPJolj=pm Product Data Sheet
CSR UK Cambridge Business Park Cowley Road Cambridge, CB4 0WZ United Kingdom Tel: +44 (0) 1223 692 000 Fax: +44 (0) 1223 692 001 e-mail: sales@csr.com
CSR Denmark Novi Science Park Niels Jernes Vej 10 9220 Aalborg East Denmark Tel: +45 72 200 380 Fax: +45 96 354 599 e-mail: sales@csr.com
CSR Japan 9F Kojimachi KS Square 5-3-3, Kojimachi, Chiyoda-ku, Tokyo 102-0083 Japan Tel: +81 3 5276 2911 Fax: +81 3 5276 2915 e-mail: sales@csr.com
CSR Korea Rm. 1111 Keumgang Venturetel, #1108 Beesan-dong, Dong An-ku, Anyang-city, Kyunggi-do 431-050, Korea Tel: +82 31 389 0541 Fax : +82 31 389 0545 e-mail: sales@csr.com
CSR Taiwan 6th Floor, No.407 Rui Guang Road Neihu, Taipei 114 Taiwan R.O.C. Tel: +886 2 7721 5588 Fax: +886 2 7721 5589CSR e-mail: sales@csr.com
CSR U.S. 2524 N. Central Expressway Suite 1000 Richardson, TX 75080 Tel: +1 (972) 238 2300 Fax: +1 (972) 231 1440 e-mail: sales@csr.com
To contact a CSR representative, go to http://www.csr.com/contacts.htm
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Document References
16 Document References
Document
Specification of the Bluetooth system Universal Serial Bus Specification Restrictions of Hazardous Substances
Reference
v1.2, 0.95, 10 October 2002 v1.1, 23 September 1998 RoHS directive 2002/95/EC
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Terms and Definitions
Terms and Definitions
BlueCore Bluetooth ACL AC ADC AGC A-law API BCSP BER BGA BIST BOM BMC C/I CDMA CMOS CODEC CPU CQDDR CSB CSP CSR CTS CVSD DAC dBm DC DFU eSCO FSK GSM HCI HV I/O IQ Modulation IF ISDN ISM ksamples/s L2CAP LC Group term for CSR's range of Bluetooth chips A set of technologies providing audio and data transfer over short-range radio connections Asynchronous Connection-Less. A Bluetooth data packet Alternating Current Analogue to Digital Converter Automatic Gain Control Audio encoding standard Application Programming Interface BlueCoreTM Serial Protocol Bit Error Rate. Used to measure the quality of a link Ball Grid Array Built-In Self-Test Bill of Materials. Component part list and costing for a product Burst Mode Controller Carrier Over Interferer Code Division Multiple Access Complementary Metal Oxide Semiconductor Coder Decoder Central Processing Unit Channel Quality Driven Data Rate Chip Select (Active Low) Chip Scale Package Cambridge Silicon Radio Clear to Send Continuous Variable Slope Delta Modulation Digital to Analogue Converter Decibels relative to 1mW Direct Current Device Firmware Upgrade Extended Synchronous Connection-Oriented Frequency Shift Keying Global System for Mobile communications Host Controller Interface Header Value Input Output In-Phase and Quadrature Modulation Intermediate Frequency Integrated Services Digital Network Industrial, Scientific and Medical kilosamples per second Logical Link Control and Adaptation Protocol (protocol layer) Link Controller
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Terms and Definitions
LCD LNA LSB
-law
Liquid Crystal Display Low Noise Amplifier Least-Significant Bit Audio Encoding Standard Memory Management Unit Master In Serial Out Open Host Controller Interface Power Amplifier Printed Circuit Board Pulse Code Modulation. Refers to digital voice data Personal Digital Assistant Protocol Implementation Conformance Statement Parallel Input Output Phase Lock Loop parts per million Persistent Store Key Random Access Memory Read enable (Active Low) Radio Frequency Protocol layer providing serial port emulation over L2CAP Reduced Instruction Set Computer root mean squared Read Only Memory Restrictions of Hazardous Substances Receive Signal Strength Indication Ready To Send Receive or Receiver Synchronous Connection-Oriented. Voice oriented Bluetooth packet Software Development Kit Service Discovery Protocol Special Interest Group Serial Peripheral Interface Signal Strength Indication To Be Announced To Be Defined Temperature Controlled crystal Oscillator Transmit or Transmitter Universal Asynchronous Receiver Transmitter Upper Host Control Interface Universal Serial Bus or Upper Side Band (depending on context) Voltage Controlled Oscillator Very Fine Ball Grid Array Virtual Machine Wideband Code Division Multiple Access Write Enable (Active Low)
MMU MISO OHCI PA PCB PCM PDA PICS PIO PLL ppm PS Key RAM REB RF RFCOMM RISC rms ROM RoHS RSSI RTS RX SCO SDK SDP SIG SPI SSI TBA TBD TCXO TX UART UHCI USB VCO VFBGA VM W-CDMA WEB
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Document History
Document History
Date
MAY 04 AUG 04 FEB 05 MAR 05 APR 05
Revision
a b c d e
Reason for Change
Original publication of Advance Information Product Data Sheet (CSR reference BC313143ACS-ds-001Pa) Changes made to package diagram. Production radio characteristics added
_aiEceEPJolj=pm Product Data Sheet
Typical peak current @20C added to Power Consumption Updated Power Consumption. Transmitter/Receiver S-Parameters and Transmit/Receive Impedances added to Device Terminal Descriptions. Amendment to note concerning VREG_EN and VREG_IN in Linear Regulator table of Electrical Characteristics section.
JUN 05
f
Changed title of Record of Changes to Document History; changed title of Acronyms and Abbreviations to Terms and Definitions Changed copyright information on Status Information page Tape and reel information updated Changes to reflect obsolete part BC313143A. Solder ball composition clarified. Key features section updated for consistency
JUL 05 JUL 05 NOV 06
g h i
= _aiEceEPJolj=pm= Product Data Sheet BC313143ACS-db-001Pi November 2006
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