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TDA19989
150 MHz pixel rate HDMI 1.3 transmitter with 3 x 8-bit video inputs, HDCP and CEC support
Rev. 01 -- 15 February 2010 Preliminary data sheet
1. General description
TDA19989 is a very low power and very small size High-Definition Multimedia Interface (HDMI) v. 1.3a transmitter. It is backward compatible DVI 1.0 and can be connected to any DVI 1.0 and HDMI sink. This device is primarily intended for mobile applications like Digital Video Camera (DVC), Digital Still Camera (DSC), Portable Multimedia Player (PMP), Mobile Phone and Ultra-Mobile Personal Computer (UM PC) where size and very low power are mandatory for battery autonomy. It allows mixing 3 x 8-bit RGB or YCbCr video stream with a pixel rate up to 150 MHz together with one S/PDIF or one I2S-bus audio streams with an audio sampling rate up to 192 kHz. In order to be compatible with most applications, TDA19989 integrates a full programmable input formatter and color space conversion block. The video input formats accepted are YCbCr 4 :4 : 4 (up to 3 x 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to 2 x 12-bit) and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 x 12-bit). In case of ITU656-like format, the input pixel clock can be made active on one (SDR mode) or both edges (DDR mode). TDA19989 includes a HDCP 1.3 compliant cipher block. The HDCP key are stored internally in a non-volatile OTP memory for maximum security. This device provides additional embedded feature like CEC (Consumer Electronic Control). CEC is a single bidirectional wire that transmits CEC commands (like Standby from remote control) over the home appliance network connected through this wire. This eliminates the need of any additional device to handle this feature thus improving BOM (Bill Of Materials) of the whole system and enable the connected devices (CEC enabled) to be controlled by only one remote control. TDA19989 supports xvYCC HDMI 1.3a feature. It can be switched to very low power Standby or Sleep modes to save power when HDMI is not used. TDA19989 includes I2C-bus master interface for DDC-bus communication for EDID reading and HDCP purpose. This device can be controlled or configured via I2C-bus interface.
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
I2C-BUS SLAVE I2S-bus
PLL SERIALIZER PIXEL, REPETITION
CEC
CEC
AUDIO S/PDIF video RGB YCbCr INPUT FORMATTER COLOR SPACE CONVERTER
HDCP 1.3 cipher
HDMI ENCODER SERIALIZER
HMDI TMDS link
I2C-BUS MASTER DDC-BUS
001aal264
Fig 1.
TDA19989 high-level block diagram
2. Features
Compliance: DVI 1.0 HDMI 1.3a EIA/CEA-861B CEC (HDMI 1.3) SimplayHD HDCP 1.3 Video: xvYCC HDMI 1.3 feature Video formats with a pixel rate up to 150 MHz: RGB 4 : 4 : 4 YCbCr 4 : 4 : 4 YCbCr 4 : 2 : 2 semi-planar YCbCr 4 : 2 : 2 ITU656 Maximum resolution: 1080p for TV 1600 x 1200 at 60 Hz for PC (UXGA60) 720p/1080i in ITU656 Programmable color space converter: RGB to YCbCr YCbCr to RGB Programmable input formatter and upsampler/interpolator allows input of any of the 4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656-like formats Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs or VREF, HREF and FREF could be used for input data synchronization Pixel clock input can be made active on one or both edges (selectable by I2C-bus) Repetition of video samples as required by HDMI specification Audio: 2 x I2S-bus 2 channels and S/PDIF; audio data rate up to 192 kHz per input for both standards Deals with multiple levels of HDCP receivers and repeaters
TDA19989_1 (c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 February 2010
2 of 47
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
Internal SHA-1 calculation System operation: Master DDC-bus interface for EDID read Controllable via I2C-bus Downstream availability through the use of hot plug detect (HPD) and receiver detection (RxSense) Deals with multiple levels of receivers and repeaters Package: TFBGA64 Size 4.5 x 4.5 x 0.95 mm Power management: External voltage supplies 1.8 V Low power Flexible power modes Miscellaneous: POR (Power-On Reset) Audio and video inputs LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant 250 MHz to 1.5 GHz TMDS transmitter operation
3. Applications
Digital Video Camera (DVC) Digital Still Camera (DSC) Portable Multimedia Player (PMP) Mobile Phone Ultra-Mobile Personal Computer (UM PC)
4. Ordering information
Table 1. Ordering information Package Name TDA19989AET TFBGA64 Description Version plastic thin fine-pitch ball grid array package; 64 balls SOT962-3 Type number
TDA19989_1
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 February 2010
3 of 47
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Preliminary data sheet Rev. 01 -- 15 February 2010
(c) NXP B.V. 2010. All rights reserved. TDA19989_1
5. Block diagram
NXP Semiconductors
AUDIO PROCESSING ACLK AUDIO CAPTURE PROCESSING CTS/N FIFO BUFFER
HDMI PACKET INSERTION AUDIO CONTENT DATA ISLAND PACKET INSERTION
TDA19989
TMDS BLOCK RxSense TXC+
AP1
INFO FRAME
WS
ACR
OTP MEMORY KEYS HDCP PROCESSING
TXC- TX0+ HDMI SERIALIZER TX0- TX1+ TX1- TX2+ TX2-
PLL BLOCK VCLK CLOCK MANAGEMENT
NULL AND ACP
VHREF GENERATOR
DOWNSAMPLER(1) 4 : 4 : 4 to 4 : 2 : 2 3 x 8-bit RGB or YCbCr 4 : 4 : 4 2 x 12-bit YCbCr 4 : 4 : 2 semi-planar VIDEO INPUT DATA CAPTURE I2C-BUS/DDC-BUS INTERFACE REGISTERS UPSAMPLER 4:2:2 to 4:4:4 VIDEO PROCESSING COLOR SPACE CONVERTER(1) YCbCr to RGB RGB to YCbCr INTERRUPT GENERATION
EXT_SWING
HDMI 1.3 transmitter with HDCP and CEC support
VSYNC/VREF HSYNC/VREF DE/FREF VPA[0] to VPA[7] VPB[0] to VPB[7] VPC[0] to VPC[7]
HPD MANAGEMENT
HPD
INT
DDC-BUS MASTER
I2C-BUS SLAVE
CEC
CEC
DSCL DSDA
CSCL CSDA
001aal260
TDA19989
(1) The color space converter can be bypassed. The device can handle HDCP based on 1.3 features.
4 of 47
Fig 2.
TDA19989 Block diagram
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
6. Pinning information
6.1 Pinning
TDA19989
ball A1 index area A B C D E F G H
001aal266
1
2
3
4
5
6
7
8
Transparent top view
Fig 3.
Pin configuration (TFBGA64)
6.2 Pin description
Table 2. Symbol ACLK AP0 AP1 HPD EXT_SWING Pin description Pin H5 G5 F5 E6 E7 Type[1] I I I I O Description audio clock input audio port 0 input audio port 1 input hot plug detect; 5 V tolerant TMDS output swing adjustment; place resistor (REXT_SWING = 10 k 1 %) between this pin and analog ground. DDC-bus data input/output; 5 V tolerant DDC-bus clock input; 5 V tolerant input video pixel clock input horizontal synchronization or reference input input vertical synchronization or reference input data enable or field reference input I2C-bus clock input; 1.8 V to 3.3 V tolerant I2C-bus data input/output; 1.8 V to 3.3 V tolerant interrupt HDMI output (open-drain); this pin is used as Dual function pin selectable through I2C-bus. In calibration mode only this pin is used as input for 10 ms 1 % calibration pulse. In operation mode this pin is used to warn the external microprocessor that a special event has occurred for HDMI or CEC negative data channel 0 for TMDS output positive data channel 0 for TMDS output negative data channel 1 for TMDS output
(c) NXP B.V. 2010. All rights reserved.
DSDA DSCL VCLK HSYNC/HREF VSYNC/VREF DE/FREF CSCL CSDA INT
F6 F7 D4 F4 G4 H4 B5 A5 B6
I/O I I I I I I I/O I/O
TX0- TX0+ TX1-
TDA19989_1
E8 D8 C8
O O O
Preliminary data sheet
Rev. 01 -- 15 February 2010
5 of 47
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
Pin description ...continued Pin B8 A7 A6 G8 F8 H7 H6 G6 C1 B1 B2 A2 B3 A3 B4 A4 E3 E2 E1 D1 D2 D3 C2 C3 H3 H2 G3 G2 G1 F1 F2 F3 E4 C6 G7, H8 E5 Type[1] O O O O O I/O I I I I I I I I I I I I I I I I I I I I I I I I I I P P P P P Description positive data channel 1 for TMDS output negative data channel 2 for TMDS output positive data channel 2 for TMDS output negative clock channel for TMDS output positive clock channel for TMDS output CEC connection (open-drain) to HDMI connector input connected to the external oscillator circuit or external clock source/audio port 3 input audio port 2 input video port A input bit 0 (LSB) video port A input bit 1 video port A input bit 2 video port A input bit 3 video port A input bit 4 video port A input bit 5 video port A input bit 6 video port A input bit 7 (MSB) video port B input bit 0 (LSB) video port B input bit 1 video port B input bit 2 video port B input bit 3 video port B input bit 4 video port B input bit 5 video port B input bit 6 video port B input bit 7 (MSB) video port C input bit 0 (LSB) video port C input bit 1 video port C input bit 2 video port C input bit 3 video port C input bit 4 video port C input bit 5 video port C input bit 6 video port C input bit 7 (MSB) TMDS analog supply voltage (1.8 V) I/O digital supply voltage (1.8 V) PLL analog supply voltage (1.8 V), this PLL provides the clock for the serializer analog supply voltage (1.8 V), is used for parallel-to-serial shift register and miscellaneous blocks core digital supply voltage (1.8 V)
Table 2. Symbol TX1+ TX2- TX2+ TXC- TXC+ CEC
OSC_IN/AP3 AP2 VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] VDDD(IO)(1V8) VDDA(PLL)(1V8) VDDA(1V8) VDDDC
VDDA(TMDS)(1V8) A8, C7
TDA19989_1
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 February 2010
6 of 47
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
Pin description ...continued Pin D5 B7, C4, C5 D6, D7 Type[1] P G G Description core digital supply voltage (1.8 V) digital ground supply voltage, is used for digital core; I/O analog ground supply voltage, is used for PLL; serializer, transmitter, and parallel-to-serial shift register
Table 2. Symbol VDDDC VSSD VSSA
[1]
P = power supply, G = ground, I = input, O = output.
7. Functional description
TDA19989 is designed to convert digital data (video and audio) provided by Set-Top Boxes (STB), Digital Video Camera (DVC), Digital Still Camera (DSC), Portable Multimedia Player (PMP) or DVD into an HDMI output, which can be used by a TV with either an HDMI or DVI input. The video data input formats are:
* * * *
RGB 4 : 4 : 4 YCbCr 4 : 4 : 4 YCbCr 4 : 2 : 2 semi-planar YCbCr 4 : 2 : 2 ITU656-like
TDA19989 is able to output HDMI with the formats:
* RGB 4 : 4 : 4 * YCbCr 4 : 4 : 4 * YCbCr 4 : 2 : 2
It can also handle audio formats:
* two I2S-bus channels * one S/PDIF channel
TDA19989 is also designed to support CEC protocol. For more details about CEC, refer to HDMI 1.3a specification.
7.1 System clock
The system clock section has a PLL serializer. It is a system clock generator which enables the stream produced by the encoder to be transmitted on the HDMI data channel at ten times, or above, the sampling rate.
TDA19989_1
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 February 2010
7 of 47
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
7.2 Video input formatter
7.2.1 Description
TDA19989 has three video input ports VPA[0] to VPA[7], VPB[0] to VPB[7] and VPC[0] to VPC[7]. TDA19989 can accept any of the following video input modes (see Table 6):
* * * *
RGB, with 8-bit for each component YCbCr 4 : 4 : 4, with 8-bit for each component YCbCr 4 : 2 : 2 semi-planar, with up to 12-bit for each component (YCbCr) YCbCr 4 : 2 : 2 ITU656, with up to 12-bit data depth
TDA19989 can be set to latch data at either rising or falling edge, or both.
7.2.2 Internal assignment
The aim of the video input processor is to internally map the incoming data to the corresponding mode, which can be handled by the video processing. The internal signal named VP[23:0] is assigned depending on the input mode as defined below.
VPA[0] to VPA[7] VPB[0] to VPB[7] VPC[0] to VPC[7] VIDEO INPUT PROCESSOR VP[23:0]
001aah028
Fig 4. Table 3.
Internal assignment of VP[23:0] Internal assignment RGB G[7] G[6] G[5] G[4] G[3] G[2] G[1] G[0] B[7] B[6] B[5] B[4] YCbCr 4 : 4 : 4 Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] Y[0] Cb[7] Cb[6] Cb[5] Cb[4] YCbCr 4 : 2 : 2 semi-planar Y[11] Y[10] Y[9] Y[8] Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] Y[0] YCbCr 4 : 2 : 2 ITU656 YCbCr[11] YCbCr[10] YCbCr[9] YCbCr[8] YCbCr[7] YCbCr[6] YCbCr[5] YCbCr[4] YCbCr[3] YCbCr[2] YCbCr[1] YCbCr[0]
Internal assignment Internal port VP[23] VP[22] VP[21] VP[20] VP[19] VP[18] VP[17] VP[16] VP[15] VP[14] VP[13] VP[12]
TDA19989_1
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 February 2010
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
Internal assignment ...continued RGB B[3] B[2] B[1] B[0] R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0] YCbCr 4 : 4 : 4 Cb[3] Cb[2] Cb[1] Cb[0] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Cr[1] Cr[0] YCbCr 4 : 2 : 2 semi-planar CbCr[11] CbCr[10] CbCr[9] CbCr[8] CbCr[7] CbCr[6] CbCr[5] CbCr[4] CbCr[3] CbCr[2] CbCr[1] CbCr[0] YCbCr 4 : 2 : 2 ITU656
Table 3.
Internal assignment Internal port VP[11] VP[10] VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] VP[1] VP[0]
The device can swap and invert, in the event of a little endian stream, the incoming video data using I2C-bus registers VIP_CNTRL_0, VIP_CNTRL_1 and VIP_CNTRL_2 (page 00h) to match the expectation of the video processing block. Table 4 shows the behavior of SWAP_A[2:0] of VIP_CNTRL_0 register, whose function is to map the 4 MSBs VP[23:20] to the incoming video port.
TDA19989_1
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 February 2010
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
Table 4.
Video input swap to VP[23:20] SWAP_A[2:0] Internal assignment selector value Internal RGB YCbCr port 4:4:4 VP[23] VP[22] VP[21] VP[20] VP[23] VP[22] VP[21] VP[20] VP[23] VP[22] VP[21] VP[20] VP[23] VP[22] VP[21] VP[20] VP[23] VP[22] VP[21] VP[20] VP[23] VP[22] VP[21] VP[20] G[7] G[6] G[5] G[4] G[7] G[6] G[5] G[4] G[7] G[6] G[5] G[4] G[7] G[6] G[5] G[4] G[7] G[6] G[5] G[4] G[7] G[6] G[5] G[4] Y[7] Y[6] Y[5] Y[4] Y[7] Y[6] Y[5] Y[4] Y[7] Y[6] Y[5] Y[4] Y[7] Y[6] Y[5] Y[4] Y[7] Y[6] Y[5] Y[4] Y[7] Y[6] Y[5] Y[4]
External assignment Pin number F3 F2 F1 G1 G2 G3 H2 H3 C3 C2 D3 D2 D1 E1 E2 E3 A4 B4 A3 B3 A2 B2 B1 C1 Pin name VPC[6] VPC[5] VPC[4]
YCbCr 4 : 2 : 2 semi-planar Y0[11] Y0[10] Y0[9] Y0[8] Y0[11] Y0[10] Y0[9] Y0[8] Y0[11] Y0[10] Y0[9] Y0[8] Y0[11] Y0[10] Y0[9] Y0[8] Y0[11] Y0[10] Y0[9] Y0[8] Y0[11] Y0[10] Y0[9] Y0[8] Y1[11] Y1[10] Y1[9] Y1[8] Y1[11] Y1[10] Y1[9] Y1[8] Y1[11] Y1[10] Y1[9] Y1[8] Y1[11] Y1[10] Y1[9] Y1[8] Y1[11] Y1[10] Y1[9] Y1[8] Y1[11] Y1[10] Y1[9] Y1[8]
YCbCr 4 : 2 : 2 ITU656 Cb[11] Cb[10] Cb[9] Cb[8] Cb[11] Cb[10] Cb[9] Cb[8] Cb[11] Cb[10] Cb[9] Cb[8] Cb[11] Cb[10] Cb[9] Cb[8] Cb[11] Cb[10] Cb[9] Cb[8] Cb[11] Cb[10] Cb[9] Cb[8] Y0[11] Y0[10] Y0[9] Y0[8] Y0[11] Y0[10] Y0[9] Y0[8] Y0[11] Y0[10] Y0[9] Y0[8] Y0[11] Y0[10] Y0[9] Y0[8] Y0[11] Y0[10] Y0[9] Y0[8] Y0[11] Y0[10] Y0[9] Y0[8] Cr[11] Cr[10] Cr[9] Cr[8] Cr[11] Cr[10] Cr[9] Cr[8] Cr[11] Cr[10] Cr[9] Cr[8] Cr[11] Cr[10] Cr[9] Cr[8] Cr[11] Cr[10] Cr[9] Cr[8] Cr[11] Cr[10] Cr[9] Cr[8] Y1[11] Y1[10] Y1[9] Y1[8] Y1[11] Y1[10] Y1[9] Y1[8] Y1[11] Y1[10] Y1[9] Y1[8] Y1[11] Y1[10] Y1[9] Y1[8] Y1[11] Y1[10] Y1[9] Y1[8] Y1[11] Y1[10] Y1[9] Y1[8]
VPC[7] 000b
VPC[3] 001b VPC[2] VPC[1] VPC[0] VPB[7] 010b VPB[6] VPB[5] VPB[4] VPB[3] 011b VPB[2] VPB[1] VPB[0] VPA[7] 100b VPA[6] VPA[5] VPA[4] VPA[3] 101b VPA[2] VPA[1] VPA[0]
In the same way:
* * * * *
SWAP_B[2:0] is used to map incoming video port to the internal port VP[19:16]. SWAP_C[2:0] is used to map incoming video port to the internal port VP[15:12]. SWAP_D[2:0] is used to map incoming video port to the internal port VP[11:8]. SWAP_E[2:0] is used to map incoming video port to the internal port VP[7:4]. SWAP_F[2:0] is used to map incoming video port to the internal port VP[3:0].
The device expects to receive big endian incoming data. However, in cases where the input digital stream to the chip is little endian, the use of the mirror bit of the same register can help to re-order the input bits as described in Table 5.
TDA19989_1
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 February 2010
10 of 47
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
TDA19989 input/output capability Internal port VP[23] VP[22] VP[21] VP[20] To be mapped to VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] VPA[4] VPA[5] VPA[6] VPA[7] VPA[0] VPA[1] VPA[2] VPA[3]
Table 5. Bit setting
MIRR_A = 1 SWAP_A[2:0] = 1
MIRR_B = 1 SWAP_B[2:0] = 0
VP[19] VP[18] VP[17] VP[16]
MIRR_C = 1 SWAP_C[2:0] = 3
VP[15] VP[14] VP[13] VP[12]
MIRR_D = 1 SWAP_D[2:0] = 2
VP[11] VP[10] VP[9] VP[8]
MIRR_E = 1 SWAP_E[2:0] = 5
VP[7] VP[6] VP[5] VP[4]
MIRR_F = 1 SWAP_F[2:0] = 4
VP[3] VP[2] VP[1] VP[0]
When input ports are not used, it is possible to deactivate them via the I2C-bus with the appropriate set of registers ENA_VP_0, ENA_VP_1 and ENA_VP_2 on page 00h.
TDA19989_1
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 February 2010
11 of 47
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7.2.3 Input format mappings
Table 6 gives more information concerning input format supported.
Table 6. Color space RGB Inputs of video input formatter Format Channels 4 : 4 : 4 3 x 8-bit Sync type Rising Falling Double edge edge edge external X X embedded X X YCbCr 4 : 4 : 4 3 x 8-bit external X X embedded X X Transmission Max. pixel input format clock (MHz) ITU656-like X X embedded X X X up to 2 x 8-bit semi-planar external X X embedded X X ITU656-like ITU656-like ITU656-like ITU656-like ITU656-like SMPTE293M SMPTE293M SMPTE293M SMPTE293M 150 150 150 150 150 150 150 150 54.054 148.5 54.054 148.5 74.25 54.054 148.5 54.054 148.5 74.25 148.5 148.5 148.5 148.5 Max. input format 480p/576p 720p/1080i 480p/576p 720p/1080i Section 7.2.3.3 Section 7.2.3.2 Comments Reference Section 7.2.3.1
Preliminary data sheet Rev. 01 -- 15 February 2010 12 of 47
TDA19989_1 (c) NXP B.V. 2010. All rights reserved.
NXP Semiconductors
YCbCr 4 : 2 : 2 up to 1 x 12-bit ITU656-like
external
X
HDMI 1.3 transmitter with HDCP and CEC support
720p/1080i 480p/576p 720p/1080i 480p/576p 720p/1080i 720p/1080i 1080p 1080p 1080p 1080p
double edge
Section 7.2.3.4 Section 7.2.3.5
double edge
Section 7.2.3.6 Section 7.2.3.7 Section 7.2.3.8
TDA19989
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
7.2.3.1
RGB 4 : 4 : 4 external synchronization (rising edge)
Table 7. RGB (3 x 8-bit) external synchronization input (rising edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] RGB 4 : 4 : 4 B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] RGB 4 : 4 : 4 G[0] G[1] G[2] G[3] G[4] G[5] G[6] G[7] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] RGB 4 : 4 : 4 R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF RGB 4 : 4 : 4 used used used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF B0[7:0] B1[7:0] B2[7:0] B3[7:0] ... Bxxx[7:0] Bxxx[7:0]
VPA[0] to VPA[7]
VPB[0] to VPB[7]
G0[7:0]
G1[7:0]
G2[7:0]
G3[7:0]
...
Gxxx[7:0]
Gxxx[7:0]
VPC[0] to VPC[7]
R0[7:0]
R1[7:0]
R2[7:0]
R3[7:0]
...
Rxxx[7:0]
Rxxx[7:0]
001aag380
DE could also be generated from HSYNC/HREF and VSYNC/VREF.
Fig 5.
Pixel encoding RGB 4 : 4 : 4 external synchronization input (rising edge)
7.2.3.2
YCbCr 4 : 4 : 4 external synchronization (rising edge)
Table 8. YCbCr 4 : 4 : 4 (3 x 8-bit) external synchronization input (rising edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 4 : 4 Cb[0] Cb[1] Cb[2] Cb[3] Cb[4] Cb[5] Cb[6] Cb[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 4 : 4 Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCbCr 4 : 4 : 4 Cr[0] Cr[1] Cr[2] Cr[3] Cr[4] Cr[5] Cr[6] Cr[7] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 4 : 4 used used used
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Preliminary data sheet
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF VPA[0] to VPA[7] Cb0[7:0] Cb1[7:0] Cb2[7:0] Cb3[7:0] ... Cbxxx[7:0] Cbxxx[7:0]
VPB[0] to VPB[7]
Y0[7:0]
Y1[7:0]
Y2[7:0]
Y3[7:0]
...
Yxxx[7:0]
Yxxx[7:0]
VPC[0] to VPC[7]
Cr0[7:0]
Cr1[7:0]
Cr2[7:0]
Cr3[7:0]
...
Crxxx[7:0]
Crxxx[7:0]
001aai444
DE could also be generated from HSYNC/HREF and VSYNC/VREF.
Fig 6.
Pixel encoding YCbCr 4 : 4 : 4 external synchronization input (rising edge)
7.2.3.3
YCbCr 4 : 2 : 2 ITU656-like external synchronization (rising edge)
Table 9. YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] Cr[0] Cr[1] Cr[2] Cr[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] Cb[0] VPA[1] Cb[1] VPA[2] Cb[2] VPA[3] Cb[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] Cb[4] VPB[1] Cb[5] VPB[2] Cb[6] VPB[3] Cb[7] VPB[4] Cb[8] VPB[5] Cb[9] VPB[6] Cb[10] VPB[7] Cb[11] Control Pin VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 used used HSYNC/HREF used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF Cb0[11:0] Y0[11:0] Cr0[11:0] Y1[11:0] ... Crxxx[11:0] Yxxx[1:0]
001aai445
VPB[0] to VPB[7]; VPA[0] to VPA[3]
Fig 7.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising edge)
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
7.2.3.4
YCbCr 4 : 2 : 2 ITU656-like external synchronization (double edge)
Table 10. YCbCr 4 : 2 : 2 ITU656-like external synchronization input (double edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] Cr[0] Cr[1] Cr[2] Cr[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] Cb[0] VPA[1] Cb[1] VPA[2] Cb[2] VPA[3] Cb[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[11] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] Cb[4] VPB[1] Cb[5] VPB[2] Cb[6] VPB[3] Cb[7] VPB[4] Cb[8] VPB[5] Cb[9] VPB[7] Cb[11] Control Pin VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 used used HSYNC/HREF used
VPB[6] Cb[10] Y0[10]
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF Cb0[11:0] Y0[11:0] Cr0[11:0] Y1[11:0] ... Crxxx[11:0] Yxxx[1:0]
001aai446
VPB[0] to VPB[7]; VPA[0] to VPA[3]
Fig 8.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization input (double edge)
7.2.3.5
YCbCr 4 : 2 : 2 ITU656-like embedded synchronization (rising edge)
Table 11. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising edge) mappings Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] Cr[0] Cr[1] Cr[2] Cr[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] Cb[0] VPA[1] Cb[1] VPA[2] Cb[2] VPA[3] Cb[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] Cb[4] VPB[1] Cb[5] VPB[2] Cb[6] VPB[3] Cb[7] VPB[4] Cb[8] VPB[5] Cb[9] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 not used not used not used
VPB[6] Cb[10] Y0[10] VPB[7] Cb[11] Y0[11]
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
VCLK
VPB[0] to VPB[7]; VPA[0] to VPA[3]
Cb0[11:0]
Y0[11:0]
Cr0[11:0]
Y1[11:0]
...
Crxxx[11:0]
Yxxx[1:0]
001aai447
Fig 9.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising edge)
7.2.3.6
YCbCr 4 : 2 : 2 ITU656-like embedded synchronization (double edge)
Table 12. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (double edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] Cr[0] Cr[1] Cr[2] Cr[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] Cb[0] VPA[1] Cb[1] VPA[2] Cb[2] VPA[3] Cb[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] Cb[4] VPB[1] Cb[5] VPB[2] Cb[6] VPB[3] Cb[7] VPB[4] Cb[8] VPB[5] Cb[9] Control Pin YCbCr 4 : 2 : 2 HSYNC/HREF not used VSYNC/VREF not used DE/FREF not used
VPB[6] Cb[10] Y0[10] VPB[7] Cb[11] Y0[11]
VCLK
VPB[0] to VPB[7]; VPA[0] to VPA[3]
Cb0[11:0]
Y0[11:0]
Cr0[11:0]
Y1[11:0]
...
Crxxx[11:0]
Yxxx[1:0]
001aai448
Fig 10. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (double edge)
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
7.2.3.7
YCbCr 4 : 2 : 2 semi-planar external synchronization (rising edge)
Table 13. YCbCr 4 : 2 : 2 semi-planar external synchronization input (rising edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 2 : 2 semi-planar Y0[0] Y0[1] Y0[2] Y0[3] Cb[0] Cb[1] Cb[2] Cb[3] Y1[0] Y1[1] Y1[2] Y1[3] Cr[0] Cr[1] Cr[2] Cr[3] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 2 : 2 semi-planar Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCbCr 4 : 2 : 2 semi-planar Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Cb[10] Cb[11] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 used used used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF Y0[11:0] Y1[11:0] Y2[11:0] Y3[11:0] Y4[11:0] Y5[11:0] ...
VPB[0] to VPB[7]; VPA[0] to VPA[3] VPC[0] to VPC[7]; VPA[4] to VPA[7]
Cb0[11:0]
Cr0[11:0]
Cb2[11:0]
Cr2[11:O]
Cb4[11:0]
Cr4[11:0]
...
001aai449
Fig 11. Pixel encoding YCbCr 4 : 2 : 2 semi-planar external input synchronization (rising edge)
7.2.3.8
YCbCr 4 : 2 : 2 semi-planar embedded synchronization (rising edge)
Table 14. YCbCr 4 : 2 : 2 semi-planar embedded synchronization input (rising edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 2 : 2 semi-planar Y0[0] Y0[1] Y0[2] Y0[3] Cb[0] Cb[1] Cb[2] Cb[3] Y1[0] Y1[1] Y1[2] Y1[3] Cr[0] Cr[1] Cr[2] Cr[3] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 2 : 2 semi-planar Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCbCr 4 : 2 : 2 semi-planar Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Cb[10] Cb[11] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 not used not used not used
TDA19989_1
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Preliminary data sheet
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
VCLK
VPB[0] to VPB[7]; VPA[0] to VPA[3] VPC[0] to VPC[7]; VPA[4] to VPA[7]
Y0[11:0]
Y1[11:0]
Y2[11:0]
Y3[11:0]
Y4[11:0]
Y5[11:0]
...
Cb0[11:0]
Cr0[11:0]
Cb2[11:0]
Cr2[11:0]
Cb4[11:0]
Cr4[11:0]
...
001aai450
Fig 12. Pixel encoding YCbCr 4 : 2 : 2 semi-planar embedded synchronization input (rising edge)
7.2.4 Synchronization
TDA19989 can be synchronized with extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream or with external HSYNC/VSYNC inputs. 7.2.4.1 Timing extraction generator Synchronization signals can be extracted from Start Active Video (SAV) and End Active Video (EAV) in case of embedded synchronization in the data stream. Synchronization signals can be embedded in YCbCr 4 : 2 : 2 ITU656 (up to 1 x 12-bit) and YCbCr 4 : 2 : 2 semi-planar (up to 2 x 12-bit). 7.2.4.2 Data enable generator TDA19989 contains a Data Enable (DE) generator; this can generate an internal DE signal for a system which does not provide one.
7.3 Input and output video format
Due to the flexible video input formatter, TDA19989 can accept a large range of input formats. This flexibility allows TDA19989 to be compatible with the maximum possible number of MPEG decoders. Moreover, these input formats may be changed in many ways (color space converter, upsampler, downsampler) before it is transmitted across the HDMI link. Table 15 gives the possible inputs and outputs.
Table 15. Input Color space RGB Format 4:4:4 Channels 3 x 8-bit Use of color space converter, upsampler and downsampler Output Color space RGB YCbCr YCbCr YCbCr 4:4:4 3 x 8-bit RGB YCbCr YCbCr YCbCr 4:2:2 up to 1 x 12-bit RGB semi-planar YCbCr YCbCr Format 4:4:4 4:4:4 4:2:2 4:4:4 4:4:4 4:2:2 4:4:4 4:4:4 4:2:2 Channels 3 x 8-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit 2 x 12-bit
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
Use of color space converter, upsampler and downsampler ...continued Output Format 4:2:2 Channels Color space Format 4:4:4 4:4:4 4:2:2 Channels 3 x 8-bit 3 x 8-bit 2 x 12-bit up to 2 x 12-bit RGB semi-planar YCbCr YCbCr
Table 15. Input
Color space YCbCr
7.4 Upsampler
The incoming YCbCr 4 : 2 : 2 (2 x 12-bit) data stream format could be upsampled into YCbCr 4 : 4 : 4 (3 x 8-bit) data stream by repeating or linearly interpolating the chrominance pixels.
7.5 Color space converter
The color space converter is used to convert input video data from one type to another color space (e.g. RGB to YCbCr and YCbCr to RGB). This block can be bypassed and each coefficient is programmable via the I2C-bus register. C 11 C 12 C 13 Y Oin G Y Y\G Cr\R = C 21 C 22 C 23 x R Cr + Oin R Cr Cb\B C 31 C 32 C 33 B C b Oin B Cb Oout Y\G + Oout Cr\R Oout Cb\B
(1)
7.6 Gamut-related metadata
Gamut-related metadata is an enhanced colorimetry beyond the default standard with higher definition colorimetries. Profile P0 is supported, which means that only one packet per video field is sent. Color gamut boundary data are defined the standards:
* xvYCC601 (IEC 61966-2-4 - SD) (using YCbCr) * xvYCC709 (IEC 61966-2-4 - HD) (using YCbCr)
Remark: Gamut-related metadata is an HDMI 1.3a feature.
7.7 Downsampler
This block works only with YCbCr input format; the filters downsample the Cb and Cr signals by a factor of 2. A delay is added on the Y channel, which corresponds to the pipeline delay of the filters, to put the Y channel in phase with the Cb-Cr channel.
7.8 Audio input format
TDA19989 is compatible with the following audio features described in the HDMI 1.3 specification:
* S/PDIF * I2S-bus up to four stereo channels
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
TDA19989 can carry audio in I2S-bus format (one stereo to two stereo channels) or in S/PDIF format through one audio pin named AP1. S/PDIF or I2S-bus format can be selected via the I2C-bus. Only one audio format can be used at a time: either S/PDIF or I2S-bus. Table 16 shows the audio port allocation and Section 7.8.3 gives more details.
Table 16. Audio port AP0 AP1 AP2 AP3 ACLK Audio port configuration Input configuration S/PDIF S/PDIF input S/PDIF input MCLK SCK (I2S-bus clock) I2S-bus WS (word select) I2S-bus channel 0 I2S-bus channel 1
All audio ports are LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant. It is possible to deactivate unused ports via I2C-bus with ENA_AP register on page 00h for both audio and clock inputs.
7.8.1 S/PDIF
In this format TDA19989 supports 2-channel uncompressed PCM data (IEC 60958) layout 0, or compressed bit stream up to 8 multi channels (Dolby Digital, DTS, AC3 etc.) layout 1. Only one S/PDIF input can be used at the same time. The selection is done by register. TDA19989 is able to recover the original clock from the S/PDIF signal (no need of external clock). In addition, it can also use an external clock to decode the S/PDIF signal.
7.8.2 I2S-bus
There are 2 x I2S-bus stereo input, which enables 2 uncompressed audio channels to be carried. The I2S-bus input interface receives an I2S-bus signal including serial data, word select and serial clock. Typical waveforms for the I2S-bus signals at 64fs are given by Figure 13.
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
LEFT CHANNEL (n-1) word select fs
RIGHT CHANNEL (n-1)
LEFT CHANNEL (n)
RIGHT CHANNEL (n)
LEFT CHANNEL (n+1)
RIGHT CHANNEL (n+1)
MSB
24-bit audio sample word
LSB 0 0
0
audio clock 64fs
001aah029
a. Philips format.
LEFT CHANNEL (n-1) word select fs RIGHT CHANNEL (n-1) LEFT CHANNEL (n) RIGHT CHANNEL (n) LEFT CHANNEL (n+1) RIGHT CHANNEL (n+1)
MSB
24-bit audio sample word
LSB 0 0
0
audio clock 64fs
001aah030
b. Left justified format.
LEFT CHANNEL (n-1) word select fs RIGHT CHANNEL (n-1) LEFT CHANNEL (n) RIGHT CHANNEL (n) LEFT CHANNEL (n+1) RIGHT CHANNEL (n+1)
00
0
MSB
24-bit audio sample word
LSB
audio clock 64fs
001aah031
c. Right justified format. Fig 13. I2S-bus formats
The I2S-bus input interface can receive up to 24-bit wide audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency fs. Audio samples with a precision better than 24-bit are truncated to 24-bit. If the input clock has a frequency of 32fs, only 16-bit audio-samples can be received. In this case, the 8 LSBs will be set to 0. If the input clock has a frequency of 64fs and is left justified or Philips, the audio word is truncated to 24-bit format and other bits padded with zeros. If the input clock has a frequency of 64fs and is right justified, audio sample size has to be specified via software drivers. The serial data signal carries the serial baseband audio data, sample by sample left/right interleaved. The word select signal indicates whether left or right channel information is transferred over the serial data line.
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
7.8.3 Audio port internal assignment
The aim of the internal audio input assignment is to internally map any of the incoming data from the audio port AP1 or AP2 to I2S-bus channel 0 or S/PDIF internal ports by setting the appropriate I2C-bus register.
TDA19989
AUDIO INTERNAL PORTS I2C-BUS CHANNEL 0/1 AP1/AP2 S/PDIF
I2C-bus select
001aal259
Fig 14. Audio input swap to I2S-bus channel 0 or S/PDIF
7.9 Power management
TDA19989 HDMI and CEC cores can be independently powered down by the I2C-bus register. In Standby mode all activities are reduced by switching off all PLLs, HDMI and CEC cores and disconnecting the biasing structure of the output stage. TDA19989 has a very low power consumption, which is suitable for portable applications. Table 17 gives the typical power consumption of the device in different configurations.
Table 17. 400 W TDA19989 typical power consumption in different configurations Configuration Standby mode: Comment default configuration: after power-up; PLLs HDMI and CEC cores are OFF; can be switched ON via I2C-bus register no sink connected; CEC is OFF
Typical power
*
1.3 mW
I2C-bus
ON
Sleep mode without CEC:
*
1.8 mW
HDMI interruption (HPD, RxSense only) no sink connected; CEC is ON HDMI interruption (HPD, RxSense only) CEC interruption Video format 1080i Video input RGB 4 : 4 : 4 No CEC Video format 1080p all blocks enabled and running; 30 % activity on video input ports sink connected; CEC is OFF; 30 % activity on video input ports
Sleep mode with CEC:
* *
90 mW
Low power 1080i mode:
* * *
155 mW
Full speed mode:
*
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
7.10 Interrupt controller
Pin INT is used to alert the system microcontroller that a critical event concerning the HDMI or CEC has occurred. The software provided with the device read a status register (I2C-bus) to determine which block between HDMI and CEC has caused the interruption before processing it. Some of theses interrupts are maskable. The interrupt types are described in Table 18.
Table 18. HDCP Interruptions Interrupt name r0 pj sha-1 bstatus bcaps t0 security HPD RxSense Interrupt EDID CEC hpd rx_sense sw_intsoftware edid_block_rd cec_int Definition r0 = R'0 check done pj = P'j check fails V = V' check success bstatus available bcaps available HDCP goes to initial state HDCP encryption is off or blue screen removed transition on HPD input transition on RxSense test purpose (output an interrupt signal) CEC message received not maskable maskable maskable maskable Maskable feature maskable
Interrupt domain
EDID block read finished maskable not maskable
7.10.1 Hot plug/unplug detect
The hot plug detect (HPD) pin is 5 V input tolerant. The HPD signal, when asserted, tells the transmitter that the receiver is connected. When changing from LOW-to-HIGH, TDA19989 has to read the EDID of the receiver in order to select the video format that the receiver can handle.
7.10.2 Receiver sensitivity
TDA19989 has the capability to sense the receiver connectivity and working behavior. This feature (RxSense) detects the presence of the 50 pull-up resistor RT on the TMDS clock channel of the downstream side.
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
RECEIVER VCC
Rpu Rpu
HDMI cable
Vinp_rxs Vinn_rxs
35 k 35 k
pole = 80 ns
VDD 1.8 V power_down RXS_FIL
INTERNAL BANDGAP 0.935 V 4% I_transmit
TDA19989
001aal267
Fig 15.
Receiver sensitivity detection
As long as the receiver is connected to the transmitter and powered-up, bit RXS_FIL is set to logic 1. As soon as the cable is unplugged or receiver side powered off (assuming in this case that VCC is switched off), the RxSense generates an interrupt inside TDA19989, changing the value of bit RXS_FIL to logic 0 (See Table 19). This allows the application to stop sending unnecessary video content. This feature is very useful when the receiver recovers from an off-state and does not generate a HPD transition HIGH-to-LOW-to-HIGH. In this particular case, RxSense will generate an interrupt so that the chip restarts sending video.
Table 19. Receiver detection according to averaged terminal voltage bit RXS_FIL: receiver powered on 1 undefined 0 bit RXS_FIL: receiver powered off 0 0 0
Average voltage (Vinp_rxs + Vinn_rxs) / 2 V1V 0.8 V < V < 1 V V 0.8 V
Remark: According to the HDMI specification, only the HPD interrupt allows the application to read the EDID. The RxSense interrupt is not mandatory to initialize the EDID reading procedure.
TDA19989_1
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
7.11 HDCP processing
7.11.1 High-bandwidth digital content protection
TDA19989 contains an HDCP function, which encrypts the transmitted stream content (both video and audio). This function can be enabled and disabled via the I2C-bus. The keys can be stored internally in OTP non-volatile memory or can be loaded via the I2C-bus. As the keys are stored internally, the security is maximized. 7.11.1.1 Repeater function TDA19989 can be used in a repeater device according to the HDCP specification, Rev 1.3. TDA19989 is able to store the KSV list of a maximum of 127 devices in a register memory. 7.11.1.2 SHA-1 To deal with repeater, a SHA-1 calculation is performed by the transmitter and by the downstream repeater. For security purposes and in order to relieve the microcontroller, the SHA-1 has been implemented within TDA19989. This calculation is worked out after the transmitter has loaded the KSV list (see HDCP specification, Rev 1.3). If SHA-1 calculated by transmitter equals the SHA-1 calculated by repeater, then an interrupt is sent.
7.12 CEC
TDA19989 with its embedded CEC block provides a complete solution to enable Consumer Electronic Control (CEC) in product (DSC, DVC, PMP, UM PC). This eliminates the need of any additional device to handle this feature thus improving BOM (Bill Of Materials). CEC capability allows AV products (CEC enable) to communicate together over the home appliance network which could be controlled using only one remote control. The CEC block manages low level transactions (compliant to CEC timing specification) over the one bidirectional line. It translates CEC protocol in I2C-bus for the host processor and vice versa. It manages CEC message reception and transmission compliant to CEC protocol and provides the message to the system microcontroller (host processor). For power consumption optimization purpose CEC could be enable or disable through I2C-bus register. The following sections describe CEC:
* Features * Clocking scheme
7.12.1 Features
* * * * *
TDA19989_1
Receive and transmit CEC messages to host processor Supports multiple CEC logical addresses Supports CEC messages up to 16 bytes long Programmable retry count Comprehensive arbitration and collision handling
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
7.12.2 Clock
CEC clock must be running in Sleep mode (with CEC) to wake up TDA19989 using CEC specific message as described in "HDMI specification 1.3a". CEC module can be clocked using:
* External clock:
- 12 MHz crystal 1 %.
* Internal clock:
- FRO (Free Running Oscillator). FRO frequency varies and in the range from 12.64 MHz to 12.9 MHz. See Figure 16. CEC operates normally (i.e. matches the timing requested CEC specification) if and only if its clock frequency is set to 12 MHz.
TDA19989
CEC clock calibration module FRO DIVIDER CEC CLK 12 MHz I2C-bus INT I2C-bus CEC MODULE
HOST PROCESSOR
001aal265
Fig 16. Modules involved in CEC clock calibration process
Calibration procedure is completely handled by the software delivered together with the device, it has the following steps:
* Host processor set TDA19989 in calibration mode * Host processor generates a negative pulse of 10 ms 1 % on INT pin * Host processor deselects the calibration mode when it is completed, the chip is ready
to operate CEC clock calibration must be performed at each power-up and each time TDA19989 moves from Standby or Sleep (without CEC) state to normal operating mode. Non successful calibration will lead to CEC signal not matching timings specification; as a consequence, CEC will not be functional.
7.12.3 CEC interrupt
Pin INT is used by TDA19989 to warn the host processor that HDMI or CEC events (CEC message is available to read) have occurred. Software interrupt status register reads determine which block between HDMI or CEC has raised the interruption before processing it.
TDA19989_1
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
7.12.4 Power-On Reset (POR)
After power-up, TDA19989 is activated by internal reset from POR module. This is used to set TDA19989 to a known state.
7.12.5 Repeater function
TDA19989 can be used in a repeater device according to HDMI 1.3a.
7.13 HDMI core
7.13.1 Output TMDS buffers
7.13.1.1 Digitally controlled signal amplitude The TMDS signal output peak-to-peak voltage (Vswing) is programmable by the software using I2C-bus register vswing_crtl[3:0]. Vswing varies from 370 mV to 640 mV with 5 % accuracy in 18 mV steps according to the following formula: Vswing = 370 mV + 18 mV x vswing_ctrl[3:0] An external resistor (10 k 1 %) must be connected between pin EXT_SWING and analog ground.
7.13.2 Pixel repetition
To transmit video formats with pixel rates below 25 megasamples per second or to increase the number of audio sample packets in each frame, TDA19989 uses pixel repetition to increase the transmitted pixel clock (see Table 20).
Table 20. PR[3] 0 0 0 0 0 0 0 0 1 1 others Pixel repetition PR[2] 0 0 0 0 1 1 1 1 0 0 PR[1] 0 0 1 1 0 0 1 1 0 0 PR[0] 0 1 0 1 0 1 0 1 0 1 Pixel repetition factor no repetition: pixel sent once 2 times: pixel repeated once 3 times 4 times 5 times 6 times 7 times 8 times 9 times 10 times reserved
7.13.3 DDC-bus channel
The DDC-bus pins DSDA and DSCL are 5 V tolerant and can work at standard mode (100 kHz). The DDC-bus is used as a master interface when reading the EDID. When the device is power-off, DSDA and DSCL ports:
* become in high-impedance * can withstand 5 V from the sink
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
7.14 E-EDID
7.14.1 E-EDID reading
As a master interface for the EDID process, the DDC-bus is compliant with the I2C-bus specification and has the possibility of repeat/start condition to enable quick access to the EDID content, as well as the possibility of reading a large EDID (with the use of segment pointer). TDA19989 has a whole I2C-bus page (page 09h) dedicated to the EDID where one block (128 bytes) can be stored. The block can be read by the system microcontroller to determine the supported video and audio format of the downstream site. Remark: When the block is read by TDA19989, it generates an interrupt to warn the main processor that the chip is ready to transmit the content. Once the content is read out by the main processor, it can allow other blocks to be read if required.
7.14.2 HDMI and DVI receiver discrimination
This information is located in the E-EDID receiver part, in the `vendor-specific data block' within the first CEA EDID timing extension. If the 24-bit IEEE Registration Identifier contains the value 00 0C03h, then the receiver will support HDMI, otherwise the device will be treated as a DVI device. However, even through TDA19989 have directly access to that information, it is the task of the host processor to ask to switch from DVI to HDMI mode.
TDA19989_1
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HDMI 1.3 transmitter with HDCP and CEC support
8. I2C-bus interface and register definitions
8.1 I2C-bus protocol
The I2C-bus pins CSDA and CSCL are 1.8 V and 3.3 V tolerant. Both Fast mode (400 kHz) and Standard mode (100 kHz) are supported. The registers of TDA19989 can be accessed via the I2C-bus. All registers are R/W except for those which are confidential. HDMI and CEC cores I2C-bus addresses are given in Table 21 and Table 22.
Table 21. A6 1 Table 22. A6 0 HDMI core I2C-bus address A5 1 A4 1 A3 0 A2 0 A1 0 A0 0 R/W 0/1
HDMI core address
CEC core I2C-bus address A5 1 A4 1 A3 0 A2 1 A1 0 A0 0 R/W 0/1
CEC core address
For read access, the master writes the address of TDA19989 HDMI or CEC core, and the subaddress to access the specific register and then the data.
123456789123456789123456789 CSCL CSDA SLAVE ADDRESS SUBADDRESS DATA STOP
001aal419
Fig 17. I2C-bus access
8.2 Memory page management
The I2C-bus memory is split into several pages for HDMI core only, and the selection between pages is made with common register CURPAGE_ADR. It is only necessary to write in this register once to change the current page. So multiple read or write operations in the same page need a write register CURPAGE_ADR once at the beginning. The following memory pages are available for TDA19989:
* * * * * * *
TDA19989_1
Page 00h: general control Page 02h: PLL settings Page 09h: EDID control page Page 10h: information frames and packets Page 11h: audio settings and content info packets Page 12h: HDCP and OTP' Page 13h: gamut-related metadata packets
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HDMI 1.3 transmitter with HDCP and CEC support
The CEC core does not need memory page mechanism due to its reduced number of registers.
8.3 ID version
The ID version readable via I2C-bus is defined by the concatenation of VERSION_MSB and VERSION registers. The ID version value is 212h.
8.4 Clock stretching
Clock stretching pauses a transaction by holding the CSCL line LOW. The transaction cannot continue until the line is released HIGH again. For example: on the byte level, a device may be able to receive bytes of data at a fast rate, but needs more time to store a received byte or prepare another byte to be transmitted. Slaves can then hold the CSCL line LOW after reception and acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer; see Table 31. Clock stretching must be supported by I2C-bus master especially when CEC feature of TDA19989 is used. If CEC feature of TDA19989 is not used, I2C-bus master does not need to support clock stretching.
9. Input format
In Table 23 the port VPA has been mapped to Cb (YCbCr space)/B (RGB space), VPB has been mapped to Y (YCbCr space)/G (RGB space) and VPC has been mapped to Cr (YCbCr space)/R (RGB space).
Table 23. Input format L: recommend tield to LOW voltage, e.g. ground Input pins Video port A VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5]
TDA19989_1
Signal
RGB 4:4:4
YCbCr 4:4:4 Cb[0] Cb[1] Cb[2] Cb[3] Cb[4] Cb[5] Cb[6] Cb[7] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] 4 : 2 : 2 (semi-planar) Y0[0] Y0[1] Y0[2] Y0[3] Cb[0] Cb[1] Cb[2] Cb[3] Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y1[0] Y1[1] Y1[2] Y1[3] Cr[0] Cr[1] Cr[2] Cr[3] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] 4 : 2 : 2 (ITU 656-like) Cb[0] Cb[1] Cb[2] Cb[3] L L L L Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Y0[0] Y0[1] Y0[2] Y0[3] L L L L Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Cr[0] Cr[1] Cr[2] Cr[3] L L L L Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Y1[0] Y1[1] Y1[2] Y1[3] L L L L Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9]
30 of 47
Cb[0]/B[0] Cb[1]/B[1] Cb[2]/B[2] Cb[3]/B[3] Cb[4]/B[4] Cb[5]/B[5] Cb[6]/B[6] Cb[7]/B[7] Y[0]/G[0] Y[1]/G[1] Y[2]/G[2] Y[3]/G[3] Y[4]/G[4] Y[5]/G[5]
B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] G[0] G[1] G[2] G[3] G[4] G[5]
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Preliminary data sheet
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
Table 23. Input format ...continued L: recommend tield to LOW voltage, e.g. ground Input pins VPB[6] VPB[7] Video port C VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] Cr[0]/R[0] Cr[1]/R[1] Cr[2]/R[2] Cr[3]/R[3] Cr[4]/R[4] Cr[5]/R[5] Cr[6]/R[6] Cr[7]/R[7] R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] Cr[0] Cr[1] Cr[2] Cr[3] Cr[4] Cr[5] Cr[6] Cr[7] Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Cb[10] Cb[11] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L Signal Y[6]/G[6] Y[7]/G[7] RGB 4:4:4 G[6] G[7] YCbCr 4:4:4 Y[6] Y[7] 4 : 2 : 2 (semi-planar) Y0[10] Y0[11] Y1[10] Y1[11] 4 : 2 : 2 (ITU 656-like) Cb[10] Cb[11] Y0[10] Y0[11] Cr[10] Cr[11] Y1[10] Y1[11]
9.1 Timing parameters for video supported
TDA19989 supports all EIA/CEA-861B standards and ATSC video input formats.
Table 24. Timing parameters for EIA/CEA-861B Format V frequency (Hz) H total V total H frequency (kHz) Pixel frequency (MHz) 25.175 27.000 74.175 74.175 27.000 27.000 27.000 54.000 54.000 54.000 54.000 148.350 25.200 27.027 74.250 74.250 27.027 27.027 27.027 Pixel repetition
EIA/CEA-861b Video code 59.94 Hz systems 1 (VGA) 2, 3 4 5 6, 7 (NTSC) 8, 9 8, 9 10, 11 12, 13 12, 13 14, 15 16 60 Hz systems 1 (VGA) 2, 3 4 5 6, 7 (NTSC) 8, 9 8, 9
TDA19989_1
640 x 480p 720 x 480p 1280 x 720p 1920 x 1080i 1440 x 480i 1440 x 240p 1440 x 240p 2880 x 480i 2880 x 240p 2880 x 240p 1440 x 480p 1920 x 1080p 640 x 480p 720 x 480p 1280 x 720p 1920 x 1080i 1440 x 480i 1440 x 240p 1440 x 240p
59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 60.000 60.000 60.000 60.000 60.000 60.000 60.000 60.000
800 858 1650 2200 1716 1716 1716 3452 3452 3452 1716 2200 800 858 1650 2200 1716 1716 1716
525 525 750 1125 525 262 263 525 262 263 525 1125 525 525 750 1125 525 262 263
31.469 31.469 44.955 33.716 15.734 15.734 15.734 15.734 15.734 15.734 31.469 67.432 31.500 31.500 45.000 33.750 15.750 15.750 15.750
1 1 1 1 2 2 2 4[1] 4[1] 4[1] 2 1 1 1 1 1 2 2 2
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HDMI 1.3 transmitter with HDCP and CEC support
Table 24.
Timing parameters for EIA/CEA-861B ...continued Format V frequency (Hz) 60.000 60.000 60.000 60.000 60.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 23.976 24 25 29.97 30 H total V total H frequency (kHz) 15.750 15.750 15.750 31.500 67.500 31.250 37.500 28.125 15.625 15.625 15.625 15.625 15.625 15.625 15.625 15.625 31.250 56.250 26.973 27 28.125 33.716 33.75 Pixel frequency (MHz) 54.054 54.054 54.054 54.054 148.50 27.000 74.250 74.250 27.000 27.000 27.000 27.000 54.000 54.000 54.000 54.000 54.000 148.50 74.175824 74.25 74.25 74.175824 74.25 Pixel repetition 4[1] 4[1] 4[1] 2 1 1 1 1 2 2 2 2 4[1] 4[1] 4[1] 4 2 1 1 1 1 1 1
EIA/CEA-861b Video code 10, 11 12, 13 12, 13 14, 15 16 50 Hz systems 17, 18 19 20 21, 22 (PAL) 23, 24 23, 24 23, 24 25, 26 27, 28 27, 28 27, 28 29, 30 31 Various systems 32 32 33 34 34
[1]
2880 x 480i 2880 x 240p 2880 x 240p 1440 x 480p 1920 x 1080p 720 x 576p 1280 x 720p 1920 x 1080i 1440 x 576i 1440 x 288p 1440 x 288p 1440 x 288p 2880 x 576i 2880 x 288p 2880 x 288p 720 x 288p 1440 x 576p 1920 x 1080p 1920 x 1080p 1920 x 1080p 1920 x 1080p 1920 x 1080p 1920 x 1080p
3452 3452 3452 1716 2200 864 1980 2640 1728 1728 1728 1728 3456 3456 3456 3456 1728 2640 2750 2750 2640 2200 2200
525 262 263 525 1125 625 750 1125 625 312 313 314 625 312 313 314 625 1125 1125 1125 1125 1125 1125
Format can also be defined with a repetition factor of up to 10.
Table 25. Standard
Timing parameters for ATSC DTV standards, which are not defined in EIA/CEA-861B Format V frequency (Hz) 30.000 29.970 25.000 23.976 H total V total H frequency (kHz) 22.500 22.478 18.750 17.982 Pixel frequency (MHz) 74.250 74.175 74.250 74.175 Pixel repetition 1 1 1 1
SMPTE-296M SMPTE-296M SMPTE-296M SMPTE-296M
1280 x 720p 1280 x 720p 1280 x 720p 1280 x 720p
3300 3300 3960 4125
750 750 750 750
TDA19989_1
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
9.2 Timing parameters for PC standards supported
TDA19989 can support all major PC Standards up to 150 MHz.
Table 26. Standard Timing parameters for PC standards below 150 MHz Format 640 x 350p 640 x 400p 720 x 400p 0.31M3 VGA 640 x 480p 640 x 480p 640 x 480p 640 x 480p 0.48M3 SVGA 800 x 600p 800 x 600p 800 x 600p 800 x 600p 800 x 600p 0.48M3-R 0.41M9 0.79M3 XGA 800 x 600p 848 x 480p 1024 x 768p 1024 x 768p 1024 x 768p 1024 x 768p 1024 x 768i 0.79M3-R XGA 1.00M3 0.98M9-R 0.98M9 1024 x 768p 1152 x 864p 1280 x 768p 1280 x 768p 1280 x 768p 1280 x 768p 1280 x 768p 1.02MA-R 1.02MA 1280 x 800p 1280 x 800p 1280 x 800p 1280 x 800p 1280 x 800p 1.23M3 1.31M4 SXGA 1.04M9 1.04M9-R
TDA19989_1
V frequency (Hz) 85.080 85.080 85.039 59.940 72.809 75.000 85.008 56.250 60.317 72.188 75.000 85.061 119.972 60.000 60.004 70.069 75.029 84.997 86.957 119.989 75.000 59.995 119.798 59.870 74.893 84.837 59.910 119.909 59.810 74.934 84.880 60.000 85.002 60.020 75.025 60.015 119.967
H total 832 832 936 800 832 840 832 1024 1056 1040 1056 1048 960 1088 1344 1328 1312 1376 1264 1184 1600 1440 1440 1664 1696 1712 1440 1440 1680 1696 1712 1800 1728 1688 1688 1792 1520
V total 445 445 446 525 520 500 509 625 628 666 625 631 636 517 806 806 800 808 817 813 900 790 813 798 805 809 823 847 831 838 843 1000 1011 1066 1066 795 813
H frequency (kHz) 37.861 37.861 37.927 31.469 37.861 37.500 43.269 35.156 37.879 48.077 46.875 53.674 76.302 31.020 48.363 56.476 60.023 68.677 35.522 97.551 67.500 47.396 97.396 47.776 60.289 68.633 49.306 101.563 49.702 62.795 71.554 60.000 85.938 63.981 79.976 47.712 97.533
Pixel frequency Pixel (MHz) repetition 31.500 31.500 35.500 25.175 31.500 31.500 36.000 36.000 40.000 50.000 49.500 56.250 73.250 33.750 65.000 75.000 78.750 94.500 44.900 115.500 108.000 68.250 140.250 79.500 102.250 117.500 71.000 146.250 83.500 106.500 122.500 108.000 148.500 108.000 135.000 85.500 148.250 (c) NXP B.V. 2010. All rights reserved.
1280 x 960p 1280 x 960p 1280 x 1024p 1280 x 1024p 1360 x 768p 1360 x 768p
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
Table 26. Standard 1.47M3-R 1.47M3 1.29MA-R 1.29MA 1.76MA-R 1.76MA
Timing parameters for PC standards below 150 MHz ...continued Format 1400 x 1050p 1400 x 1050p 1440 x 900p 1440 x 900p 1440 x 900p 1680 x 1050p 1680 x 1050p V frequency (Hz) 59.948 59.978 59.901 59.887 74.984 59.883 59.954 H total 1560 1864 1600 1904 1936 1840 2240 V total 1080 1089 926 934 942 1080 1089 H frequency (kHz) 64.744 65.317 55.469 55.935 70.635 64.674 65.290 Pixel frequency Pixel (MHz) repetition 101.000 121.750 88.750 106.500 136.750 119.000 146.250 -
10. Limiting values
Table 27. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA(TMDS)(1V8) VDDA(PLL)(1V8) VDDA(1V8) VDDD(IO)(1V8) VDDDC VDD VESD Parameter TMDS analog supply voltage (1.8 V) PLL analog supply voltage (1.8 V) analog supply voltage (1.8 V) I/O digital supply voltage (1.8 V) core digital supply voltage supply voltage difference electrostatic discharge voltage EIA/JESD22-A114 (HBM) EIA/JESD22-C101-C (FCDM)
[1] [2] On TMDS outputs. It withstands class III of JEDEC classification.
[1] [2]
Conditions
Min -0.5 -0.5 -0.5 -0.5 -0.5 -2 -2500 1000
Max +2.5 +2.5 +2.5 +2.5 +2.5 +2 -
Unit V V V V V V V
+2500 V
11. Thermal characteristics
Table 28. Symbol Rth(j-a) Rth(j-c) Tstg Tamb Tj Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case storage temperature ambient temperature junction temperature Conditions in free air; JEDEC 4L board Min -20 Typ 56.9 15.1 Max +150 +85 +125 Unit K/W K/W C C C
TDA19989_1
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HDMI 1.3 transmitter with HDCP and CEC support
12. Static characteristics
Table 29. Supplies Tamb = -20 C to +85 C; without HDCP; unless otherwise specified. Symbol VDDDC VDDA(TMDS)(1V8) VDDA(PLL)(1V8) VDDA(1V8) VDDD(IO)(1V8) IDDD(1V8) IDDA(sum)(1V8) IDDA(PLL)(1V8) IDDD(IO)(1V8) IDDDC(1V8) Pcons Parameter core digital supply voltage TMDS analog supply voltage (1.8 V) PLL analog supply voltage (1.8 V) analog supply voltage (1.8 V) I/O digital supply voltage (1.8 V) digital supply current (1.8 V) sum analog supply current (1.8 V) PLL analog supply current (1.8 V) input/output digital supply current (1.8 V) core digital supply current (1.8 V) power consumption Sleep mode with CEC Sleep mode without CEC Standby mode Ptot total power dissipation
[4] [5] [2]
Conditions
[1]
Min 1.7 1.7 1.7 1.7 1.7 30 15 7 50 25 -
Typ 1.8 1.8 1.8 1.8 1.8 42 19 8 40 60 32 155 90 1.8 1.3 400 265 220
Max 1.9 1.9 1.9 1.9 1.9 60 22 9 70 40 180 105 4 2 600 300 260
Unit V V V V V A mA mA A mA mA mW mW mW mW W mW mW
PLL analog and serializer
IDDA(sum)(1V8) = IDDA(TMDS)(1V8) + IDDA(1V8)
[2]
[2] [2]
[2] [3] [2] [3]
[1] [2] [3] [4] [5]
see Table 6. Input format: 1080p, any color space; output format: 1080p any color space: 30 % activity on video input ports. Input format: 1080i YCbCr 4 : 2 : 2; output format: YCbCr 4 : 2 : 2; CEC feature disable: 30 % activity on video input ports. Same as Table note [2] with TMDS output current added. Same as Table note [3] with TMDS output current added.
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HDMI 1.3 transmitter with HDCP and CEC support
Table 30. Digital inputs and outputs Tamb = -20 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Not 5 V tolerant CMOS 1.8 V and CMOS 3.3 V tolerant digital input pins HSYNC, VSYNC, APn, ACLK, VPA[n], VPB[n], VPC[n], VCLK, DE VIL VIH IIL IIH Ci VIL VIH Ci VIL VIH VOL VOL VIL VIH VOL VIL VIH CEC VOL VOH VIL VIH Vhys(i) VO(dif)
[1] [2]
LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance LOW-level input voltage HIGH-level input voltage input capacitance LOW-level input voltage HIGH-level input voltage
-
0 1.4 -2 -2 -
4.5 4.5 0.27 505
0.75 +2 +2 0.8 0.85 0.4 0.4 0.6 5.5 0.4 0.6 5.5 0.4 3.6 0.60 3.6 600
V V A A pF V V pF V V V V V V V V V V V V V V mV
5 V tolerant input pin HPD 0 2 DSCL[1] 0 0 1.4 input/output pins CSCL, CSDA[1] 0 0 1.4 0 2.5 0 2.5
[2]
CMOS 1.8 V and CMOS 3.3 V tolerant digital input/output pin INT 0 1.4 0
LOW-level output voltage CL = 10 pF; IOL = 2 mA LOW-level output voltage LOW-level input voltage HIGH-level input voltage I2C-bus LOW-level output voltage LOW-level input voltage HIGH-level input voltage input/output[2] pin LOW-level output voltage HIGH-level output voltage LOW-level input voltage HIGH-level input voltage input hysteresis voltage differential output voltage REXT_SWING = 10 k 1 %
5 V tolerant master bus: DDC-bus pins DSDA,
1.8 V to 3.3 V tolerant slave bus:
400
TMDS output pins: TX0-, TX0+, TX1-, TX1+, TX2-, TX2+, TXC- and TXC+
See Section 7.1 and refer to the I2C-bus specification version 2.1 (document order number 9398 393 40011). For information, input hysteresis is normally supplied by the microprocessor input circuit: in this circumstance, external hysteresis circuitry is not needed.
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HDMI 1.3 transmitter with HDCP and CEC support
13. Dynamic characteristics
Table 31. Timing characteristics Tamb = -20 C to +85 C; unless otherwise specified. Symbol fclk(max) tsu(D) th(D) clk fclk fSCL Ci I2C-bus: fSCL tstretch CEC tr tf fclk(max) fclk(max)
[1] [2] [3]
Parameter maximum clock frequency data input set-up time data input hold time clock duty cycle clock frequency SCL frequency capacitance for each I/O pin
Conditions see Figure 18 and 19 see Figure 18 and 19 positive edge CEC Standard mode bus[2]
[1]
Min 1.5 1 30 -
Typ 50 12 7 80 -
Max 148.5 70 100 100 400 50 2 148.5 1.485
Unit MHz ns ns % MHz kHz pF kHz kHz s s s MHz GHz
Clock input: pin VCLK
DDC-bus: pins DSDA, DSCL (5 V tolerant) master bus[2]
pins CSCL, CSDA (5 V tolerant) slave SCL frequency stretch time rise time fall time maximum clock frequency maximum clock frequency
Standard mode Fast mode CEC 10 % to 90 % 10 % to 90 % on the TMDS link
-
input/output[3]
TMDS output pins: TXC- and TXC+ TMDS output pins: TX0-, TX0+, TX1-, TX1+, TX2- and TX2+
clk = tclk(H) / (tclk(H) + tclk(L)). See Section 7.1 and refer to the I2C-bus specification version 2.1 (document order number 9398 393 40011). For details about CEC electrical specification, see HDMI 1.3a specification.
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Preliminary data sheet
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
EDGE = 0 VCLK VPA[0] to VPA[7] VPB[0] to VPB[7] VPC[0] to VPC[7] DE, HSYNC, VSYNC
tsu(D) EDGE = 1
th(D)
VCLK VPA[0] to VPA[7] VPB[0] to VPB[7] VPC[0] to VPC[7] DE, HSYNC, VSYNC
tsu(D)
th(D)
data is not allowed to change in this period data can change to meet the minimum set-up and hold time requirement
001aah035
Fig 18. Set-up and hold time definition diagram for single-edge clock mode
VCLK VPA[0] to VPA[7] VPB[0] to VPB[7] VPC[0] to VPC[7] DE, HSYNC, VSYNC tsu(D) th(D) tsu(D) th(D)
data is not allowed to change in this period data can change to meet the minimum set-up and hold time requirement
001aah036
Fig 19. Set-up and hold time definition diagram for double-edge clock mode
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Preliminary data sheet
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
14. Application information
14.1 Transmitter connection with external world
Figure 20 and Figure 21 refer to a simple receiver application. However, TDA19989 can be part of a repeater application as described in "HDMI specification 1.3a".
TRANSMITTER SIDE I2C-bus
DOWNSTREAM SIDE
video 24-bit MASTER sync MAIN PROCESSOR audio
TMDS channel 0 I2C-BUS SLAVE TMDS channel 1 TMDS channel 2
TDA19989
EXTERNAL CLOCK 12 MHz DDC-BUS MASTER
TMDS clock HPD DDC-bus channel
HDMI RECEIVER/ REPEATER
SLAVE CEC
001aal261
Fig 20. Connecting TDA19989 transmitter using external clock source
TRANSMITTER SIDE I2C-bus
DOWNSTREAM SIDE
video 24-bit MASTER sync MAIN PROCESSOR audio
TMDS channel 0 I2C-BUS SLAVE TMDS channel 1 TMDS channel 2
TDA19989
TMDS clock HPD
HDMI RECEIVER/ REPEATER
DDC-BUS MASTER
DDC-bus channel SLAVE CEC
001aal262
Fig 21. Connecting TDA19989 transmitter using internal FRO for CEC
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Preliminary data sheet
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HDMI 1.3 transmitter with HDCP and CEC support
15. Package outline
TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls SOT962-3
D
B
A
ball A1 index area
A2 E A
A1
detail X
e1 1/2 e e b v w
M M
CAB C
C y1 C y
H
e
G F E
e2
D
1/2 e
C B A
ball A1 index area
1
2
3
4
5
6
7
8
X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A 1.10 0.95 0.85 A1 0.30 0.25 0.20 A2 0.80 0.70 0.65 b 0.35 0.30 0.25 D 4.6 4.5 4.4 E 4.6 4.5 4.4 e 0.5 e1 3.5 e2 3.5 v 0.15 w 0.05 y 0.08 y1 0.1
OUTLINE VERSION SOT962-3
REFERENCES IEC --JEDEC --JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 08-05-26 08-06-18
Fig 22. Package outline SOT962-3 (TFBGA64)
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HDMI 1.3 transmitter with HDCP and CEC support
16. Abbreviations
Table 32. Acronym AC3 ACP ACR ATSC AV BOM CEA CEC CTS/N DDC DDR DE DSC DTS DTV DVC DVD DVI EAV EDID E-EDID EIA FCDM FIFO FREF FRO HBM HDCP HDMI HPD HREF HSYNC LSB LV-CMOS MPEG MSB OTP PC PCB
TDA19989_1
Abbreviations Description Active Coding-3 Audio Content Protection Audio Clock Recovery Advanced Television Systems Committee Audio Video Bill Of Materials Consumer Electronics Association Consumer Electronics Control Clock Time Stamp integer divider Display Data Channel Double Data Rate Data Enable Digital Still Camera Digital Transmission System Desk Top Video Digital Video Camera Digital Versatile Disc Digital Visual Interface End Active Video Extended Display Identification Data Enhanced Extended Display Identification Data Electronic Industries Alliance Field Charged Device Model First In, First Out Field REFerence Free Running Oscillator Human Body Model High-bandwidth Digital Content Protection High-Definition Multimedia Interface Hot Plug Detection Horizontal REFerence Horizontal SYNChronization Least Significant Bit Low Voltage Complementary Metal-Oxide Semiconductor Moving Picture Experts Group Most Significant Bit One Time Programming Personal Computer Printed Circuit Board
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Preliminary data sheet
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HDMI 1.3 transmitter with HDCP and CEC support
Abbreviations ...continued Description Pulse Code Modulation Phase-Locked Loop Portable Multimedia Player Power-On Reset R = red, G = green, B = blue Start Active Video Single Data Rate Society of Motion Picture and Television Engineers Sony/Philips Digital Interface Set-Top Box Transition Minimized Differential Signalling Ultra-Mobile Personal Computer Ultra Extended Graphics Array Vertical Horizontal REFerence Vertical REFerence Vertical SYNChronization Y = luminance, Cb = Chroma component blue, Cr = Chroma component red Word Select
Table 32. Acronym PCM PLL PMP POR RGB SAV SDR SMPTE S/PDIF STB TMDS UM PC UXGA60 VHREF VREF VSYNC YCbCr WS
17. Revision history
Table 33. Revision history Release date 20100215 Data sheet status Preliminary data sheet Change notice Supersedes Document ID TDA19989_1
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Preliminary data sheet
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TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products -- Unless the data sheet of an NXP Semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the
(c) NXP B.V. 2010. All rights reserved.
18.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
TDA19989_1
Preliminary data sheet
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
18.4 Licenses
Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: admin@hdmi.org.
18.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Preliminary data sheet
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
20. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Internal assignment . . . . . . . . . . . . . . . . . . . . . .8 Video input swap to VP[23:20] . . . . . . . . . . . . .10 TDA19989 input/output capability . . . . . . . . . . 11 Inputs of video input formatter . . . . . . . . . . . . .12 RGB (3 8-bit) external synchronization input (rising edge) mapping . . . . . . . . . . . . . . . . . . .13 YCbCr 4 : 4 : 4 (3 8-bit) external synchronization input (rising edge) mapping . . . . . . . . . . . . . . .13 YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising edge) mapping . .14 YCbCr 4 : 2 : 2 ITU656-like external synchronization input (double edge) mapping .15 YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising edge) mappings .15 YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (double edge) mapping .16 YCbCr 4 : 2 : 2 semi-planar external synchronization input (rising edge) mapping . .17 YCbCr 4 : 2 : 2 semi-planar embedded synchronization input (rising edge) mapping . .17 Use of color space converter, upsampler and downsampler . . . . . . . . . . . . . . . . . . . . . . . . . .18 Audio port configuration . . . . . . . . . . . . . . . . . .20 TDA19989 typical power consumption in different configurations . . . . . . . . . . . . . . . . . .22 Interruptions . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Receiver detection according to averaged terminal voltage . . . . . . . . . . . . . . . . . . . . . . . .24 Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . .27 HDMI core I2C-bus address . . . . . . . . . . . . . . .29 CEC core I2C-bus address . . . . . . . . . . . . . . .29 Input format . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Timing parameters for EIA/CEA-861B . . . . . . .31 Timing parameters for ATSC DTV standards, which are not defined in EIA/CEA-861B . . . . .32 Timing parameters for PC standards below 150 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .34 Thermal characteristics. . . . . . . . . . . . . . . . . . .34 Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Digital inputs and outputs . . . . . . . . . . . . . . . .36 Timing characteristics . . . . . . . . . . . . . . . . . . .37 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .41 Revision history . . . . . . . . . . . . . . . . . . . . . . . .42
continued >>
TDA19989_1
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Preliminary data sheet
Rev. 01 -- 15 February 2010
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NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
21. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. TDA19989 high-level block diagram . . . . . . . . . . .2 TDA19989 Block diagram . . . . . . . . . . . . . . . . . . .4 Pin configuration (TFBGA64). . . . . . . . . . . . . . . . .5 Internal assignment of VP[23:0]. . . . . . . . . . . . . . .8 Pixel encoding RGB 4 : 4 : 4 external synchronization input (rising edge) . . . . . . . . . . .13 Pixel encoding YCbCr 4 : 4 : 4 external synchronization input (rising edge) . . . . . . . . . . .14 Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising edge) . . . .14 Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization input (double edge) . . .15 Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising edge) . .16 Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (double edge) .16 Pixel encoding YCbCr 4 : 2 : 2 semi-planar external input synchronization (rising edge) . . . .17 Pixel encoding YCbCr 4 : 2 : 2 semi-planar embedded synchronization input (rising edge) . .18 I2S-bus formats . . . . . . . . . . . . . . . . . . . . . . . . . .21 Audio input swap to I2S-bus channel 0 or S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Receiver sensitivity detection . . . . . . . . . . . . . . .24 Modules involved in CEC clock calibration process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 I2C-bus access. . . . . . . . . . . . . . . . . . . . . . . . . . .29 Set-up and hold time definition diagram for single-edge clock mode . . . . . . . . . . . . . . . . . . . .38 Set-up and hold time definition diagram for double-edge clock mode . . . . . . . . . . . . . . . . . . .38 Connecting TDA19989 transmitter using external clock source . . . . . . . . . . . . . . . . . . . . . .39 Connecting TDA19989 transmitter using internal FRO for CEC. . . . . . . . . . . . . . . . . . . . . .39 Package outline SOT962-3 (TFBGA64) . . . . . . .40
continued >>
TDA19989_1
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Preliminary data sheet
Rev. 01 -- 15 February 2010
46 of 47
NXP Semiconductors
TDA19989
HDMI 1.3 transmitter with HDCP and CEC support
22. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.3.1 7.2.3.2 7.2.3.3 7.2.3.4 7.2.3.5 7.2.3.6 7.2.3.7 7.2.3.8 7.2.4 7.2.4.1 7.2.4.2 7.3 7.4 7.5 7.6 7.7 7.8 7.8.1 7.8.2 7.8.3 7.9 7.10 7.10.1 7.10.2 7.11 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Video input formatter . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Internal assignment . . . . . . . . . . . . . . . . . . . . . 8 Input format mappings . . . . . . . . . . . . . . . . . . 12 RGB 4 : 4 : 4 external synchronization (rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 13 YCbCr 4 : 4 : 4 external synchronization (rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 13 YCbCr 4 : 2 : 2 ITU656-like external synchronization (rising edge) . . . . . . . . . . . . . 14 YCbCr 4 : 2 : 2 ITU656-like external synchronization (double edge) . . . . . . . . . . . . 15 YCbCr 4 : 2 : 2 ITU656-like embedded synchronization (rising edge) . . . . . . . . . . . . . 15 YCbCr 4 : 2 : 2 ITU656-like embedded synchronization (double edge) . . . . . . . . . . . . 16 YCbCr 4 : 2 : 2 semi-planar external synchronization (rising edge) . . . . . . . . . . . . . 17 YCbCr 4 : 2 : 2 semi-planar embedded synchronization (rising edge) . . . . . . . . . . . . . 17 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 18 Timing extraction generator . . . . . . . . . . . . . . 18 Data enable generator . . . . . . . . . . . . . . . . . . 18 Input and output video format . . . . . . . . . . . . . 18 Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Color space converter. . . . . . . . . . . . . . . . . . . 19 Gamut-related metadata. . . . . . . . . . . . . . . . . 19 Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 19 Audio input format . . . . . . . . . . . . . . . . . . . . . 19 S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Audio port internal assignment . . . . . . . . . . . . 22 Power management . . . . . . . . . . . . . . . . . . . . 22 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 23 Hot plug/unplug detect . . . . . . . . . . . . . . . . . . 23 Receiver sensitivity . . . . . . . . . . . . . . . . . . . . . 23 HDCP processing . . . . . . . . . . . . . . . . . . . . . . 25 7.11.1 High-bandwidth digital content protection . . . 7.11.1.1 Repeater function. . . . . . . . . . . . . . . . . . . . . . 7.11.1.2 SHA-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12 CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12.2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12.3 CEC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 7.12.4 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 7.12.5 Repeater function. . . . . . . . . . . . . . . . . . . . . . 7.13 HDMI core . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.13.1 Output TMDS buffers . . . . . . . . . . . . . . . . . . . 7.13.1.1 Digitally controlled signal amplitude . . . . . . . . 7.13.2 Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 7.13.3 DDC-bus channel. . . . . . . . . . . . . . . . . . . . . . 7.14 E-EDID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.14.1 E-EDID reading . . . . . . . . . . . . . . . . . . . . . . . 7.14.2 HDMI and DVI receiver discrimination . . . . . . 8 I2C-bus interface and register definitions. . . 8.1 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 8.2 Memory page management . . . . . . . . . . . . . . 8.3 ID version. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Clock stretching . . . . . . . . . . . . . . . . . . . . . . . 9 Input format . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Timing parameters for video supported . . . . . 9.2 Timing parameters for PC standards supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal characteristics . . . . . . . . . . . . . . . . . 12 Static characteristics . . . . . . . . . . . . . . . . . . . 13 Dynamic characteristics. . . . . . . . . . . . . . . . . 14 Application information . . . . . . . . . . . . . . . . . 14.1 Transmitter connection with external world . . 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 20 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 25 25 26 26 27 27 27 27 27 27 27 28 28 28 29 29 29 30 30 30 31 33 34 34 35 37 39 39 40 41 42 43 43 43 43 44 44 44 45 46 47
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 February 2010 Document identifier: TDA19989_1

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