View HB52R329E22-A6F_4534869.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HB52R329E22-F
EO
Description Features
256 MB Registered SDRAM DIMM 32-Mword x 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M x 4 Components) PC100 SDRAM
E0112H10 (1st edition) (Previous ADE-203-1046A (Z)) Feb. 28, 2001
The HB 52R 329E22 belongs to 8-byte DI MM (D ual In- line Memory Module) fa mily, and has bee n deve loped as an optimiz ed main memory solution for 8-byte proc essor applica tions. The HB 52R 329E22 is a 16M x 72 x 2-ba nk S ynchronous Dyna mic R AM Module, mounted 36 piec es of 64-Mbit S DRA M (H M5264405F TB ) sea led in TC P pac kage and 1 piec e of P LL cloc k drive r (2510) , 3 piec es re giste r drive r (162835) , 1 piec e of inver te r and 1 piec e of ser ia l EEP RO M (2- kbit EEP RO M) for P rese nce De te ct (P D). An outline of the HB 52R 329E22 is 168-pin socke t type pac kage (dua l lea d out). The ref ore, the HB 52R 329E22 make s high density mounting possible without surf ace mount tec hnology. The HB 52R 329E22 provide s common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board. Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects.
* Fully compatible with : JEDEC standard outline registered 8-byte DIMM : Intel PCB Reference design (Rev. 1.2) * 168-pin socket type package (dual lead out) Outline: 133.37 mm (length) x 38.10 mm (Height) x 4.80 mm (Thickness) Lead pitch: 1.27 mm * 3.3 V power supply * Clock frequency: 100 MHz (max) * LVTTL interface * Data bus width: x 72 ECC * Single pulsed RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length: 1/2/4/8/full page * 2 variations of burst sequence Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
This Product became EOL in October, 2005.
Pr
uc od t
HB52R329E22-F
Sequential (BL = 1/2/4/8/full page) Interleave (BL = 1/2/4/8) Programmable CE latency : 3/4 (HB52R329E22-A6F) : 4 (HB52R329E22-B6F) Byte control by DQMB Refresh cycles: 4096 refresh cycles/64 ms 2 variations of refresh Auto refresh Self refresh Full page burst length capability Sequential burst Burst stop capability
EO
* * * * *
Ordering Information
Type No. HB52R329E22-A6F HB52R329E22-B6F
L
Frequency 100 MHz 100 MHz 3/4 4
CE latency
Package 168-pin dual lead out socket type
Contact pad Gold
Data Sheet No. E0112H10 2
Pr
uc od t
HB52R329E22-F
Pin Arrangement
EO
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
L
VSS S2 NC NC VCC NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS
Pin name
Pin No. 85 86 87 88 89
Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC
Pin No. 127 128 129 130 131 132 133 134 135 136 137
Pin name VSS CKE0 S3 DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS
DQMB2 DQMB3
Data Sheet No. E0112H10 3
Pr
90 91 92 93 94 95 96 VSS 97 98 99 100 101 102 VCC 103 104 105 CB4 106 CB5 107 VSS 108 109 NC NC 110 VCC
DQ36
DQ37 DQ38 DQ39 DQ40
uc od
138 DQ41 DQ42 DQ43 DQ44 139 140 141 142 DQ48 DQ49 DQ50 DQ51 VCC DQ45 143 144 DQ52 DQ46 DQ47 145 146 NC NC 147 REGE VSS 148 149 DQ53 150 151 DQ54 DQ55 VSS
t
152
HB52R329E22-F
Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name W Pin No. 69 70 71 72 Pin name DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS Pin No. 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 Pin name CE DQMB4 DQMB5 S1 RE VSS A1 A3 A5 A7 A9 A13 (BA0) A11 VCC CK1 NC Pin No. 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin name DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VCC
EO
DQMB0 DQMB1 S0 NC VSS A0 A2 A4 A6 A8 73 74 75 76 77 78 79 A10 (AP) 80 81 A12 (BA1) VCC VCC CK0 82 83 84 4
L
CK2 NC WP SDA SCL VCC
Data Sheet No. E0112H10
Pr
126
uc od t
HB52R329E22-F
Pin Description
EO
Pin name A0 to A11 A13/A12 DQ0 to DQ63 CB0 to CB7 S0 to S3 RE CE W DQMB0 to DQMB7 CK0 to CK3 CKE0 WP REGE* SDA SCL SA0 to SA2 VCC VSS NC Note:
1
Function Address input Row address Column address Bank select address Data input/output Check bit (Data input/output) Chip select input Row enable (RAS) input Column enable (CAS) input Write enable input A0 to A11 A0 to A9 BA0/BA1
1. REGE is the Register Enable pin which permits the DIMM to operate in "buffered" mode and "registered" mode. To conform to this specification, mother boards must pull this pin to high state ("registerd" mode).
L
Byte data mask Clock input Clock enable input
Data Sheet No. E0112H10 5
Pr
Write protect for serial PD Register enable Clock input for serial PD Serial address input Ground No connection
Data input/output for serial PD
Primary positive power supply
uc od t
HB52R329E22-F
Serial PD Matrix*1
EO
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes used by module manufacturer Total SPD memory size Memory type Number of banks Module data width SDRAM cycle time (highest CE latency) 10 ns 10 11 12 Module configuration type Refresh rate/type 13 14 15 SDRAM width 16 17 SDRAM device attributes: Burst lengths supported 18 SDRAM device attributes: CE latency (-A6F) (-B6F) 19 SDRAM device attributes: S latency 6
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 80 08 04 0C 0A 02 48 00 01 A0 128 256 byte SDRAM 12 10 2 72 bit 0 (+) LVTTL CL = 3
Number of row addresses bits Number of column addresses bits
Module data width (continued) Module interface signal levels
SDRAM access from Clock (highest CE latency) 6 ns
Error checking SDRAM width
SDRAM device attributes: 0 minimum clock delay for back-toback random column addresses 1 0
SDRAM device attributes: number of banks on SDRAM device
L
1 0 0 1 0 0 0 0 0
Data Sheet No. E0112H10
Pr
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
0
0
60
*3
1 0
0 0
02 80
ECC Normal (15.625 s) Self refresh 16M x 4 x4
uc od
0 0 0 0 0 1 04 04 01 1 CLK 1 0 1 0 8F 04 1, 2, 4, 8, full page 4 1 0 06 2, 3 0 0 04 3 0 1 01 0
t
HB52R329E22-F
Byte No. Function described 20 SDRAM device attributes: W latency SDRAM device attributes Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 01 16 0E A0 0 Registered VCC 10% CL = 2
EO
21 22 23 SDRAM device attributes: General SDRAM cycle time (2nd highest CE latency) (-A6F) 10 ns (-B6F) Undefined 24 (-B6F) Undefined 25 SDRAM cycle time (3rd highest CE latency) Undefined 26 27 28 29 30 31 32 33 34 35 RE to CE delay min Minimum RE pulse width 36 to 61 Superset information 62 63 SPD data revision code (-B6F) 64
0 0
0 1
0 1
0 0
0 0
0 0
0 0
0 0
00 60 CL = 2
SDRAM access from Clock (2nd highest CE latency) (-A6F) 6 ns
SDRAM access from Clock (3rd highest CE latency) Undefined
Minimum row precharge time Row active to row active min
Density of each bank on module 0 Address and command signal input setup time Address and command signal input hold time Data signal input setup time Data signal input hold time 0 0 0 0 0 0 0
Checksum for bytes 0 to 62 (-A6F)
Manufacturer's JEDEC ID code
65 to 71 Manufacturer's JEDEC ID code
L
0 0 0 0 0 0 0 0 0 0
0
0 0
0 0
0 0
0 0
0 0
0 0
00 00
0
0
0
0
0
0
0
0
00
Data Sheet No. E0112H10 7
Pr
0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0
0 0
0 0 0 0 0 0 0 0 0 0 0 1
14 14 14 32 20 20 10 20 10 00 12 37
20 ns 20 ns 20 ns 50 ns 2 bank 128M byte 2 ns*3 1 ns*3 2 ns*3 1 ns*3
0 1 0 0 0 0 0 0 1 1
uc od
Future use Rev. 1.2A 55 0 1 35 53 1 0 1 0 07 00 HITACHI
t
HB52R329E22-F
Byte No. Function described 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Manufacturing location Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments x 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 1 0 0 1 0 0 0 1 0 0 0 1 x 0 0 1 1 0 1 1 1 0 1 1 1 0 x 0 0 1 1 1 1 1 1 0 1 1 0 0 x 1 0 0 0 0 0 0 1 0 0 0 1 0 x 0 0 1 0 0 0 0 0 1 0 0 1 0 x 0 1 0 1 1 1 1 0 0 1 1 0 0 1 x 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 xx 48 42 35 32 52 33 32 39 45 32 32 2D 41 42 36 46 20 20 20 * 4 (ASCII8bit code) H B 5 2 R 3 2 9 E 2 2 -- A B 6 F (Space) (Space) (Space)
EO
Manufacturer's part (-B6F) 86 87 88 89 90 91 92 93 94 Revision code Revision code Manufacturing date Manufacturing date 95 to 98 Assembly serial number 126 127 (-B6F) 8
Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number
Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (-A6F)
Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number
99 t o 125 Manufacturer specific data Intel specification frequency Intel specification CE# latency support (-A6F)
L
0 0 0 0 0 0 0 0 x x *7 -- 0 1 1
Data Sheet No. E0112H10
Pr
1 0 0 0 0 0 1 0 0 0 0 0 x x 1 0 1 1 1 1 1 x x 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 x x 0 0 x x 0 0 x x -- 1 0 -- 1 0 -- -- -- 0 0 0 0 1 1 0 0 0 0 1
1 1 0 0 0
uc od
0 0 x x 0 0 x x 30 20 xx xx Initial (Space) Year code (BCD)*5 Week code (BCD) * 5 -- -- -- *6 0 1 0 1 64 87 100 MHz CL = 2, 3 0 1 85 CL = 3
t
HB52R329E22-F
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on Intel specification (Rev.1.2A). 2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119. 3. Byte10, 32 through 35 are component spec. 4. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 5. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is "Binary Coded Decimal". 6. All bits of 99 through 125 are not defined ("1" or "0"). 7. Bytes 95 through 98 are assembly serial number.
EO
L
Data Sheet No. E0112H10 9
Pr uc od t
HB52R329E22-F
Block Diagram
EO
RS0 RS1 RDQMB0 4 10 DQ0 to DQ3 4 10 DQ4 to DQ7 RDQMB1 4 10 DQ8 to DQ11 4 DQ12 to DQ15 10 CB0 to CB3 RS2 RS3 RDQMB2 4 DQ16 to DQ19 10 4 10 DQ20 to DQ23 RDQMB3 10 4 10 4 DQ24 to DQ27 4 DQ28 to DQ31 10 S0, S1, S2, S3 DQMB0 to DQMB7 BA0 to BA1 A0 to A11 RE CE CKE0 W VCC REGE PLL CK 10k R E G I S T E R
RDQMB4 DQMB CS I/O0 to I/O3 DQMB CS 4 DQ32 to DQ35 10 I/O0 to I/O3 DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
D0
D18
D9
D27
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS 4 DQ36 to DQ39 RDQMB5 10 I/O0 to I/O3
DQMB CS I/O0 to I/O3
D1
D19
D10
D28
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS 4 DQ40 to DQ43 10 I/O0 to I/O3
DQMB CS I/O0 to I/O3
D2
D20
D11
D29
SA0 SA1 SA2 VSS Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
L
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS 4 DQ44 to DQ47 10 I/O0 to I/O3 DQMB CB4 to CB7 4 10 I/O0 to I/O3 CS
DQMB CS I/O0 to I/O3 DQMB
D3
D21
D12
D30
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
D4
D22
D13
I/O0 to I/O3
D31
CS
DQMB CS I/O0 to I/O3
D5
DQMB CS I/O0 to I/O3
D6
DQMB CS I/O0 to I/O3
D7
DQMB CS I/O0 to I/O3
D8
RS0, RS1, RS2, RS3 RDQMB0 to RDQMB7 RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35 CK1 RA0 to RA11 -> A0 to A11: SDRAMs D0 to D35 to CK3 RRAS -> RAS: SDRAMs D0 to D35 RCAS -> CAS: SDRAMs D0 to D35 VCC RCKE0 -> CKE: SDRAMs D0 to D35 0.0022 F x 25 pcs RW -> WE: SDRAMs D0 to D35 VSS Serial PD SCL SCL SDA SDA WP
Data Sheet No. E0112H10 10
Pr
RDQMB6 DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
D23
4
10
D14
D32
DQ48 to DQ51
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
D24
DQ52 to DQ55
4
10
D15
D33
RDQMB7
uc od
DQMB CS I/O0 to I/O3 DQMB CS I/O0 to I/O3 4 10
DQMB CS I/O0 to I/O3
D25
D16
D34
DQ56 to DQ59
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3 10
DQMB CS I/O0 to I/O3
D26
4
10
D17
D35
DQ60 to DQ63
CK0
PLL 12 pF
CK : SDRAMs (D0 to D35) Register
10
VSS
12 pF
VCC (D0 to D35, U0)
0.22 F x 19 pcs VSS (D0 to D35, U0)
U0
A0 A1
A2
* D0 to D35: HM5264405 PLL: 2510 Register: 162835 U0: 2k bit EEPROM
47 k
t
HB52R329E22-F
Absolute Maximum Ratings
EO
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to VSS Parameter Supply voltage Input high voltage Input low voltage Ambient illuminance Notes: 1. 2. 3. 4. 5.
Symbol VT VCC Iout PT Topr Tstg
Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 18.0 0 to +55 -50 to +100
Unit V V mA W C C
Note 1 1
DC Operating Conditions (Ta = 0 to +55C)
Symbol VCC VSS Min 3.0 0 Max 3.6 0 Unit V V V V lx Notes 1, 2 3 1, 4 1, 5
All voltage referred to VSS The supply voltage with all VCC and VCCQ pins must be on the same level. The supply voltage with all VSS and VSS Q pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC. VIL (min) = VCC - 2.0 V for pulse width 3 ns at VSS .
L
VIH VIL --
Data Sheet No. E0112H10 11
Pr
2.0 0 VCC 0.8 -- 100
uc od t
HB52R329E22-F
VIL/VIH Clamp (Component characteristics)
I (mA)
EO
Minimum VIL Clamp Current
VIL (V) -2 -1.8 -1.6 -1.4 -1.2 -1 -0.9 -0.8 -0.6 -0.4 -0.2 0 0 -5 -10 -15 -20 -25 -30 -35 -2 12
This SDRAM component has VIL and VIH clamp for CK, CKE, S, DQMB and DQ pins.
I (mA) -32 -25 -19 -13 -8 -4 -2 -0.6 0
L
-1.5
Data Sheet No. E0112H10
Pr
0 0 0 -1 VIL (V)
-0.5
0
uc od t
HB52R329E22-F
Minimum VIH Clamp Current (referred to VCC)
I (mA)
EO
VIH (V) VCC + 2 VCC + 1.8 VCC + 1.6 VCC + 1.4 VCC + 1.2 VCC + 1 VCC + 0.8 VCC + 0.6
I (mA) 10 8 5.5 3.5 1.5 0.3 0 0 0 0 0
L
10 8 6 4 2 0 VCC + 0 VCC + 0.5
VCC + 0.4 VCC + 0.2 VCC + 0
Data Sheet No. E0112H10 13
Pr
VCC + 1
uc od
VCC + 1.5 VCC + 2 VIH (V)
t
HB52R329E22-F
IOL/IOH Characteristics (Component characteristics)
IOL (mA)
EO
Output Low Current (I OL)
Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 250 200 150 100 50 0 0 0.5 14
I OL Min (mA) 0 27 41 51 58 70 72
I OL Max (mA) 0 71 108 134 151 188 194 203 209 212 220 223
L
75 77 77 80 81 1 1.5 2 2.5 Vout (V) Data Sheet No. E0112H10
Pr
uc od
min max 3 3.5
t
HB52R329E22-F
Output High Current (I OH ) (Ta = 0 to 55C, VCC = 3.0 V to 3.45 V, VSS = 0 V)
IOH (mA)
EO
Vout (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1.4 1 0 0 0 0.5 -100 -200 -300 -400 -500 -600
I OH Min (mA) -- -- 0 -21 -34 -59 -67 -73 -78 -81 -89 -93
I OH Max (mA) -3 -28 -75 -130 -154 -197 -227 -248 -270 -285 -345 -503
L
1 1.5 2 2.5 Vout (V) Data Sheet No. E0112H10
Pr
3
3.5
uc od
min max
t
15
HB52R329E22-F
DC Characteristics (Ta = 0 to 55C, VCC = 3.3 V 0.3 V, VSS = 0 V)
EO
Parameter Operating current (CE latency = 3) (CE latency = 4) I CC1 I CC1 Standby current in non power down Active standby current in non power down Burst operating current (CE latency = 3) (CE latency = 4) Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage I CC4 I CC4 I CC5 I CC6 I LI I LO VOH VOL 16
HB52R329E22 -A6F/B6F Min -- -- -- -- -- -- -- Max 2315 2315 803 767 1271 839 1415 Unit mA mA mA mA mA mA mA CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, S = VIH, t CK = 12 ns CKE = VIL, t CK = 12 ns CKE, S = VIH, t CK = 12 ns t CK = min, BL = 4 6 7 4 1, 2, 6 1, 2, 4 1, 2, 5 Test conditions Burst length = 1 t RC = min Notes 1, 2, 3
Symbol
Standby current in power down I CC2P Standby current in power down I CC2PS (input signal stable) I CC2N
Active standby current in power I CC3P down
Notes: 1. I CC depends on output load condition when the device is selected. I CC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK operating current. 7. After power down mode, no CK operating current. 8. After self refresh mode set, self refresh current.
L
I CC3N -- -- -- -- -10 -10 2.4 --
Data Sheet No. E0112H10
Pr
2315 2315 3125 731 mA mA mA mA 10 10 -- A A V V 0.4
t RC = min
3 8
VIH VCC - 0.2 V VIL 0.2 V
0 Vin VCC
uc od
0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA
t
HB52R329E22-F
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
EO
Parameter Input capacitance (Address) Input capacitance (RE, CE, W) Input capacitance (CKE) Input capacitance (S) Input capacitance (CK) Input capacitance (DQMB) Input/Output capacitance (DQ) Notes: 1. 2. 3. 4.
Symbol CI1 CI2 CI3 CI4 CI5 CI6 CI/O1
Max 25 25 45 20 45 20 25
Unit pF pF pF pF pF pF pF
Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested.
L
Data Sheet No. E0112H10 17
Pr uc od t
HB52R329E22-F
AC Characteristics (Ta = 0 to 55C, VCC = 3.3 V 0.3 V, VSS = 0 V)
EO
Parameter System clock cycle time (CE latency = 3) (CE latency = 4) CK high pulse width CK low pulse width Access time from CK (CE latency = 3) (CE latency = 4) Data-out hold time CK to Data-out low impedance CK to Data-out high impedance Data-in setup time Data in hold time Address setup time Address hold time CKE setup time CKE setup time for power down exit CKE hold time Command setup time Command hold time Active to precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period 18
HB52R329E22 -A6F/B6F Symbol t CK t CK t CKH t CKL t AC t AC PC100 Symbol Tclk Tclk Tch Tcl Tac Tac Toh Min 10 10 4 4 -- -- 2.1 1.1 -- Max -- -- -- -- 7.5 7.5 -- -- 7.5 -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 1 1 1 1 1 1, 2 Notes 1
Ref/Active to Ref/Active command period t RC t RAS t RCD t RP t DPL t RRD tT t REF
L
t OH t LZ t HZ t DS t DH t AS t AH t CES t CESP t CEH t CS t CH
Data Sheet No. E0112H10
Pr
Tsi 2.9 Thi Tsi 3.4 2.6 Thi Tsi 3.0 2.6 Tpde Thi Tsi 2.6 3.0 2.6 Thi 3.0 70 50 20 20 10 20 Trc Tras Trcd Trp Tdpl Trrd 1 --
uc od
120000 ns 1 -- -- -- -- 5 ns ns ns ns ns 1 1 1 1 64 ms
t
HB52R329E22-F
Notes: 1. 2. 3. 4. 5. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is CL = 50 pF. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CK rising edge except power down exit command.
EO
Test Conditions
2.4 V 0.4 V
* Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures * Ambient illuminance: Under 100 lx
L
2.0 V 0.8 V t
T
input
DQ CL
Data Sheet No. E0112H10 19
Pr
tT
uc od t
HB52R329E22-F
Relationship Between Frequency and Minimum Latency
EO
Parameter Frequency (MHz) tCK (ns) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input (CE latency = 4) (CE latency = 4) Write command to data in latency DQMB to data in DQMB to data out CKE to CK disable Register set to active command S to command disable Power down exit to command input 20
HB52R329E22 -A6F/B6F 100 PC100 Symbol Symbol 10 I RCD I RC I RAS I RP Tdpl 2 7 5 2 1 2 Tsrx Tdal 2 3 7 Notes 1 = [IRAS + I RP] 1 1 1 1 1 2 = [IDPL + I RP] = [IRC] 3
Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank)
Write recovery or data-in to precharge command (same I DPL bank) Active command to active command (different bank) I RRD I SREX I APW
Precharge command to high impedance (CE latency = 3)
Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CE latency = 3)
Column command to column command
L
Data Sheet No. E0112H10
Pr
I SEC I HZP I HZP Troh Troh I APR I EP I EP I CCD Tccd I WCD I DID Tdwd Tdqm Tdqz Tcke I DOD I CLE I RSA Tmrd I CDD I PEC
3 4 0
uc od
-2 -3 1 1 1 3 2 1 0 1
t
HB52R329E22-F
HB52R329E22 Parameter -A6F/B6F 100 PC100 Symbol Symbol 10 I BSR I BSR I BSH I BSH I BSW 2 3 3 4 1 Notes
EO
Frequency (MHz) tCK (ns) Burst stop to output valid data hold (CE latency = 3) (CE latency = 4) (CE latency = 4) Burst stop to write data ignore
Burst stop to output high impedance (CE latency = 3)
Notes: 1. I RCD to I RRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP]
L
Data Sheet No. E0112H10 21
Pr uc od t
HB52R329E22-F
Pin Functions
EO
22
CK0 to CK3 (in pu t p in ): C K is the master cloc k input to this pin. The other input signals ar e re fe rre d at C K rising edge. S0 to S3 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE , CE an d W (in pu t p in s): Although these pin name s ar e the same as those of conve ntiona l DR AMs, they func tion in a diffe re nt wa y. The se pins def ine oper ation commands (r ea d, wr ite , etc .) depe nding on the combination of their voltage levels. For details, refer to the command operation section. A0 to A11 (in pu t p in s): R ow addr ess (A X0 to AX11) is dete rmined by A0 to A11 leve l at the bank ac tive command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or wr ite command cyc le C K rising edge . And this column addr ess bec omes burst ac ce ss start addr ess. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But whe n A10 = Low at the pre cha rge command cyc le, only the bank that is sele cted by A12/A13 (B A) is precharged. A12/A13 (input pin): A12/A13 are bank select signal (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If A12 is Low and A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If C KE is Low, the next C K rising edge is invalid. This pin is used for powe r-dow n and cloc k suspend modes. DQMB 0 to DQMB 7 (in pu t p in s) : R ea d oper ation: If DQMB is High, the output buff er bec omes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Wr ite oper ation: If DQMB is High, the pre vious data is held (the new data is not wr itten) . If DQMB is Low, the data is written. DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.
L
Data Sheet No. E0112H10
Pr
uc od t
HB52R329E22-F
Command Operation
EO
Command Truth Table
Command Ignore command No operation Burst stop in full page Read with auto-precharge Write with auto-precharge Precharge select bank Precharge all bank Refresh Mode register set
The SDRAM module recognizes the following commands specified by the S, RE, CE, W and address pins.
CKE Symbol DESL NOP BST n-1 n H H H H H H H H x x x x x x x x x x x S H L L L L L L L L L RE x H H H H H H L L L CE x H H L L L L H H H L L W x H L H H L L H L L H L A0 A12/A13 A10 to A11 x x x V V V V V V x x V x x x L H L H V L H x V x x x V V V V V x x x V
Column address and read command
Column address and write command
Row address strobe and bank active
Note: H: VIH. L: VIL. x: VIH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (S is High), the SDRAM module ignore command input at the clock. However, the internal status is held.
No op erat ion [N OP] : This command is not an exe cution command. Howe ver , the interna l oper ations continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page) and is illegal otherwise. When data input/output is completed for a full page of data, it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address and the bank select address (BA). After the read operation, the output buffer becomes High-Z.
Re ad with au to-p re ch arge [R EAD A] : This command automatica lly per forms a pre cha rge oper ation af ter a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.
L
READ READ A WRIT WRIT A ACTV PRE PALL MRS
Data Sheet No. E0112H10 23
Pr
H H REF/SELF H H V L L L L
uc od t
HB52R329E22-F
Colu mn ad dr ess str obe an d wr it e com man d [WR IT ]: This command starts a wr ite oper ation. Whe n the burst wr ite mode is sele cted, the column addr ess and the bank sele ct addr ess (B A) bec ome the burst wr ite start addr ess. Whe n the single wr ite mode is sele cte d, data is only wr itten to the loca tion spec ified by the column address and the bank select address (BA). Writ e with au to-p re ch arge [WR IT A] : This command automatica lly per forms a pre cha rge oper ation af ter a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal. Row ad dr ess str obe an d b ank act ivate [A CTV ]: This command ac tiva tes the bank that is sele cted by B ank sele ct addr ess (B A) and dete rmines the row addr ess (A X0 to AX11) . Whe n A12 and A13 ar e Low, bank 0 is activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2 is activated. When A12 and A13 are High, bank 3 is activated. Pr ech arge sele cte d b ank [PR E] : This command starts pre cha rge oper ation for the bank sele cted by B ank sele ct addr ess (B A) . If A12 and A13 ar e Low, bank 0 is sele cted. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mod e re gister set [M RS ]: The S DRA M module has a mode re giste r that def ines how it oper ates. The mode register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode re giste r conf iguration. Af te r powe r on, the conte nts of the mode re giste r ar e undef ined, exe cute the mode register set command to set up the mode register.
EO
24
L
Data Sheet No. E0112H10
Pr
uc od t
HB52R329E22-F
DQMB Truth Table
EO
Command Write enable/output enable Write inhibit/output disable Note: H: VIH. L: VIL. x: VIH or VIL. Write: I DID is needed. Read: I DOD is needed.
CKE Symbol ENB MASK n-1 H H n x x DQMB L H
The SDRAM module can mask input/output data by means of DQMB. During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the other hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is held (the new data is not wr itten) . De sir ed data ca n be maske d during burst re ad or burst wr ite by setting DQMB . For details, refer to the DQMB control section of the SDRAM module operating instructions.
L
Pr
CKE n-1 n S H L x x x L L L H H H L L H H H L L L L H L H L L H H L L H L H H
CKE Truth Table
Current state Active Any Clock suspend Idle Idle Idle
Command
RE x x x
CE x x x
W x x x
Address x x x
Clock suspend mode entry Clock suspend Clock suspend mode exit
uc od
L L H x L L H x H x x x H x x x H x x x x x x x x x H H H H H H
Auto-refresh command (REF) Self-refresh entry (SELF) Power down entry
Self refresh
Self refresh exit (SELFX)
Power down
Power down exit
Note: H: VIH. L: VIL. x: VIH or VIL.
Clock susp en d mod e en tr y: The S DRA M module ente rs cloc k suspend mode fr om ac tive mode by setting C KE to Low. If command is input in the cloc k suspend mode entr y cyc le, the command is valid. The cloc k suspend mode changes depending on the current status (1 clock before) as shown below.
t
25
Data Sheet No. E0112H10
HB52R329E22-F
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. RE AD susp en d an d RE AD with Au to-p re ch arge susp en d: The data being output is held (a nd continues to be output). WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low. Clock susp en d mod e exit : The S DRA M module exits fr om cloc k suspend mode by setting C KE to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation. Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM module starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto- ref resh oper ation, re fre sh addr ess and bank sele ct addr ess ar e gene ra te d inside the S DRA M module. F or eve ry auto- ref resh cyc le, the interna l addr ess counte r is update d. Ac cordingly, 4096 time s ar e re quired to refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In addition, since the pre cha rge for all banks is automatica lly per forme d afte r auto- ref resh, no pre cha rge command is required after auto-refresh. S elf-r ef re sh en tr y [S E LF] : Whe n this command is input during the ID LE state, the S DRA M module starts self- re fre sh oper ation. Af te r the exe cution of this command, self- re fre sh continues while C KE is Low. S inc e self-refresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry: When this command is executed during the IDLE state, the SDRAM module enters powe r down mode. In powe r down mode, powe r consumption is suppre sse d by cutting off the initia l input circuit. S elf-r ef re sh exit : Whe n this command is exe cute d during self- re fre sh mode, the S DRA M module ca n exit from self-refresh mode. After exiting from self-refresh mode, the SDRAM module enters the IDLE state. Powe r d own exit : Whe n this command is exe cute d at the powe r down mode, the S DRA M module ca n exit from power down mode. After exiting from power down mode, the SDRAM module enters the IDLE state.
EO
26
L
Data Sheet No. E0112H10
Pr
uc od t
HB52R329E22-F
Function Truth Table
EO
Current state Precharge S RE H x L L L L L L L L H H H H L L L L x H H H H L L L L x H H H H L L L L Idle H L L L L L L L L Row active H L L L L L L L L
The following table shows the operations that are performed when each command is issued in each mode of the SDRAM module. The following table assumes that CKE is high.
CE x H H L L H H L W x H L H L H L Address x x x Command DESL NOP BST Operation Enter IDLE after t RP Enter IDLE after t RP NOP ILLEGAL*4 ILLEGAL*4 ILLEGAL*4 NOP*6 ILLEGAL ILLEGAL NOP NOP NOP ILLEGAL*5 ILLEGAL*5 Bank and row active NOP Refresh
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST
L
H L x H H L L L x H L H L H H L L x H H L L H H L L H L H L x H L H L H L H L
Data Sheet No. E0112H10 27
Pr
BA, RA x ACTV BA, A10 MODE x x x MRS DESL NOP BST BA, RA ACTV BA, A10 x MODE MRS
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A
PRE, PALL REF, SELF
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A
uc od
Mode register set NOP NOP NOP Begin read Begin write Other bank active ILLEGAL on same bank*3 Precharge ILLEGAL PRE, PALL REF, SELF ILLEGAL
t
HB52R329E22-F
Current state Read S H RE x CE x H H L L H H L W x H L H L H L H Address x x x Command DESL NOP BST Operation Continue burst to end Continue burst to end Burst stop to full page Continue burst read to CE latency and New read Term burst read/start write Other bank active ILLEGAL on same bank*3 Term burst read and Precharge ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL*4 ILLEGAL*4 Other bank active ILLEGAL on same bank*3 ILLEGAL*4 ILLEGAL
EO
L L L L L L L L H H H H L L L L x Read with autoprecharge H L L L L L L L L Write H L L L L L L L H H H H L L L L x H H H H L L L 28
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST
L
L x L x H H L L H L H L H H L L x H H L L H H L H L H L x H L H L H L H
Data Sheet No. E0112H10
Pr
BA, RA ACTV BA, A10 x MODE x x x MRS DESL NOP BST BA, RA ACTV BA, A10 x
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A
PRE, PALL REF, SELF
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A
uc od
ILLEGAL Continue burst to end Continue burst to end Burst stop on full page Term burst and New read Term burst and New write Other bank active ILLEGAL on same bank*3 Term burst write and Precharge*2 ILLEGAL PRE, PALL REF, SELF
t
HB52R329E22-F
Current state Write with autoprecharge S H L L L L L L L L RE x CE x H H L L H H L W x H L H L H L H Address x x x Command DESL NOP BST Operation Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL*4 ILLEGAL*4 Other bank active ILLEGAL on same bank*3 ILLEGAL*4 ILLEGAL ILLEGAL Enter IDLE after t RC Enter IDLE after t RC Enter IDLE after t RC ILLEGAL*5 ILLEGAL*5 ILLEGAL*5 ILLEGAL*5 ILLEGAL ILLEGAL
EO
H H H H L L L L x Refresh (auto-refresh) H L L L L L L L L H H H H L L L L
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST
Notes: 1. H: VIH. L: VIL. x: VIH or VIL. The other combinations are inhibit. 2. An interval of t DPL is required between the final valid data input and the precharge command. 3. If t RRD is not satisfied, this operation is illegal. 4. Illegal for same bank, except for another bank. 5. Illegal for all banks. 6. NOP for same bank, except for another bank.
L
L x L x H H L L H L H L H H L L H L H L
Data Sheet No. E0112H10 29
Pr
BA, RA x ACTV BA, A10 MODE MRS
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A
PRE, PALL REF, SELF
uc od t
HB52R329E22-F
From PRECHARGE state, command operation
EO
30
To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM module enters the IDLE state after tRP has elapsed from the completion of precharge.
From IDLE state, command operation To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The SDRAM module enters refresh mode (auto-refresh or self-refresh). To [MRS]: The SDRAM module enters the mode register set cycle.
From ROW ACTIVE state, command operation To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command. T o [PR E] , [PA LL ]: The se commands set the S DRA M module to pre cha rge mode. (H oweve r, an interva l of tRAS is required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CE latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the SDRAM module enters precharge mode.
L
Data Sheet No. E0112H10
Pr
uc od t
HB52R329E22-F
From READ with AUTO-PRECHARGE state, command operation
EO
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM module then enters precharge mode. T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the SDRAM module then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the SDRAM module enters precharge mode.
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
T o [D ES L] , [N OP] , [B S T] : Af te r an auto- ref resh cyc le (a fter tRC), the S DRA M module automatica lly ente rs the IDLE state.
L
Data Sheet No. E0112H10 31
Pr
uc od t
HB52R329E22-F
Simplified State Diagram
EO
Write WRITE SUSPEND CKE WRITEA SUSPEND CKE POWER APPLIED
SELF REFRESH SR ENTRY SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
Automatic transition after completion of command. Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
L
BST (on full page)
CKE CKE_ IDLE POWER DOWN
ACTIVE CLOCK SUSPEND
ACTIVE
CKE_ CKE
Pr
ROW ACTIVE WRITE READ WRITE WRITE WITH AP READ READ WITH AP WRITE READ READ WITH AP WRITE WITH AP PRECHARGE WRITEA READA PRECHARGE PRECHARGE PRECHARGE PRECHARGE
BST (on full page)
Read CKE_ CKE READ SUSPEND
CKE_
WRITE WITH AP CKE_
READ WITH AP
uc od
CKE_ CKE READA SUSPEND
POWER ON
t
Data Sheet No. E0112H10 32
HB52R329E22-F
Mode Register Configuration
EO
A13 A12 A11 A10 A9 OPCODE 0 0 0 0 1 0 0 1 1 X A13 A12 A11 A10 0 X X X 0 X X X 0 X X X 0 X X X A9 0 0 1 1 A8 0 1 0 1 Note: Only -6A.
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, A12, A11, A10, A9 A8: (OPCODE ): The S DRA M module has two types of wr ite modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. B ur st re ad an d b ur st wr it e: B urst wr ite is per forme d for the spec ified burst length starting fr om the column address specified in the write cycle. B ur st re ad an d single wr it e: Da ta is only wr itten to the column addr ess spec ified during the wr ite cyc le, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set. A6, A5, A4: (LMODE): These pins specify the CE latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length.
L
A8 A7 0 0 1 0 1 X R R
A6 A5 A4 CAS Latency R R 3* 4 R
Data Sheet No. E0112H10 33
Pr
A6 A5 A4 A3 LMODE BT A3 Burst Type 0 Sequential Interleave 1 Write mode Burst read and burst write Burst read and single write
A2
A1 BL
A0
uc od
A2 A1 A0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 0 Burst Length 1 2 4 1 2 4 8 BT=0 BT=1 8 R R R R R 1 0 1 R R 1 1 F.P. F.P. = Full Page R is Reserved (inhibit) X: 0 or 1
t
HB52R329E22-F
Burst Sequence
EO
Burst length = 2 A0 0 1 0, 1, 1, 0, Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 34
Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 A0 0 1 0 1 Sequential 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
Starting Ad. Addressing(decimal) Sequential Interleave 0, 1, 1, 0,
Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6,
L
A0 Sequential
Data Sheet No. E0112H10
Pr
uc od t
HB52R329E22-F
Operation of the Registered SDRAM module
EO
Read/Write Operations CE Latency
CK t RCD Command
ACTV
B ank act ive: B efor e exe cuting a re ad or wr ite oper ation, the cor re sponding bank and the row addr ess must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the B ank sele ct addr ess (B A) pin, and the row addr ess (A X0 to AX11) is ac tiva ted by the A0 to A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CE Latency - 1) cycle after read command set. The SDRAM module can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the column address and the bank select address (BA) at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the CE Latency. The CE Latency can be set to 3 or 4. Whe n the burst length is 1, 2, 4 or 8, the Dout buff er automatica lly bec omes High-Z at the next cloc k af ter the successive burst-length data has been output. The CE latency and burst length must be specified at the mode register.
Address
Row
L
READ Column
Pr uc od
out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 CL = CE latency Burst Length = 4
Dout
CL = 3 CL = 4
t
Data Sheet No. E0112H10 35
HB52R329E22-F
Burst Length
EO
CK
t RCD
Command Address
ACTV
READ
Row
Column
BL = 1 BL = 2 BL = 4 BL = 8
out 0 out 0 out 1 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
out 0-1
Dout
L
WRIT
Column
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 0
out 1
BL = full page
BL : Burst Length CE Latency = 3
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the next clock as a write command set. (The latency of data input is 1 clock.) The burst length can be set to 1, 2, 4, 8, and full-pa ge, like burst re ad oper ations. The wr ite start addr ess is spec ified by the column addr ess (and the bank select address (BA) at the write command set cycle.
CK
Pr
in 1 in 1 in 1 in 1
in 2 in 2 in 2
t RCD
Command Address
ACTV
uc od
in 5 in 6 in 7 in 5 in 6 in 7 in 8
in 0-1
Row
BL = 1 BL = 2
in 0 in 0
Din
in 0
in 3 in 3 in 3
BL = 4
in 0
in 4
BL = 8
in 0
in 4
in 0
in 1
BL = full page
CE Latency = 3, 4
t
Data Sheet No. E0112H10 36
HB52R329E22-F
2. S in gle wr it e: A single wr ite oper ation is ena bled by setting OP CO DE (A 9, A8) to (1, 0). In a single wr ite oper ation, data is only wr itten to the column addr ess and the bank selec t addr ess (B A) spec ified by the wr ite command set cycle without regard to the burst length setting. (The latency of data input is 1 clock).
EO
CK Command Address Din
t RCD
WRIT
ACTV
Row
Column
L
Precharge start cycle
READ A lRAS READ A lRAS
in 0
Auto Precharge
Re ad with au to-p re ch arge : In this oper ation, since pre cha rge is automatica lly per forme d af ter completing a re ad oper ation, a pre cha rge command nee d not be exe cute d af ter ea ch re ad oper ation. The command exe cute d for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by lAPR is required before execution of the next command.
Pr
out0 out1 out0
CE latency 4 3
2 cycle before the final data is output 1 cycle before the final data is output
uc od
ACTV out2 out3 lAPR = 0 ACTV out1 out2 out3 lAPR = 0
Burst Read (Burst Length = 4)
CK
CL=3 Command
ACTV
Dout
CL=4 Command
ACTV
Dout
Note: Internal auto-precharge starts at the timing indicated by " ". And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge "
".
t
Data Sheet No. E0112H10 37
HB52R329E22-F
Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command exe cute d for the same bank af ter the exe cution of this command must be the bank ac tive (A CTV ) command. In addition, an interva l of lAP W is re quired betwe en the fina l valid data input and input of next command. Burst Write (Burst Length = 4)
EO
CK Command
ACTV
L
IRAS
WRIT A
ACTV
Din
in0
in1
in2
in3 lAPW
Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ".
Pr
WRIT A
Single Write
uc od
ACTV
CK Command
ACTV
IRAS Din
in
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ".
t
Data Sheet No. E0112H10 38
HB52R329E22-F
Full-page Burst Stop
EO
CE latency 3 4 2 3
CK Command Dout
out out
CK Command Dout out out
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-pa ge burst. The B ST command sets the output buff er to High-Z and stops the full-pa ge burst re ad. The timing from command input to the last data changes depending on the CE latency setting. In addition, the BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8.
BST to valid data BST to high impedance 3 4
CE Latency = 3, Burst Length = full page
CE Latency = 4, Burst Length = full page
L
Data Sheet No. E0112H10 39
Pr
BST out out out
BST out out out out
out
out
l BSH = 3 clocks
l BSR = 2 clocks
uc od
out out l BSR = 3 clocks l BSH = 4 clocks
t
HB52R329E22-F
B ur st stop com man d at b ur st wr it e: The burst stop command (B S T command) is used to stop data input during a full-pa ge burst wr ite . No data is wr itten in the same cloc k as the B ST command, and in subseque nt cloc ks. In addition, the B ST command is only valid during full-pa ge burst mode, and is ille gal with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge command. Burst Length = full page
EO
CK Command Din in
BST in in t DPL
PRE/PALL
L
I BSW = 1 cycle
Data Sheet No. E0112H10 40
Pr uc od t
HB52R329E22-F
Command Intervals
EO
CK Command
Address
BA
ACTV
READ
Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cloc k. Eve n whe n the first command is a burst re ad that is not yet finished, the data re ad by the second command will be valid. READ to READ Command Interval (same ROW address in same bank)
L
READ Column A Column B
Row
Dout
Bank0 Active
out A0 out B0 out B1 out B2 out B3
Column =A Column =B Read Read
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges on same bank, conse cutive re ad commands ca nnot be exe cute d; it is nec essa ry to sepa ra te the two re ad commands with a pre cha rge command and a bank-active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cloc k, provide d that the other bank is in the bank- ac tive state. Eve n whe n the first command is a burst re ad that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank)
Pr
Column =A Column =B Dout Dout
CE Latency = 4 Burst Length = 4 Bank 0
uc od
out A0 out B0 out B1 out B2 out B3 Bank0 Bank3 Dout Dout
CK Command
Address
BA
ACTV
Row 0
ACTV
Row 1
READ READ
Column A Column B
Dout
Bank0 Active Bank3 Bank0 Bank3 Active Read Read
CE Latency = 4 Burst Length = 4
t
Data Sheet No. E0112H10 41
HB52R329E22-F
Write command to Write command interval:
EO
CK Command
Address
BA
ACTV WRIT
Row
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the pre ce ding wr ite command, the sec ond wr ite ca n be per forme d af ter an interva l of no less than 1 clock. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank)
WRIT
L
Column A Column B
Din
Bank0 Active
in A0
in B0
in B1
in B2
in B3
Column =A Column =B Write Write
Burst Write Mode Burst Length = 4 Bank 0
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands ca nnot be exe cute d; it is nec essa ry to sepa ra te the two wr ite commands with a pre cha rge command and a bank-active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cloc k, provide d that the other bank is in the bank- ac tive state. In the ca se of burst wr ite , the sec ond wr ite command has priority. WRITE to WRITE Command Interval (different bank)
Pr
WRIT in A0 in B0 in B1 in B2 in B3
uc od
Burst Write Mode Burst Length = 4
CK Command
Address
BA
ACTV ACTV WRIT
Row 0
Row 1
Column A Column B
Din
Bank0 Active
Bank3 Bank0 Bank3 Active Write Write
t
Data Sheet No. E0112H10 42
HB52R329E22-F
Read command to Write command interval:
EO
CK Command
CL=3
DQMB
1. S ame b ank , same ROW ad dr ess: Whe n the wr ite command is exe cute d at the same R OW addr ess of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQMB must be set High so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1)
READ WRIT
L
READ
CL=4
Din
in B0 High-Z
in B1
in B2
in B3
Dout
Burst Length = 4 Burst write
READ to WRITE Command Interval (2)
Pr
WRIT
CK Command
uc od
2 clock
DQMB
CL=3
High-Z High-Z
Dout
CL=4
Din
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active command.
3. Diff er en t b ank : Whe n the bank cha nges, the wr ite command ca n be per forme d af ter an interva l of no less than 1 clock, provided that the other bank is in the bank-active state. However, DQMB must be set High so that the output buffer becomes High-Z before data input.
t
Data Sheet No. E0112H10 43
HB52R329E22-F
Write command to Read command interval:
EO
CK Command DQMB Din Dout WRIT
CK Command DQMB Din Dout Column = A Write WRIT
1. S ame b ank , same ROW ad dr ess: Whe n the re ad command is exe cute d at the same R OW addr ess of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 cloc k. Howe ver , in the ca se of a burst wr ite , data will continue to be wr itten until one cyc le bef ore the re ad command is executed. WRITE to READ Command Interval (1)
READ
WRITE to READ Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be exe cute d; it is nec essa ry to sepa ra te the two commands with a pre cha rge command and a bank- ac tive command.
3. Diff er en t b ank : Whe n the bank cha nges, the re ad command ca n be per forme d af ter an interva l of no less than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
L
in A0 out B0 Column = A Write Column = B Read out B1 out B2 out B3 Burst Write Mode CE Latency = 3 Burst Length = 4 Bank 0
Pr
READ in A1 out B0 Column = B Read Column = B Dout
CE Latency Column = B Dout
uc od
out B1 out B2 out B3 CE Latency Burst Write Mode CE Latency = 3 Burst Length = 4 Bank 0
in A0
t
Data Sheet No. E0112H10 44
HB52R329E22-F
Read with auto precharge to Read command interval
EO
CK Command BA Dout READ A bank0 Read A
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is exe cute d. Eve n whe n the first re ad with auto- prec har ge is a burst re ad that is not yet finished, the data re ad by the sec ond command is valid. The interna l auto- prec har ge of one bank starts at the next cloc k of the sec ond command. Read with Auto Precharge to Read Command Interval (Different bank)
READ
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive read command (the same bank) is illegal. Write with auto precharge to Write command interval
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts at the next clock of the second command . Write with Auto Precharge to Write Command Interval (Different bank)
L
bank3 Read
out A0
out A1
out B0
out B1 CE Latency = 4 Burst Length = 4
".
Pr
WRIT in A1 bank3 Write in B0 in B1 ".
uc od
in B2 in B3 Burst Length = 4
CK Command BA Din bank0 Write A in A0 WRIT A
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive write command (the same bank) is illegal.
t
Data Sheet No. E0112H10 45
HB52R329E22-F
Read with auto precharge to Write command interval
EO
CK Command BA DQMB CL = 3 CL = 4 Din Dout 46
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is executed. However, DQMB must be set High so that the output buffer becomes High-Z before data input. The internal auto-precharge of one bank starts at the next clock of the second command. Read with Auto Precharge to Write Command Interval (Different bank)
READ A
WRIT
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.
L
bank0 Read A bank3 Write
in B0
in B1
in B2
in B3
High-Z
Data Sheet No. E0112H10
Pr
Burst Length = 4
".
uc od t
HB52R329E22-F
Write with auto precharge to Read command interval
EO
CK Command BA WRIT A DQMB Din Dout in A0 bank0 Write A
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is exe cute d. Howe ver , in ca se of a burst wr ite , data will continue to be wr itten until one cloc k bef ore the re ad command is executed. The internal auto-precharge of one bank starts at the next clock of the second command. Write with Auto Precharge to Read Command Interval (Different bank)
READ
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.
L
bank3 Read
out B0
out B1
out B2
out B3
CE Latency = 4 Burst Length = 4
Data Sheet No. E0112H10 47
Pr
".
uc od t
HB52R329E22-F
Read command to Precharge command interval (same bank):
EO
CK Command READ Dout
CK Command READ Dout
When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the cloc ks def ined by lHZ P, ther e is a ca se of interr uption to burst re ad data output will be interr upte d, if the precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CE Latency = 3, Burst Length = 4
CE Latency = 4, Burst Length = 4
L
out A0 CL=3
CL=4
PRE/PALL
out A1
out A2 l EP = -2 cycle
out A3
Data Sheet No. E0112H10 48
Pr
PRE/PALL
uc od
out A0 out A1 out A2 out A3 l EP = -3 cycle
t
HB52R329E22-F
READ to PRECHARGE Command Interval (same bank): To stop output data
EO
CK Command READ Dout
CK Command READ Dout
CE Latency = 3, Burst Length = 1, 2, 4, 8, full page burst
PRE/PALL High-Z
out A0 lHZP = 3
CE Latency = 4, Burst Length = 1, 2, 4, 8, full page burst
L
PRE/PALL
Data Sheet No. E0112H10 49
Pr
out A0 High-Z lHZP = 4
uc od t
HB52R329E22-F
Writ e com man d to Pr ech arge com man d int er val (sam e b ank ): Whe n the pre cha rge command is exe cute d for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cloc k. Howe ver , if the burst wr ite oper ation is unfinished, the input data must be maske d by mea ns of DQMB for assurance of the clock defined by tDPL. WRITE to PRECHARGE Command Interval (same bank): Burst Length = 4 (To stop write operation)
EO
CK Command WRIT DQMB Din tDPL CK Command DQMB WRIT Din CK Command DQMB WRIT Din
PRE/PALL
Burst Length = 4 (To write all data)
L
in A0 in A0
Data Sheet No. E0112H10 50
Pr
PRE/PALL
in A1
uc od
PRE/PALL
tDPL
in A1
in A2
in A3
tDPL
t
HB52R329E22-F
Bank active command interval:
EO
CK Command ACTV Address ROW BA Bank 0 Active
1. Same bank: The interval between the two bank-active commands must be no less than tRC. Bank Active to Bank Active for Same Bank
ACTV
ROW
2. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank Active to Bank Active for Different Bank
L
ACTV ROW:0 t RRD Bank 0 Active
t RC Bank 0 Active
Pr
ACTV ROW:1 Bank 3 Active
CK
uc od t
51
Command
Address
BA
Data Sheet No. E0112H10
HB52R329E22-F
Mod e re gister set to B ank -ac tive com man d int er val: The interva l betwe en setting the mode re giste r and executing a bank-active command must be no less than lRSA .
EO
CK Command Address
MRS
ACTV
CODE
BS & ROW
L
Mode Register Set
I RSA Bank Active
DQMB Control The DQMB mask the DQ data. The timing of DQMB is different during reading and writing. Re adin g: Whe n data is re ad, the output buff er ca n be contr olle d by DQMB . B y setting DQMB to Low, the output buff er bec omes Low- Z, ena bling data output. B y setting DQMB to High, the output buff er bec omes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMB during reading is 3 clocks. Writ in g: Input data ca n be maske d by DQMB . B y setting DQMB to Low, data ca n be wr itten. In addition, when DQMB is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMB during writing is 1 clock.
Data Sheet No. E0112H10 52
Pr
uc od t
HB52R329E22-F
Reading
; ;;
DQMB Din in 0 in 1 in 3 l DID = 1 Latency Data Sheet No. E0112H10
EO
CK DQMB Dout
High-Z out 0 out 1 out 3
lDOD = 3 Latency
L
CK
Writing
Pr
uc od t
53
HB52R329E22-F
Refresh
EO
Others
54
Au to-r ef re sh : All the banks must be pre cha rged bef ore exe cuting an auto- ref resh command. S inc e the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW addr esses to be re fre shed, exte rnal addr ess spec ifica tion is not re quired. The re fre sh cyc le is 4096 cyc les/64 ms. (4096 cyc les ar e re quired to re fre sh all the R OW addr esses. ) The output buff er bec omes High-Z af ter auto- ref resh start. In addition, since a pre cha rge has bee n complete d by an interna l oper ation af ter the autorefresh, an additional precharge operation by the precharge command is not required.
S elf-r ef re sh : Af te r exe cuting a self- re fre sh command, the self- re fre sh oper ation continues while C KE is held Low. Dur ing self- re fre sh oper ation, all R OW addr esses ar e re fre shed by the interna l re fre sh time r. A selfre fre sh is ter mina te d by a self- re fre sh exit command. B efor e and af ter self- re fre sh mode, exe cute auto- ref resh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below. (1) Enter self-refresh mode within 15.6 s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 s after exiting from self-refresh mode.
Powe r- down mod e: The S DRA M module ente rs powe r-dow n mode whe n C KE goes Low in the ID LE state. In powe r down mode, powe r consumption is suppre sse d by dea ctivating the input initia l cir cuit. P ower down mode continues while C KE is held Low. In addition, by setting C KE to High, the S DRA M module exits fr om the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed. Clock susp en d mod e: B y driving C KE to Low during a bank- ac tive or re ad/wr ite oper ation, the S DRA M module ente rs cloc k suspend mode. Dur ing cloc k suspend mode, exte rnal input signals ar e ignore d and the interna l state is maintained. Whe n C KE is drive n High, the S DRA M module ter mina te s cloc k suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table". Power-up sequence: The SDRAM module should be gone on the following sequence with power up.
The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes. The CK pin is stabilized within 100 s after power stabilizes before the following initialization sequence. The CKE and DQMB is driven to high between power stabilizes and the initialization sequence.
This SDRAM module has VCC clamp diodes for CK, CKE, S, DQMB and DQ pins. If these pins go high before power up, the large current flows from these pins to VCC through the diodes.
Initialization sequence: When 200 s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). S et the mode re giste r set command (MR S) to initia liz e the mode re giste r. We re commend that by kee ping DQM, DQMU /D QML to High, the output buff er bec omes High-Z during Initializa tion seque nce , to avoid DQ bus contention on memory system formed with a number of device.
L
Data Sheet No. E0112H10
Pr
uc od t
HB52R329E22-F
Initialization sequence: When 200 s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). S et the mode re giste r set command (MR S) to initia liz e the mode re giste r. We re commend that by kee ping DQMB to High, the output buff er bec omes High-Z during Initializa tion seque nce , to avoid DQ bus conte ntion on memory system formed with a number of device. S tabilizat ion time : The P LL re quires a stabiliz ation time to ac hieve phase lock of the fe edba ck signal to the re fe renc e signal. This stabiliz ation time is re quired following powe r-up. S o this S DRA M module nee ds dammy cycle for 50 s after power-up.
Power up sequence 100 s Initialization sequence 200 s
EO
VCC CKE, DQMB CK S, DQ 0V Low Low Low
L
Power stabilize
Data Sheet No. E0112H10 55
Pr uc od t
HB52R329E22-F
Timing Waveforms
;;; ; ;;;; ; ; ;;;; ;
t CK t CKH t CKL
; ;; ;; ;; ;; ;; ;; ;
t RCD t CS t CH t CS t CH t CS t CH t CS t CH
EO
Read Cycle
CK
VIH
t RC
CKE
t RAS
t
RP
S
t CS t CH
L
t CS t CH t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t CS Bank 0 Read
t CS t CH
t CS t CH
RE
t CS t CH
t CS t CH
t CS t CH
CE
t CS t CH
t CS t CH
t CS t CH
W
Pr
t AS t AH t AS t AH t CH t AC t AC t AC t LZ t OH t OH t OH
t AS t AH t AS t AH
t AS t AH t AS t AH
BA
A10
t AS t AH
t AS t AH
Address
uc od
t AC t HZ t OH Bank 0 Precharge
DQMB
Din
Dout
Bank 0 Active
CE latency = 3 Burst length = 4 Bank 0 access = VIH or VIL
t
Data Sheet No. E0112H10
56
;; ;; ;; ;; ;
HB52R329E22-F
Write Cycle
;;; ; ;
t CS t CH t CS t CH t CS t CH
EO
t CK t CKH t CKL
CK
t RC
VIH
CKE
t RCD
t RAS
t RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
S
t CS t CH
RE
t CS t CH
L
t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t CS Bank 0 Write
t CS t CH
t CS t CH
CE
t CS t CH
t CS t CH
t CS t CH
W
t AS t AH t AS t AH
t AS t AH
t AS t AH t AS t AH
BA
Pr
t AS t AH t CH t DS t DH tDS t DH t DS t DH t DS t DH t DPL
A10
t AS t AH
t AS t AH
Address
DQMB
uc od
Bank 0 Precharge
Din
Dout
Bank 0 Active
CE latency = 3 Burst length = 4 Bank 0 access = VIH or VIL
t
Data Sheet No. E0112H10 57
;;;; ;;; ; ;;;;;; ;;; ; ; ;; ; ;;;;;;; ; ; ;;;; ; ;
DQMB Dout Din
High-Z l RP l RSA l RCD
Output mask Precharge If needed Mode Bank 3 register Active Set Bank 3 Read
;;;; ;;; ;; ;;
HB52R329E22-F
Mode Register Set Cycle
0 1
Read Cycle/Write Cycle
0 1 2
3
4
5
6
7
8
9
10
11
12
13
CK S
CKE
VIH
RE CE W BA
Address DQMB Dout Din
R:a
C:a
R:b
C:b
C:b'
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
Bank 3 Read
High-Z
Bank 0 Active
Bank 0 Read
Bank 3 Active
Bank 3 Bank 0 Read Precharge
Bank 3 Read
CKE S
VIH
RE CE W BA
Address DQMB Dout
R:a
C:a
R:b
C:b
C:b'
High-Z
Din
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
Bank 3 Write
Bank 0 Active
Bank 0 Write
Bank 3 Active
Bank 3 Write
Bank 0 Precharge
Data Sheet No. E0112H10
58
;
b b+3 b' b'+1 b'+2 b'+3
EO
2 3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CK
CKE S
VIH
RE CE W
BA
L
code R: b
Address
valid
C: b
C: b'
l RCD = 3 CE latency = 4 Burst length = 4 IH = V IL or V
Pr
14 15 C:b" C:b" b'+1 b"
Bank 3 Write
16
17
18
19
20
21
Read cycle RE-CE delay = 3 CE latency = 4 Burst length = 4 = VIH or VIL
uc od
b'+1 b" b"+1 b"+2 b"+3
Bank 3 Precharge
Write cycle RE-CE delay = 3 CE latency = 4 Burst length = 4 = VIH or VIL
t
b"+1 b"+2 b"+3
Bank 3 Precharge
;;; ; ; ;;; ;
HB52R329E22-F
Read/Single Write Cycle
0 1
;;; ; ; ; ; ;
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK S CKE RE CE W BA
VIH
EO
Address DQMB Dout R:a C:a Din
Bank 0 Active Bank 0 Read
R:b
C:a' C:a a
L
a
Bank 3 Active
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0 Precharge
Bank 0 Bank 0 Write Read
Bank 3 Precharge
CKE S
VIH
RE CE W BA
Pr
R:b C:a a a a+1 a+3
Bank 3 Active Bank 0 Write
Address DQMB
R:a
C:a
C:b C:c b
Din
c
Dout
Bank 0 Active
Bank 0 Read
Bank 0 Bank 0 Write Write
Bank 0 Precharge
Data Sheet No. E0112H10 59
uc od
Read/Single write RE-CE delay = 3 CE latency = 4 Burst length = 4 = VIH or VIL
t
;; ; ; ; ;;
HB52R329E22-F
Read/Burst Write Cycle
0 1
; ;; ;
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK S CKE RE CE W BA Address DQMB R:a C:a R:b C:a' Din a a+1 a+2 a+3
EO
Dout
Bank 0 Active Bank 0 Read
L
a
Bank 3 Active
a+1 a+2 a+3
Clock suspend
Bank 0 Write
Bank 0 Precharge
Bank 3 Precharge
CKE S
VIH
RE CE W BA
Pr
R:b C:a a a a+1 a+3
Bank 3 Active Bank 0 Write
Address DQMB
R:a
C:a
Din
a+1 a+2 a+3
Dout
Bank 0 Active
Bank 0 Read
Bank 0 Precharge
Data Sheet No. E0112H10
uc od
Read/Burst write RE-CE delay = 3 CE latency = 4 Burst length = 4 = VIH or VIL
t
60
;;;; ; ; ;
HB52R329E22-F
Full Page Read/Write Cycle
CK
CKE RE CE
VIH
S
W
BA
Address DQMB Dout Din
R:a
Bank 0 Active
Bank 0 Read
CKE
VIH
S
RE CE BA
W
Address DQMB
R:a
Dout Din
Bank 0 Active
Bank 0 Write
;; ;
Read cycle RE-CE delay = 3 CE latency = 4 Burst length = full page = VIH or VIL
C:a R:b a a+1 a+2
EO
C:a R:b a a+1
High-Z
Bank 3 Active
Burst stop
Bank 3 Precharge
L
a+2 a+3 a+4 Bank 3 Active
Write cycle RE-CE delay = 3 CE latency = 4 Burst length = full page = VIH or VIL
Data Sheet No. E0112H10
Pr
High-Z
a+5
Burst stop
Bank 3 Precharge
uc od
61
t
;;;; ;; ; ;; ;;;
HB52R329E22-F
Auto Refresh Cycle
0
;;;; ; ;;; ;;; ; ;; ;;; ;;; ;;;;; ;;; ;;;; ;;;; ; ;; ; ;;;;;; ;; ;; ; ;
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
EO
CK CKE S
VIH
RE CE
W
BA
Address DQMB Din
A10=1
R:a
C:a
L
t RC
Auto Refresh
Dout
High-Z
a
a+1
t RP
tRC
Precharge If needed
Auto Refresh
Active Bank 0
Read Bank 0
Refresh cycle and Read cycle RE-CE delay = 2 CE latency = 4 Burst length = 4 = VIH or VIL
Pr
l SREX
Self Refresh Cycle
CK
CKE S
CKE Low
uc od
tRC tRC
Next clock enable Self refresh entry command Auto Next clock refresh enable
RE CE W
BA
Address
A10=1
DQMB Din
Dout
High-Z
tRP
Precharge command If needed
Self refresh entry command
Self refresh exit ignore command or No operation
Self refresh cycle RE-CE delay = 3 CE latency = 4 Burst length = 4 = VIH or VIL
t
Data Sheet No. E0112H10
62
;;;; ;;; ;;
HB52R329E22-F
Clock Suspend Mode
t CES
t CEH
t CES
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CK S
CKE RE CE W BA
Address DQMB
R:a
C:a
R:b
C:b
Dout Din
a
a+1 a+2
a+3
b
High-Z
Bank0 Active clock Active suspend start
Active clock Bank0 suspend end Read
Bank3 Active
Read suspend start
Read suspend end
Bank3 Read
Bank0 Precharge
CKE S RE CE W BA
Address DQMB
R:a
C:a R:b
C:b
Dout Din
High-Z
a
a+1 a+2
a+3 b
b+1 b+2 b+3
Bank0 Active
Active clock suspend start
Active clock Bank0 Bank3 supend end Write Active
Write suspend start
Write suspend end
Bank3 Bank0 Write Precharge
Data Sheet No. E0112H10
;
17 18 19 20
Read cycle RE-CE delay = 2 CE latency = 3 Burst length = 4 = VIH or VIL
;; ;;;; ; ;;;; ; ; ;;; ;; ; ;;; ;;;;
L
b+1 b+2 b+3
Earliest Bank3 Precharge
EO
Write cycle RE-CE delay = 2 CE latency = 3 Burst length = 4 = VIH or VIL
Pr
Earliest Bank3 Precharge
uc od
63
t
;; ;; ;; ; ; ;
HB52R329E22-F
Power Down Mode
;; ;; ;;; ; ;;; ;; ;; ; ;; ;
0 1 2 3 4 5 6 7 8 9 10 48 49 50 51 52 53 54 55
;;; ; ;;; ;;; ;; ;; ;;; ; ; ;; ;; ; ;;
CKE S
CKE Low
EO
CK RE CE W BA Address DQMB Din
A10=1
L
tRP
t RP
Auto Refresh
R: a
Pr
High-Z
Power down entry
t RC tRC
Auto Refresh
Dout
Precharge command If needed
Power down mode exit Active Bank 0
Power down cycle RE-CE delay = 3 CE latency = 3 Burst length = 4 = VIH or VIL
uc od
code Valid High-Z t RSA
Mode register Set Bank active If needed
Initialization Sequence
CK
CKE S
VIH
RE CE
W
Address DQMB DQ
valid
VIH
All banks Precharge
t
Data Sheet No. E0112H10
64
HB52R329E22-F
Physical Outline
4.00 0.157
17.78 0.700
Detail A
2.54 min 0.100 min
Detail B 1.27 0.050
0.25 max 0.010 max
Detail C
3.175 0.125
4.175 0.164
3.125 0.125 0.123 0.005
1.00 0.05 0.039 0.002
Note: Tolerance on all dimensions 0.15/0.006 unless otherwise specified.
3.125 0.125 0.123 0.005
6.35 0.250 2.00 0.10 0.079 0.004
6.35 0.250 2.00 0.10 0.079 0.004
Data Sheet No. E0112H10 65
38.10 1.500
168
EO
Front side 3.00 0.118
3.00 0.118
133.37 5.251 127.35 5.014
Unit: mm inch 4.80 0.189
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Front) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 1 84 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ; ;; ; ;; ; ;; ; ;; ; ;; ; ;; ; ;; ; ;; ;
C
B 54.61 2.150
A 1.27 0.10 0.050 0.004
8.89 0.350
11.43 0.450
36.83 1.450
Back side 2 - 3.00 2 - 0.118 85
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Back) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4.00 min 0.157 min
L
Pr
uc od t
HB52R329E22-F
Cautions
EO
66
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
L
Data Sheet No. E0112H10
Pr
uc od t

▲Up To Search▲

Price & Availability of HB52R329E22-A6F

	To Download HB52R329E22-A6F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .