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Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS General Description
The AZ7500F is a voltage mode pulse width modulation switching regulator control circuit designed primarily for power supply control. The AZ7500F consists of a reference voltage circuit, two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC) comparator, a pulse-steering control flip-flop, and an output control circuit. The precision of voltage reference (VREF) is improved up to 1% through trimming and this provides a better output voltage regulation. The AZ7500F provides for pushpull or single-ended output operation, which can be selected through the output control. The AZ7500F is available in standard packages of DIP16 and SOIC-16.
AZ7500F
Features
* * * * * * Stable 5V Reference Voltage Trimmed to 1.0% Accuracy Uncommitted Output TR for 200mA Sink or Source Current Single-End or Push-Pull Operation Selected by Output Control Internal Circuitry Prohibits Double Pulse at Either Output Complete PWM Control Circuit with Variable Duty Cycle On-Chip Oscillator With Master or Slave Operation
Applications
* * * SMPS Back Light Inverter Charger
SOIC-16
DIP-16
Figure 1. Package Types of AZ7500F
Oct. 2009 Rev. 1. 2 1
BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS AZ7500F
Pin Configuration
M Package (SOIC-16)
1IN + 1IN FEEDBACK DTC CT RT GND C1
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
P Package (DIP-16)
2IN + 2IN REF OUTPUT CTRL VCC C2 E2 E1 1IN + 1IN FEEDBACK DTC CT RT GND C1
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
2IN + 2IN REF OUTPUT CTRL VCC C2 E2 E1
Figure 2. Pin Configuration of AZ7500F (Top View)
Output Function Control Table
Signal for Output Control VI = GND VI = VREF Output Function Single-ended or parallel output Normal push-pull operation
Functional Block Diagram
OUTPUT CTRL
RT CT 6 5
13
Oscillator
8
Q1
Pulse-Steering Flip-Flop
C1
Dead-Time Control Comparator DTC 4
0.12V
9
D CK
E1 C2
+
11
Q2
Error Amplifier 1 1IN + 1IN 1 2
+
+
PWM Comparator
10
E2
12
2IN + 2IN 16 15 Error Amplifier 2
VCC REF GND
+
0.7mA
Reference Regulator
14 7
FEEDBACK
3
Figure 3. Functional Block Diagram of AZ7500F Oct. 2009 Rev. 1. 2 2 BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS Ordering Information AZ7500F
AZ7500
G1: Green
Circuit Type TR: Tape and Reel Blank: Tube Reference Voltage F: 5V Package M: SOIC-16 P: DIP-16
Package SOIC-16 DIP-16
Temperature Range
Part Number AZ7500FM-G1
Marking ID AZ7500FM-G1 AZ7500FM-G1 AZ7500FP-G1
Packing Type Tube Tape & Reel Tube
-40 to 85oC
AZ7500FMTR-G1 AZ7500FP-G1
BCD Semiconductor's Pb-free products, as designated with "G1" suffix in the part number, are RoHS compliant and green.
Oct. 2009 Rev. 1. 2 3
BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS Absolute Maximum Ratings (Note 1)
Parameter Supply Voltage (Note 2) Amplifier Input Voltage Collector Output Voltage Collector Output Current Package Thermal Impedance (Note 3) Lead Temperature 1.6mm from case for 10 seconds Storage Temperature Range ESD Rating (Machine Model) TSTG Symbol VCC VI VO IO RJA M Package P Package 260 -65 to 150 200 Value 40 -0.3 to VCC + 0.3 40 250 73 67 Unit V V V mA
oC/W oC o
AZ7500F
C
V
Note 1: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to "Absolute Maximum Ratings" for extended periods may affect device reliability. Note 2: All voltage values are with respect to the network ground terminal. Note 3: Maximum power dissipation is a function of TJ(max), RJA and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = ( TJ(max) - TA )/RJA. Operating at the absolute maximum TJ of 150oC can affect reliability.
Recommended Operating Conditions
Parameter Supply Voltage Collector Output Voltage Collector Output Current (Each Transistor) Amplifier Input Voltage Current Into Feedback Terminal Reference Output Current Timing Capacitor Timing Resistor Oscillator Frequency PWM Input Voltage (Pin 3, 4, 14) Operating Free-Air Temperature TA Push-pull Mode Single-ended Mode Symbol VCC VC1, VC2 IC1, IC2 VI IFB IREF CT RT fOSC 0.00047 1.8 1 0.3 -40 0.001 30 40 0.3 Min 7 Typ 15 30 Max 36 36 200 VCC - 2 0.3 10 10 500 300 500 5.3 85 Unit V V mA V mA mA F K kHz V
oC
Oct. 2009 Rev. 1. 2 4
BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS Electrical Characteristics
Parameter Reference Section Output Reference Voltage Line Regulation Load Regulation Short-Circuit Output Current Oscillator Section CT=0.01F, RT=12K Oscillator Frequency fOSC CT=0.01F, RT=12K, TA= -40 to 85 C Frequency Change with Temperature Dead-Time Control Section Input Bias Current Maximum Duty Cycle Input Threshold Voltage Error-Amplifier Section Input Offset Voltage Input Offset Current Input Bias Current Common-Mode Input Voltage Range Open-Loop Voltage Gain Unity-Gain Bandwidth Common-Mode Rejection Ratio Output Sink Current (Feedback) Output Source Current (Feedback) VIO IIO IBIAS VCM GVO BW CMRR ISINK ISOURCE VID = -15mV to -5V, V3 = 0.7V VID=15mV to 5V V3 = 3.5V 65 -0.3 2 V3 = 2.5V V3 = 2.5V V3 = 2.5V VCC=7V to 36V VO =0.5V to 3.5V -0.3 70 95 650 80 -0.7 2 25 0.2 10 250 1 VCC-2 mV nA A V dB KHz dB mA mA IBIAS D(MAX) VITH VCC=15V, V4= 0 to 5.25V VCC=15V, V4= 0V, Pin 13= VREF Zero Duty Cycle Maximum Duty Cycle 0 45 3 3.3 -2 -10 A % V f /T CT=0.01F, RT=12K, TA= -40 to 85oC
o
AZ7500F
TA = 25oC, VCC=20V, f=10KHz unless otherwise noted.
Symbol Conditions IREF=1mA IREF=1mA, TA= -40 to 85 C VCC = 7V to 36V IREF=1mA to 10mA VREF = 0V 10 9.9 9.7
o
Min 4.95 4.9
Typ 5.0 5.0 2 1 35 10.7
Max 5.05 5.1 25 15 50 11.5 12.7
Unit V V mV mV mA
VREF RLINE RLOAD ISC
KHz
1
%
Oct. 2009 Rev. 1. 2 5
BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS Electrical Characteristics (Continued)
Parameter PWM Comparator Section Input Threshold Voltage Input Sink Current Output Section Common Emitter Output Saturation Voltage Emitter Follower VCE (SAT) VCC (SAT) IC (OFF) IE(OFF) ICC VE = 0V, IC =200mA VCC = 15V, IE = -200mA VCE = 36V, VCC=36V VCC = VC = 36V, VE = 0 Pin 6 = VREF, VCC=15V Common Emitter Common Collector Common Emitter Common Collector 6 1.1 1.5 2 1.3 V 2.5 100 -100 10 A A mA VITH ISINK Zero duty cycle V3 = 0.7V -0.3 4 -0.7 4.5 V mA Symbol Conditions Min Typ Max Unit
AZ7500F
Collector Off-State Current Emitter Off-State Current Total Device Supply Current Output Switching Characteristics Rise Time Fall Time
tR tF
100 25
200 100
ns ns
Oct. 2009 Rev. 1. 2 6
BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS Parameter Measurement information
VCC = 20V 12 4 Test Inputs 3 12K 6 5 0.01uF 1 2 16 15 13 50K VCC DTC FEEDBACK RT CT 1IN+ 1IN2IN+ 2INOUTPUT CTRL GND 7 REF 14 C1 E1 C2 E2 8 9 11 10 Output 2 150 4W 150 4W Output 1
AZ7500F
Test Circuit
Voltage at C1 Voltage at C2 Voltage at CT
VCC 0V VCC 0V
Threshold Voltage DTC
0V Threshold Voltage
FEEDBACK 0.7V Duty Cycle 0% MAX
0%
Voltage Waveforms Figure 4. Operational Test Circuit and Waveforms
Oct. 2009 Rev. 1. 2 7
BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS Parameter Measurement information (Continued)
+ Amplifier Under Test FEEDBACK
AZ7500F
VI
+ Vref Other Amplifier
Figure 5. Error Amplifier Characteristics
20V
68 4W Each Output Circuit Output CL = 15pF (See Note A) 90%
tf
tr 90%
10%
10%
Note A: CL includes probe and jig capacitance. Figure 6. Common-Emitter Configuration
20V Each Output Circuit
90%
90%
Output CL = 15pF (See Note A) 68 4W 10% tr 10% tf
Note A: CL includes probe and jig capacitance. Figure 7. Emitter-Follower Configuration
Oct. 2009 Rev. 1. 2 8
BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS Typical Performance Characteristics AZ7500F
100 90 80
VCC=20V VO=3V TA=25 C
o
Voltage Gain (dB)
70 60 50 40 30 20 10 0 1 10 100 1k 10k 100k 1M
Frequency (Hz)
Figure 8. Error Amplifier Small-Signal Voltage Gain vs. Frequency
Oct. 2009 Rev. 1. 2 9
BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS Typical Application
(VI=10V to 40V) 1mH 2A (VO=5V, IO=1A)
AZ7500F
VI(+)
47
KSA1010
VO
150
0.1
1M 5.1k
12
VCC
11
C2
8
C1
3
FEED BACK
2
1INREF 2IN1IN+ 2IN+
14 15 1 16
50 + 10V 5.1k 5.1k
+
50 10V
+ 50 50V
AZ7500F
DTC GND 4 7
E1 9
OUTPUT CTRL 13
E2 10
RT 6 47k
CT 5
150
+
0.001
GND
0.1
VI(-)
Figure 9. Pulse Width Modulated Step-Down Converter
Oct. 2009 Rev. 1. 2 10
BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS Mechanical Dimensions SOIC-16 Unit: mm(inch) AZ7500F
1.350(0.053) 1.750(0.069) 7 0.330(0.013) 0.510(0.020) B
1.250(0.049) 1.650(0.065)
7
0.250(0.010)
A 20:1 0.400(0.016) 1.270(0.050)
9.800(0.386) 10.200(0.402)
0 8 R0.200(0.008) R0.200(0.008)
1.270(0.050) BSC
0.170(0.007) 0.250(0.010)
5.800(0.228) 6.240(0.246) 3.800(0.150) 4.040(0.159) 9 .5
0.050(0.002) 0.250(0.010)
0.200(0.008) 0.250(0.010)
C-C 50:1
8
B 20:1 C 0.200(0.008) S 1.000(0.039) Depth 0.200(0.008) C
1.000(0.039)
3 7
8
8
A 0.400(0.016)x45
Note: Eject hole, oriented hole and mold mark is optional.
Oct. 2009 Rev. 1. 2 11
BCD Semiconductor Manufacturing Limited
Preliminary Datasheet PULSE-WIDTH-MODULATION CONTROL CIRCUITS Mechanical Dimensions (Continued) DIP-16 Unit: mm(inch) AZ7500F
Note: Eject hole, oriented hole and m old mark is optional.
Oct. 2009 Rev. 1. 2 12
BCD Semiconductor Manufacturing Limited
BCD Semiconductor Manufacturing Limited
http://www.bcdsemi.com
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