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ISL34341
Data Sheet December 15, 2008 FN6827.0
WSVGA 24-Bit Long-Reach Video SERDES with Bi-directional Side-Channel
The ISL34341 is a serializer/deserializer of LVCMOS parallel video data. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer. It also transports auxiliary data bi-directionally over the same link during the video vertical retrace interval. I2C bus mastering allows the placement of external slave devices on the remote side of the link. An I2C controller can be placed on either side of the link allowing bi-directional I2C communication through the link to the external devices on the other side. Both chips can be fully configured from a single controller or independently by local controllers.
Features
* 24-bit RGB transport over single differential pair * 6MHz to 40MHz pixel clock rates * Bi-directional auxiliary data transport without extra bandwidth and over the same differential pair * I2C Bus Mastering to the remote side of the link with a controller on either the serializer or deserializer * 40MHz PCLK transports - SVGA 800x600 @ 70fps, 16% blanking - WSVGA 1024x600 @ 60fps, 8% blanking * Internal 100 termination on high-speed serial lines * DC balanced with industry standard 8b/10b line code allows AC-coupling - Provides immunity against ground shifts * Hot plugging with automatic resynchronization every line * 16 programmable settings each for transmitter amplitude boost and pre-emphasis and receiver equalization allow for longer cable lengths and higher data rates * Programmable power-down of the transmitter and the receiver * Same device for serializer and deserializer simplifies inventory * I2C communication interface * 8kV ESD rating for serial lines * Pb-free (RoHS compliant)
Ordering Information
PART NUMBER (Note) PART MARKING TEMP. RANGE (C) PACKAGE (Pb-free) PKG. DWG. #
ISL34341INZ* ISL34341INZ -40 to +85 64 Ld EPTQFP Q64.10x10C *Add "-T13" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Applications
* Navigation and display systems * Video entertainment systems * Industrial computing terminals * Remote cameras
3.3V
1.8V
VDD _IO
3.3V
1.8V
VDD _IO
RSTB/PDB
24
RSTB/PDB
VDD_P
VDD_TX
VDD_TX
VDD_IO
VDD_AN
VDD_AN
VDD_IO
VDD_P
VDD_CR
VDD_CR
VDD_CDR
VDD_CDR
24
RG BA/B/C
27nF
10m D IFFER EN TIAL CABLE
27nF
SERIO P
SERIO P
27nF 27nF
RG BA/B/C
V ID E O SOURCE
VSYN C HSYN C DATAEN PC LK _IN
ISL34341
SER IO N REF_C LK
SER IO N PC LK _IN
ISL34341
VSYNC HSYNC D ATAEN PC LK _O UT VIDEO_TX
V ID E O S IN K
GND_CDR
GND_CDR
VIDEO_TX
REF_RES
REF_RES
GND_CR
GND_CR
GND_AN
GND_AN
GND_TX
GND_TX
GND_IO
GND_IO
GND_P
GND_P
I2CA0
3.16 K
VD D_IO
3.16 K
VD D_IO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
I2CA0
ISL34341 Pinout
ISL34341 (64 LD TQFP) TOP VIEW
GND_IO VDD_CDR VDD_CDR GND_CDR GND_CDR VDD_TX GND_TX SERIOP SERION GND_TX VDD_AN GND_AN REF_RES MASTER I2CA0 I2CA1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Block Diagram
SCL SDA I2C VCM GENERATOR RAM PREEMPHASIS 3 V/H/DE TDM RGB 24 RX EQ 8b/10b MUX DEMUX SERION SERIOP
VDD_IO RGBB4 RGBB5 RGBB6 RGBB7 RGBC0 RGBC1 RGBC2 RGBC3 RGBC4 RGBC5 RGBC6 RGBC7 STATUS TEST_EN RSTB/PDB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VIDEO_TX VDD_IO PCLK_OUT RGBA0 RGBA1 RGBA2 RGBA3 RGBA4 RGBA5 RGBA6 RGBA7 RGBB0 RGBB1 RGBB2 RGBB3 GND_IO
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
I2CA2 I2CA3 SDA SCL VDD_P GND_P PCLK_IN VSYNCPOL HSYNCPOL VSYNC HSYNC DATAEN VDD_CR VDD_CR GND_CR GND_CR
TX
VIDEO_TX (HI) CDR PCLK_IN (REF_CLK WHEN VIDEO_TX IS LO) PCLK_OUT
x30
/30
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ISL34341
Absolute Maximum Ratings
Supply Voltage VDD_P to GND_P, VDD_TX to GND_TX, VDD_IO to GND_IO . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V VDD_CDR to GND_CDR, VDD_CR to GND_CR . . -0.5V to 2.5V Between any pair of GND_P, GND_TX, GND_IO, GND_CDR, GND_CR . . . . . . . . . . . . . -0.1V to 0.1V 3.3V Tolerant LVTTL/LVCMOS Input Voltage . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V Differential Input Voltage . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V Differential Output Current . . . . . . . . . . . . . . Short Circuit Protected LVTTL/LVCMOS Outputs . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating Human Body Model All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4kV SERIOP/N (all VDD Connected, all GND Connected) . . . . .8kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA JC (C/W) EPTQFP. . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. SYMBOL CONDITIONS MIN TYP MAX UNITS
PARAMETER POWER SUPPLY VOLTAGE VDD_CDR, VDD_CR VDD_TX, VDD_P, VDD_AN, VDD_IO SERIALIZER POWER SUPPLY CURRENTS Analog TX Supply Current Analog CDR Supply Current Digital I/O Supply Current Digital Supply Current PLL/VCO Supply Current Analog Bias Supply Current Total 1.8V Supply Current Total 3.3V Supply Current DESERIALIZER POWER SUPPLY CURRENTS Analog TX Supply Current Analog CDR Supply Current Digital I/O Supply Current Digital Supply Current PLL/VCO Supply Current Analog Bias Supply Current Total 1.8V Supply Current Total 3.3V Supply Current
1.7 3.0
1.8 3.3
1.9 3.6
V V
IDDTX IDDCDR IDDIO IDDCR IDDP IDDAN
VIDEO_TX = 1 PCLK_IN = 40MHz
17 57 1 20 17 5.5 77 40 90 46 2
mA mA mA mA mA mA mA mA
IDDTX IDDCDR IDDIO IDDCR IDDP IDDAN
VIDEO_TX = 0 REF_CLK = 40MHz
24 45 17 32 17 5.4 77 64 90 80 25
mA mA mA mA mA mA mA mA
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ISL34341
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. (Continued) SYMBOL CONDITIONS MIN TYP MAX UNITS
PARAMETER POWER-DOWN SUPPLY CURRENT Total 1.8V Power-Down Supply Current Total 3.3V Power-Down Supply Current PARALLEL INTERFACE High Level Input Voltage Low Level Input Voltage Input Leakage Current High Level Output Voltage Low Level Output Voltage Output Short Circuit Current Output Rise and Fall Times
RSTB = GND; spec is per device
0.5 1
mA mA
VIH VIL IIN VOH VOL IOSC tOR/tOF Slew rate control set to min, CL = 8pF Slew rate control set to max, CL = 8pF
2.0 0.8 -10 IOH = -2.0mA, VDD_IO = 3V 0.8*VDD_IO IOL = 2.0mA, VDD_IO = 3V 0.2*VDD_IO 50 1 4 0.01 10
V V A V V mA ns ns
SERIALIZER PARALLEL INTERFACE PCLK_IN Frequency PCLK_IN Duty Cycle Parallel Input Setup Time Parallel Input Hold Time DESERIALIZER PARALLEL INTERFACE PCLK_OUT Frequency PCLK_OUT Duty Cycle PCLK_OUT Period Jitter (rms) PCLK_OUT Spread Width Time to Parallel Output Data Valid Deserializer Output Latency fOUT tODC tOJ tOSPRD tDV tCPD Clock randomizer off Clock randomizer on Relative to PCLK_OUT Part-to-part, side-channel disabled -4.7 4 9 6 50 0.5 20 5.5 14 40 MHz % %tPCLK %tPCLK ns PCLK fIN tIDC tIS tIH 6 40 3.6 1.6 50 40 60 MHz % ns ns
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN) REF_CLK Lock Time REF_CLK to PCLK_OUT Maximum Frequency Offset HIGH-SPEED TRANSMITTER HS Differential Output Voltage, Transition Bit VODTR TXCN = 0x00 TXCN = 0x0F TXCN = 0xF0 TXCN = 0xFF HS Differential Output Voltage, Non-Transition Bit VODNTR TXCN = 0x00 TXCN = 0x0F TXCN = 0xF0 TXCN = 0xFF 600 600 825 1170 975 1300 825 460 975 600 990 990 mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P tPLL PCLK_OUT is the recovered clock 1500 100 5000 s ppm
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ISL34341
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. (Continued) SYMBOL VOCM VCM ROUT tLPD tR/tF tSKEW tRJ tDJ Part-to-part 20% to 80% 80 4 CONDITIONS MIN TYP 2.35 20 100 7 150 <10 13.4 40 120 120 10 MAX UNITS V mV PCLK ps ps psrms psP-P
PARAMETER HS Generated Output Common Mode Voltage HS Common Mode Serializer-Deserializer Voltage Difference HS Differential Output Impedance HS Output Latency HS Output Rise and Fall Times HS Differential Skew HS Output Random Jitter HS Output Deterministic Jitter HIGH SPEED RECEIVER HS Differential Input Voltage HS Generated Input Common Mode Voltage HS Differential Input Impedance HS Maximum Jitter Tolerance I2C I2C Clock Rate (on SCL) I2C Clock Pulse Width (HI or LO) I2C Clock Low to Data Out Valid I2C Start/Stop Setup/Hold Time I2C Data in Setup Time I2C Data in Hold Time I2C Data out Hold Time
VID VICM RIN
150 2.32 80 100 0.52 120
mVP-P V UIP-P
fI2C 1.3 0 0.6 100 100 100
100
400
kHz s
1
s s ns ns ms
Pin Descriptions
DESCRIPTION PIN NUMBER 52 to 63, 2 to 13 22 23 21 26 51 41, 40 24 PIN NAME SERIALIZER DESERIALIZER Parallel video data LVCMOS outputs Horizontal (line) Sync LVCMOS output Vertical (frame) Sync LVCMOS output Video Data Enable LVCMOS output PLL reference clock LVCMOS input Recovered clock LVCMOS output High speed differential serial I/O
RGBA[7:0], Parallel video data LVCMOS inputs RGBB[7:0], RGBC[7:0] HSYNC VSYNC DATAEN PCLK_IN PCLK_OUT SERIOP, SERION HSYNCPOL Horizontal (line) Sync LVCMOS input Vertical (frame) Sync LVCMOS input Video Data Enable LVCMOS input Pixel clock LVCMOS input Default; not used High speed differential serial I/O CMOS input for HSYNC 1: HSYNC is active low 0: HSYNC is active high CMOS input for VSYNC 1: VSYNC is active low 0: VSYNC is active high
25
VSYNCPOL
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ISL34341 Pin Descriptions (Continued)
DESCRIPTION PIN NUMBER 49 PIN NAME VIDEO_TX SERIALIZER CMOS input for video flow direction 1: video serializer 0: video deserializer I2C Interface Pins (I2C DATA, I2C CLK) I2C Device Address I2C Master Mode 1: Master 0: Slave CMOS input for Reset and Power-down. For normal operation, this pin must be forced high. When this pin is forced low, the device will be reset. If this pin stays low, the device will be in PD mode. CMOS output for Receiver Status: 1: Valid 8b/10b data received 0: otherwise Note: serializer and deserializer switch roles during side-channel reverse traffic Analog bias setting resistor connection; use 3.16k 1% to ground PLL Ground Digital (Parallel and Control) Ground Analog (Serial) Data Recovery Ground Analog (Serial) Output Ground Analog Bias Ground Core Logic Ground Core Logic VDD Analog (Serial) Output VDD Analog Bias VDD Analog (Serial) Data Recovery VDD Digital (Parallel and Control) VDD PLL VDD Must be connected to ground Must be connected to ground DESERIALIZER
29, 30 31 to 34 35
SCL, SDA I2CA[3:0] MASTER
16 14
RSTB/PDB STATUS
36 27 48, 64 44, 45 39, 42 37 17, 18 19, 20 43 38 46, 47 1, 50 28 15 Exposed Pad NOTES:
REF_RES GND_P GND_IO GND_CDR GND_TX GND_AN GND_CR VDD_CR VDD_TX VDD_AN VDD_CDR VDD_IO VDD_P TEST_EN Exposed Pad
3. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external components or features. 4. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are provided to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they should be considered a common connection.
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ISL34341 Diagrams
VODTR VODNTR
TXCN 0x00 0x0F 0xF0 0xFF
FIGURE 1. VOD vs TXCN SETTING
VIDEO_TX = 1
PCLK_IN tIS RGB[A:C][7:0]
1/fIN
tIDC
tIH VALID DATA VALID DATA DATA IGNORED DATA IGNORED VALID DATA
tIS HSYNC VSYNC
tIH
DATAEN
FIGURE 2. PARALLEL VIDEO INPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg) = 0]
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ISL34341
VIDEO_TX = 0
PCLK_OUT tDV RGB[A:C][7:0] VALID DATA VALID DATA DATA HELD AT PREVIOUS VALUE VALID DATA tOF TODC
1/fOUT
tOR
tDV HSYNC VSYNC
DATAEN
FIGURE 3. PARALLEL VIDEO OUTPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg) = 0]
Applications
Overview
A pair of ISL34341 SERDES transports 24-bit parallel video (16-bit parallel video for the ISL34321) along with auxiliary data over a single 100 differential cable either to a display or from a camera. Auxiliary data is transferred in both directions and can be used for remote configuration and telemetry. The benefits include lower EMI, lower costs, greater reliability and space savings. The same device can be configured to be either a serializer or deserializer by setting one pin (VIDEO_TX), simplifying inventory. RGBA/B/C, VSYNC, HSYNC, and DATAEN pins are inputs in serializer mode and outputs in deserializer mode. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer. The Side Channel data is transferred between the SERDES pair during two lines of the vertical video blanking interval. When the side-channel is enabled, there will be a number of PCLK cycles uncertainty from frame-to-frame. This should not cause sync problems with most displays, as this occurs during the vertical front porch of the blanking period. When properly configured, the SERDES link supports end-to-end transport with fewer than one error in 1010 bits.
The high bit rate of the differential serial data requires special care in the layout of traces on PCBs, in the choice and assembly of connectors, and in the cables themselves. PCB traces need to be adjacent and matched in length (so as to minimize the imbalanced coupling to other traces or elements) and of a geometry to match the impedance of the transmitter and receiver to minimize reflections. Similar care needs to be applied to the choice of connectors and cables. SERIOP and SERION pins incorporate internal differential termination of the serial signal lines.
SERIO Pin AC-Coupling
AC-coupling minimizes the effects of DC common mode voltage difference and local power supply variations between two SERDES. The serializer outputs DC balanced 8b/10b line code, which allows AC-coupling. The AC-coupling capacitor on SERIO pins must be 27nF on the serializer board and 27nF on the deserializer board. The value of the AC-coupling capacitor is very critical since a value too small will attenuate the high speed signal at low clock rate. A value too big will slow down the turn around time for the side-channel.
Receiver Reference Clock (REF_CLK)
The reference clock (REF_CLK) for the PLL is fed into PCLK_IN pin. REF_CLK is used to recover the clock from the high speed serial stream. REF_CLK is very sensitive to any instability. The following conditions must be met at all times after power is applied to the deserializer, or else the deserializer may need a manual reset: * REF_CLK frequency must be within the limits specified * REF_CLK amplitude must be stable. A simple 3.3V CMOS crystal oscillator can be used for REF_CLK.
Differential Signals and Termination
The ISL34341 serializes the 24-bit parallel data along with 3 sync signals at 30x the PCLK_IN frequency. The ISL34321 serializes the 16-bit parallel data plus 3 sync signals at 20x the PCLK_IN frequency. The extra 2 bits per word come from the 8b/10b encoding scheme which helps create the highest quality serial link.
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ISL34341
Power Supply Sequencing
The 3.3V supply must be higher than the 1.8V supply at all times, including during power-up and power-down. To meet this requirement, the 3.3V supply must be powered up before the 1.8V supply. For the deserializer, REF_CLK must not be applied before the device is fully powered up. Applying REF_CLK before power-up may require the deserializer to be manually reset. A 10ms delay after the 1.8V supply is powered up guarantees normal operation. supplies are tied together, the PCB layout should be arranged to emulate this arrangement, at least for the smaller value (high frequency) capacitors, as much as possible.
Power Supply Bypassing
The serializer and deserializer functions rely on the stable functioning of PLLs locked to local reference sources or locked to an incoming signal. It is important that the various supplies (VDD_P, VDD_AN, VDD_CDR, VDD_TX) be well bypassed over a wide range of frequencies, from below the typical loop bandwidth of the PLL to approaching the signal bit rate of the serial data. A combination of different values of capacitors from 1000pF to 5F or more with low ESR characteristics is generally required. The parallel LVCMOS VDD_IO supply is inherently less sensitive, but since the RGB and SYNC/DATAEN signals can all swing on the same clock edge, the current in these pins and the corresponding GND pins can undergo substantial current flow changes, so once again, a combination of different values of capacitors over a wide range, with low ESR characteristics, is desirable. A set of arrangements of this type is shown in Figure 4, where each supply is bypassed with a ferrite-bead-based choke, and a range of capacitors. A "choke" is preferable to an "inductor" in this application, since a high-Q inductor will be likely to cause one or more resonances with the shunt capacitors. This potentially causes problems at or near those frequencies, while a "lossy" choke will reflect a high impedance over a wide frequency range. The higher value capacitor, in particular, needs to be chosen carefully with special care regarding its ESR. Very good results can be obtained with multilayer ceramic capacitors, available from many suppliers, and generally in small outlines (such as the 1210 outline suggested in the schematic shown in Figure 4), which provide good bypass capabilities down to a few m at 1MHz to 2MHz. Other capacitor technologies may also be suitable (perhaps niobium oxide), but "classic" electrolytic capacitors frequently have ESR values of above 1, that nullify any decoupling effect above the 1kHz to 10kHz frequency range. Capacitors of 0.1F offer low impedance in the 10MHz to 20MHz region, and 1000pF capacitors in the 100MHz to 200MHz region. In general, one of the lower value capacitors should be used at each supply pin on the IC. Figure 4 shows the grounding of the various capacitors to the pin corresponding to the supply pin. Although all the ground
FIGURE 4. POWER SUPPLY BYPASSING
I2C Interface
The I2C interface allows access to internal registers used to configure the SERDES and to obtain status information. A serializer must be assigned a different address than its deserializer counterpart. The upper 3 bits are permanently set to 011 and the lower 4 bits determined by pins as follows:
0 1 1 I2CA3 I2CA2 I2CA1 I2CA0 R/W
Thus, 16 SERDES can reside on the same bus. By convention, when all address pins are tied low, the device address is referred to as 0x60. SCL and SDA are open drain to allow multiple devices to share the bus. If not used, SCL and SDA should be tied to VDD_IO.
Side Channel Interface
The Side Channel is a mechanism for transferring data between the two chips on each end of the link. This data is transferred during video blanking so none of the video bandwidth is used. It has three basic uses: * Data exchanges between two processors * Master Mode I2C commands to remote slaves * Remote SERDES configuration This interface allows the user to initialize registers, control and monitor both SERDES chips from a single micro-controller which can reside on either side of the serial link. This feature is used to automatically transport the remote side chip's status which is available in a local register. The Side Channel needs to be enabled for this to work which is the default mode. In the case where there is a
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ISL34341
micro-controller on each side of the of the link data can be buffered and exchanged between the two. Up to 224 bytes can be sent in each direction during each VSYNC active period.
Master Mode
This is a mode activated by strapping the MASTER pin to a `1' on the 34341 on the remote side of the controller. This is a virtual extension of the I2C interface across the link that allows the local processor to read and write slave devices connected to the remote side I2C bus. No additional wires or components are needed other than the serial link. The I2C commands and data are transferred during video blanking causing no interruptions in the video data. Data is transported by the Side Channel across the link so the maximum throughput would be the same.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN6827.0 December 15, 2008
ISL34341 Thin Plastic Quad Flatpack Exposed Pad Plastic Packages (EPTQFP)
D D1 -D-
Q64.10x10C (JEDEC MS-026ACD-HU ISSUE D) 64 LEAD THIN PLASTIC QUAD FLATPACK EXPOSED PAD PACKAGE
MILLIMETERS SYMBOL MIN 0.05 0.95 0.16 0.17 11.80 9.90 2.90 11.80 9.90 2.90 0.45 64 0.50 BSC MAX 1.20 0.15 1.05 0.28 0.23 12.20 10.10 3.10 12.20 10.10 3.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 0 10/08
11o-13o
EJECTOR PIN MARK NOT PIN #1 ID -A-B-
A A1 A2 b b1
E E1
D D1 D2
e
E E1 E2 L N
PIN 1 TOP VIEW
e NOTES:
0.020 0.008 MIN 0o MIN GAGE PLANE 0o-7o L 0.25 0.010 A2 A1
1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. "N" is the number of terminal positions.
11o-13o
PIN 1
EJECTOR PIN MARK NOT PIN #1 ID -HA SEATING PLANE 0.08 0.003 -C0.08 M 0.003 EJECTOR PIN MARK NOT PIN #1 ID 0.09/0.16 0.004/0.006 BASE METAL WITH PLATING C A-B S DS b b1
E2
D2 BOTTOM VIEW
0.09/0.20 0.004/0.008
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