View AD9572ACPZPEC-R7_4507892.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs AD9572
FEATURES
Fully integrated dual VCO/PLL cores 167 fs rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz 178 fs rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz 418 fs rms jitter from 12 kHz to 20 MHz at 125 MHz Input crystal or clock frequency of 25 MHz Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz, 100 MHz, 125 MHz Choice of LVPECL or LVDS output format Integrated loop filters Copy of reference clock output Rates configured via strapping pins Space saving, 6 mm x 6 mm, 40-lead LFCSP 0.71 W power dissipation (LVDS operation) 1.07 W power dissipation (LVPECL operation) 3.3 V operation
FUNCTIONAL BLOCK DIAGRAM
REFSEL XTAL OSC REFCLK LDO
CMOS 1 x 25MHz LVPECL OR LVDS
LPF 3RD ORDER
VCO
DIVIDERS
PFD/CP
2 x 106.25MHz
LVPECL OR LVDS 1 x 156.25MHz LDO LVPECL OR LVDS
LPF 3RD ORDER
VCO
DIVIDERS
PFD/CP
2 x 100MHz OR 125MHz CMOS
APPLICATIONS
Fiber channel line cards, switches, and routers Gigabit Ethernet/PCIe support included Low jitter, low phase noise clock generation
AD9572
FREQSEL
1 x 33.33MHz FORCE_LOW
07498-001
Figure 1.
GENERAL DESCRIPTION
The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed
feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference. Each output divider and feedback divider ratio is preprogrammed for the required output rates. A second PLL also operates as an integer-N synthesizer and drives two LVPECL or LVDS output buffers for 106.25 MHz operation. No external loop filter components are required, thus conserving valuable design time and board space. The AD9572 is available in a 40-lead, 6 mm x 6 mm lead frame chip scale package (LFCSP) and can be operated from a single 3.3 V supply. The temperature range is -40C to +85C.
10G SFP+
CPU ISLAND 1 x 156.25MHz 2 x 106.25MHz 1 x 100MHz/125MHz 1 x 25MHz 1 x 33.33MHz
16-PORT FIBRE CHANNEL ASIC
AD9572
07498-002
QUAD SFP PHY
QUAD SFP PHY
QUAD SFP PHY
QUAD SFP PHY
Figure 2. Typical Application
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
AD9572 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 PLL Characteristics ...................................................................... 3 LVDS Clock Output Jitter............................................................ 4 LVPECL Clock Output Jitter ....................................................... 5 CMOS Clock Output Jitter .......................................................... 5 Reference Input ............................................................................. 5 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 6 Control Pins .................................................................................. 7 Power .............................................................................................. 7 Crystal Oscillator .......................................................................... 7 Timing Diagrams .............................................................................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution...................................................................................9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 12 Terminology .................................................................................... 13 Theory of Operation ...................................................................... 14 Outputs ........................................................................................ 14 Phase Frequency Detector (PFD) and Charge Pump............ 15 Power Supply............................................................................... 15 CMOS Clock Distribution ........................................................ 15 LVPECL Clock Distribution ..................................................... 16 LVDS Clock Distribution .......................................................... 16 Reference Input........................................................................... 16 Power and Grounding Considerations and Power Supply Rejection ...................................................................................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17
REVISION HISTORY
7/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD9572 SPECIFICATIONS
PLL CHARACTERISTICS
Typical (typ) is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 1.
Parameter PHASE NOISE CHARACTERISTICS PLL Noise (106.25 MHz LVDS Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz PLL Noise (156.25 MHz LVDS Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz PLL Noise (125 MHz LVDS Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz PLL Noise (100 MHz LVDS Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz PLL Noise (106.25 MHz LVPECL Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz PLL Noise (156.25 MHz LVPECL Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz Min Typ Max Unit Test Conditions/Comments
-123 -127 -129 -150 -152 -153 -118 -125 -126 -145 -151 -151 -119 -127 -128 -147 -151 -152 -121 -128 -130 -147 -150 -150 -121 -128 -129 -151 -154 -155 -119 -125 -126 -147 -152 -153
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled
Rev. 0 | Page 3 of 20
AD9572
Parameter PLL Noise (125 MHz LVPECL Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz PLL Noise (100 MHz LVPECL Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz Phase Noise (33.33 MHz CMOS Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 5 MHz Phase Noise (25 MHz CMOS Output) @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 5 MHz Spurious Content 1 PLL Figures of Merit
1
Min
Typ -122 -127 -128 -148 -152 -153 -122 -128 -130 -148 -150 -151 -130 -138 -139 -152 -152 -133 -142 -148 -148 -148 -70 -217.5
Max
Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc/Hz
Test Conditions/Comments 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled
Dominant amplitude with all outputs active
When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case -50 dBc spurious content might be presented on Pin 21 and Pin 22 only.
LVDS CLOCK OUTPUT JITTER
Typical (typ) is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 2.
Jitter Integration Bandwidth (Typ) 12 kHz to 20 MHz 100 MHz 33M = Off/On 508/490 106.25 MHz 33M = Off/On 402/440 125 MHz 33M = Off/On 418/883 156.25 MHz 33M = Off/On 417/423 Unit fS rms Test Conditions/Comments LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 2 x 125 MHz, 2 x 106.25 MHz
1.875 MHz to 20 MHz 637 kHz to 10 MHz 167/217
178/185
fS rms
fS rms
200 kHz to 10 MHz
316/308
253/776
fS rms
12 kHz to 35 MHz
500 (off only)
fS rms
Rev. 0 | Page 4 of 20
AD9572
LVPECL CLOCK OUTPUT JITTER
Typical (typ) is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 3.
Jitter Integration Bandwidth (Typ) 12 kHz to 20 MHz 100 MHz 33M = Off/On 608/564 106.25 MHz 33M = Off/On 418/451 125 MHz 33M = Off/On 444/2200 156.25 MHz 33M = Off/On 420/461 Unit fS rms Test Conditions/Comments LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 2 x 125 MHz, 2 x 106.25 MHz
1.875 MHz to 20 MHz 637 kHz to 10 MHz 227/232
200/277
fS rms
fS rms
200 kHz to 10 MHz
337/378
242/2200
fS rms
12 kHz to 35 MHz
523 (off only)
fS rms
CMOS CLOCK OUTPUT JITTER
Typical (typ) is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 4.
Jitter Integration Bandwidth 12 kHz to 5 MHz 200 kHz to 5 MHz 25 MHz 781 764 33.3 MHz 417 524 Unit fS rms fS rms Test Conditions/Comments
REFERENCE INPUT
Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 5.
Parameter CLOCK INPUT (REFCLK) Input Frequency Input High Voltage Input Low Voltage Input Current Input Capacitance Min Typ 25 2.0 -1.0 2 0.8 +1.0 Max Unit MHz V V A pF Test Conditions/Comments
Rev. 0 | Page 5 of 20
AD9572
CLOCK OUTPUTS
Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 6.
Parameter LVPECL CLOCK OUTPUTS Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Output Differential Voltage (VOD) Duty Cycle LVDS CLOCK OUTPUTS Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) Duty Cycle CMOS CLOCK OUTPUTS Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Duty Cycle Min Typ Max 156.25 VS - 0.83 VS - 1.62 950 55 156.25 475 25 1.375 25 24 55 33.33 VS - 0.1 42 0.1 58 Unit MHz V V mV % MHz mV mV V mV mA % MHz V V % Test Conditions/Comments
VS - 1.24 VS - 2.07 700 45
VS - 1.05 VS - 1.87 825
250 1.125
350 1.25 14
Output shorted to GND
45
Sourcing 1.0 mA current Sinking 1.0 mA current
TIMING CHARACTERISTICS
Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 7.
Parameter LVPECL Output Rise Time, tRP Output Fall Time, tFP LVDS Output Rise Time, tRL Output Fall Time, tFL CMOS Output Rise Time, tRC Output Fall Time, tFC Min 480 480 160 160 0.25 0.25 Typ 625 625 350 350 0.50 0.70 Max 810 810 540 540 2.5 2.5 Unit ps ps ps ps ns ns Test Conditions/Comments Termination = 200 to 0 V; CLOAD = 0 pF 20% to 80%, measured differentially 80% to 20%, measured differentially Termination = 100 differential; CLOAD = 0 pF 20% to 80%, measured differentially 80% to 20%, measured differentially Termination = 50 to 0 V; CLOAD = 5 pF 20% to 80% 80% to 20%
Rev. 0 | Page 6 of 20
AD9572
CONTROL PINS
Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 8.
Parameter INPUT CHARACTERISTICS REFSEL Pin Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current FREQSEL Pin Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current FORCE_LOW Pin Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Min Typ Max Unit Test Conditions/Comments REFSEL has a 30 k pull-up resistor. 2.0 0.8 1.0 155 V V A A FREQSEL has a 150 k pull-up resistor and a 100 k pull-down resistor. 2/3(VS) + 0.2 1/3(VS) - 0.2 45 30 2.0 0.8 240 2.0 V V A A FORCE_LOW has a 16 k pull-down resistor. V V A A
POWER
Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 9.
Parameter Power Supply LVDS Power Dissipation LVPECL Power Dissipation Min 3.0 Typ 3.3 715 1075 Max 3.6 870 1305 Unit V mW mW Test Conditions/Comments
CRYSTAL OSCILLATOR
Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 10.
Parameter CRYSTAL SPECIFICATION Frequency ESR Load Capacitance Phase Noise Stability Min Typ 25 50 14 -135 -30 +30 Max Unit MHz pF dBc/Hz ppm Test Conditions/Comments Fundamental mode
@ 1 kHz offset
Rev. 0 | Page 7 of 20
AD9572 TIMING DIAGRAMS
DIFFERENTIAL 80% LVPECL 20%
07498-004
SINGLE-ENDED 80% CMOS 5pF LOAD 20%
07498-006
tRP
tFP
tRC
tFC
Figure 3. LVPECL Timing, Differential
Figure 5. CMOS Timing, Single-Ended, 5 pF Load
DIFFERENTIAL 80% LVDS 20%
07498-005
tRL
tFL
Figure 4. LVDS Timing, Differential
Rev. 0 | Page 8 of 20
AD9572 ABSOLUTE MAXIMUM RATINGS
Table 11.
Parameter VS to GND REFCLK to GND BYPASSx to GND XO to GND FREQSEL, FORCE_LOW, and REFSEL to GND 25M, 33M, 100M/125M, 106M, and 156M to GND Junction Temperature1 Storage Temperature Range
1
THERMAL RESISTANCE
Rating -0.3 V to +3.6 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V 150C -65C to +150C
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-7. Table 12. Thermal Resistance
Package Type 40-Lead LFCSP JA 27.5 Unit C/W
ESD CAUTION
See Table 12 for JA.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 9 of 20
AD9572 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VS VS * FORCE_LO W BYPASS1 VS GND VS 106M 106M
GND 1 VS 2 NC 3 25M 4 VS 5 XO 6 XO 7 REFCLK 8 REFSEL 9 GND 10
40 39 38 37 36 35 34 33 32 31
PIN 1 INDICATOR
AD9572
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
106M 106M VS FREQSEL VS VS VS 33M 100M/125M 100M/125M
Figure 6. Pin Configuration
Table 13. Pin Function Descriptions 1
Pin No. 3 2 4 5 6, 7 8 9 11 1, 10, 34 14, 36 15 16 17 18 19, 21 20, 22 23 24 25 26 27 28 29, 31 30, 32 Mnemonic NC VS 25M VS XO REFCLK REFSEL VS GND BYPASS2, BYPASS1 VS VS 156M 156M 100M/125M 100M/125M 33M VS VS VS FREQSEL VS 106M 106M Description No Connect. This pin should be left floating. Power Supply Connection for the 25M CMOS Buffer. CMOS 25 MHz Output. Power Supply Connection for the Crystal Oscillator. External 25 MHz Crystal. 25 MHz Reference Clock Input. Tie low when not in use. Logic Input. Used to select the reference source. Power Supply Connection for the GbE PLL. Ground. Includes external paddle (EPAD). These pins are for bypassing each LDO to ground with a 220 nF capacitor. Power Supply Connection for the GbE VCO. Power Supply Connection for the 156M LVDS Output Buffer and Output Dividers. LVPECL/LVDS Output at 156.25 MHz. Complementary LVPECL/LVDS Output at 156.25 MHz. LVPECL/LVDS Output at 100 MHz or 125 MHz. Selected by FREQSEL pin strapping. Complementary LVPECL/LVDS Output at 100 MHz or 125 MHz. CMOS 33.33 MHz Output. Power Supply Connection for the 33M CMOS Output Buffer and Output Dividers. Power Supply Connection for the 100M/125M LVDS Output Buffer and Output Dividers. Power Supply Connection for the GbE PLL Feedback Divider. Logic Input. Used to configure output drivers. Power Supply Connection for the FC PLL Feedback Divider. LVPECL/LVDS Output at 106.25 MHz. Complementary LVPECL/LVDS Output at 106.25 MHz.
Rev. 0 | Page 10 of 20
07498-007
NOTES 1. * = SHORT TO PIN 36. 2. ** = SHORT TO PIN 14. 3. NC = NO CONNECT. 4. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND).
VS ** ** BYPASS2 VS VS 156M 156M 100M/125M 100M/125M
11 12 13 14 15 16 17 18 19 20
AD9572
Pin No. 33 35 37 39 40
1
Mnemonic VS VS FORCE_LOW VS VS
Description Power Supply Connection for the 106.25 MHz LVDS Output Buffer and Output Dividers. Power Supply Connection for the FC VCO. Forces the 33.33 MHz output into a low state. Power Supply Connection for the FC PLL. Power Supply Connection for Miscellaneous Logic.
The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground (GND).
Rev. 0 | Page 11 of 20
AD9572 TYPICAL PERFORMANCE CHARACTERISTICS
Both 100 MHz and 125 MHz outputs enabled; 33.3 MHz output disabled.
-100 -100
-110
PHASE NOISE (dBc/Hz)
-110
PHASE NOISE (dBc/Hz)
07498-008
-120
-120
-130
-130
-140
-140
-150
-150
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. 106.25 MHz Phase Noise
-100 -100
Figure 10. 156.25 MHz Phase Noise
-110
PHASE NOISE (dBc/Hz)
-110
PHASE NOISE (dBc/Hz)
-120
-120
-130
-130
-140
-140
-150
-150
07498-009
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. 125 MHz Phase Noise
-100
Figure 11. 100 MHz Phase Noise
-110
PHASE NOISE (dBc/Hz)
-120
-130
-140
-150
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 9. 25 MHz Phase Noise
07498-010
-160 1k
Rev. 0 | Page 12 of 20
07498-012
-160 1k
-160 1k
07498-011
-160 1k
-160 1k
AD9572 TERMINOLOGY
Phase Jitter An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. Actual signals, however, display a certain amount of variation from the ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. Phase Noise When the total power contained within some interval of offset frequencies (for example, 12 kHz to 20 MHz) is integrated, it is called the integrated phase noise over that frequency offset interval, and it can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on error rate performance by increasing eye closure at the transmitter output and reducing the jitter tolerance/sensitivity of the receiver. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. In a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the gaussian distribution. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillator or clock source has been subtracted. This makes it possible to predict the degree to which the device will impact the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
Rev. 0 | Page 13 of 20
AD9572 THEORY OF OPERATION
REFSEL VS XTAL OSC REFCLK BYPASS1 VS GND CMOS 25M
1 0
PHASE FREQUENCY DETECTOR
LDO DIVIDE BY 17 106.25MHz 106M 106M DIVIDE BY 4 LVPECL/ LVDS 106M 106M
CHARGE PUMP VCO VLDO PHASE FREQUENCY DETECTOR LDO
DIVIDE BY 5
BYPASS2 DIVIDE BY 25 156.25MHz 156M 156M
CHARGE PUMP VCO VLDO
DIVIDE BY 4
DIVIDE BY 4 LVPECL/ LVDS
DIVIDE BY 5
DIVIDE BY 4
0 1
125MHz/100MHz LVPECL/ LVDS
100M/125M 100M/125M
LEVEL DECODE 125MHz/100MHz LVPECL/ LVDS 33.33MHz
FREQSEL
DIVIDE BY 5
0 1
100M/125M 100M/125M
AD9572
DIVIDE BY 3
33M
07498-013
CMOS
FORCE_LOW
Figure 12. Detailed Block Diagram
Figure 12 shows a block diagram of the AD9572. The chip combines dual PLL cores, which are configured to generate the specific clock frequencies required for networking applications, without any user programming. This PLL is based on proven Analog Devices synthesizer technology, noted for its exceptional phase noise performance. The AD9572 is highly integrated and includes loop filters, regulators for supply noise immunity, all the necessary dividers with multiple output buffers in a choice of formats, and a crystal oscillator. A user need only supply a 25 MHz reference clock or an external crystal to implement an entire line card clocking solution that does not require any processor intervention. A copy of the 25 MHz reference source is also available.
OUTPUTS
Table 14 provides a summary of the outputs available. Table 14. Output Formats
Frequency 25 MHz 106.25 MHz 156.25 MHz 100 MHz or 125 MHz 33.33 MHz Format CMOS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS CMOS Copies 1 2 1 2 1
Note that the pins labeled 100M/125M can provide 100 MHz or 125 MHz by strapping the FREQSEL pin as shown in Table 15.
Rev. 0 | Page 14 of 20
AD9572
Table 15. FREQSEL (Pin 27) Definition
Frequency Available from Pin 19 and Pin 20 (MHZ) 125 100 125
3.5mA
FREQSEL 0 1 NC
Frequency Available from Pin 21 and Pin 22 (MHZ) 125 100 100
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
The PFD takes inputs from the reference clock and feedback divider to produce an output proportional to the phase and frequency difference between them. Figure 15 shows a simplified schematic.
3.3V CHARGE PUMP
HIGH REFCLK
D1 Q1 CLR1
UP
OUT OUTB
CP
07498-014
3.5mA
HIGH FEEDBACK DIVIDER
CLR2 DOWN D2 Q2
Figure 13. LVDS Output Simplified Equivalent Circuit
The simplified equivalent circuits of the LVDS and LVPECL outputs are shown in Figure 13 and Figure 14.
3.3V
GND
Figure 15. PFD Simplified Schematic
POWER SUPPLY
The AD9572 requires a 3.3 V 10% power supply for VS. The tables in the Specifications section give the performance expected from the AD9572 with the power supply voltage within this range. The absolute maximum range of -0.3 V to +3.6 V, with respect to GND, must never be exceeded on the VS pin. Good engineering practice should be followed in the layout of power supply traces and the ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 F). The AD9572 should be bypassed with adequate capacitors (0.1 F) at all power pins as close as possible to the part. The layout of the AD9572 evaluation board is a good example. The exposed metal paddle on the AD9572 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The PCB acts as a heat sink for the AD9572; therefore, this GND connection should provide a good thermal path to a larger dissipation area, such as a ground plane on the PCB.
OUT OUTB
GND
Figure 14. LVPECL Output Simplified Equivalent Circuit
The differential outputs are factory programmed to either LVPECL or LVDS format, and either option can be sampled on request. CMOS drivers tend to generate more noise than differential outputs and, as a result, the proximity of the 33.33 MHz output to Pin 21 and Pin 22 does affect the jitter performance when FREQSEL = 0 (that is, when the differential output is generating 125 MHz). For this reason, the 33 MHz pin can be forced to a low state by asserting the FORCE_LOW signal on Pin 37 (see Table 16). An internal pull-down enables the 33.33 MHz output if the pin is not connected. Table 16. FORCE_LOW (Pin 37) Definition
FORCE_LOW 0 or NC 1 33.33 MHz Output (Pin 23) 33.33 MHz 0
07498-015
CMOS CLOCK DISTRIBUTION
The AD9572 provides two CMOS clock outputs (one 25 MHz and one 33.33 MHz) that are dedicated CMOS levels. Whenever single-ended CMOS clocking is used, some of the following general guidelines should be followed. Point-to-point nets should be designed such that a driver has one receiver only on the net, if possible. This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver.
Rev. 0 | Page 15 of 20
07498-016
AD9572
The value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). CMOS outputs are limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 6 inches are recommended to preserve signal rise/fall times and signal integrity.
CMOS 10 60.4 1.0 INCH MICROSTRIP
07498-017
3.3V 0.1nF DIFFERENTIAL (COUPLED)
3.3V
LVPECL
0.1nF 200
100
LVPECL
Figure 19. LVPECL with Parallel Transmission Line
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is a second differential output option for the AD9572. LVDS uses a current mode output stage with a factory programmed current level. The normal value (default) for this current is 3.5 mA, which yields a 350 mV output swing across a 100 resistor. The LVDS outputs meet or exceed all ANSI/TIA/EIA-644 specifications. A recommended termination circuit for the LVDS outputs is shown in Figure 20.
50
07498-021
5pF GND
Figure 16. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9572 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 17. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.
VPULLUP = 3.3V 50 100 100 5pF
07498-018
LVDS 50
100
LVDS
Figure 20. LVDS Output Termination
CMOS
10
See the AN-586 Application Note on the Analog Devices website at www.analog.com for more information about LVDS.
REFERENCE INPUT
By default, the crystal oscillator is enabled and used as the reference source, which requires the connection of an external 25 MHz crystal. The REFSEL pin is pulled high internally by about 30 k to support default operation. When REFSEL is tied low, the crystal oscillator is powered down, and the REFCLK pin must provide a good quality 25 MHz reference clock instead. This single-ended input can be driven by either a dc-coupled LVCMOS level signal or an ac-coupled sine wave or square wave, provided that an external divider is used to bias the input at VS/2. Table 17. REFSEL (Pin 9) Definition
REFSEL 0 1 Reference Source REFCLK input Internal crystal oscillator
Figure 17. CMOS Output with Far-End Termination
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled logic (LVPECL) outputs of the AD9572 provide the lowest jitter clock signals available from the AD9572. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 14 shows the LVPECL output stage. In most applications, a standard LVPECL far-end termination is recommended, as shown in Figure 18. The resistor network is designed to match the transmission line impedance (50 ) and the desired switching threshold (1.3 V).
3.3V 3.3V 3.3V
50 SINGLE-ENDED (NOT COUPLED) 50
127
127
POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION
Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the PCB is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as for power supply bypassing and grounding to ensure optimum performance.
LVPECL
LVPECL
Figure 18. LVPECL Far-End Termination
07498-019
VT = VCC - 1.3V
83
83
Rev. 0 | Page 16 of 20
07498-020
200
AD9572 OUTLINE DIMENSIONS
PIN 1 INDICATOR 6.10 6.00 SQ 5.90 0.30 0.25 0.18
31 30 40 1
PIN 1 INDICATOR
*4.80 4.70 SQ 4.50
0.50 BSC
EXPOSED PAD
21
10 11
TOP VIEW 0.80 0.75 0.70
0.45 0.40 0.35
20
BOTTOM VIEW
0.25 MIN
SEATING PLANE
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 21. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm x 6 mm Body, Very Very Thin Quad (CP-40-7) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9572ACPZLVD1, 2 AD9572ACPZLVD-RL1, 2 AD9572ACPZLVD-R71, 2 AD9572ACPZPEC1, 3 AD9572ACPZPEC-RL1, 3 AD9572ACPZPEC-R71, 3 AD9572-EVALZ-LVD1, 2 AD9572-EVALZ-PEC1, 3
1 2
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7" Tape Reel, 2,500 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7" Tape Reel, 750 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7" Tape Reel, 2,500 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7" Tape Reel, 750 Pieces Evaluation Board Evaluation Board
072709-A
Package Option CP-40-7 CP-40-7 CP-40-7 CP-40-7 CP-40-7 CP-40-7
Z = RoHS Compliant Part. LVD indicates LVDS compliant, differential clock outputs. 3 PEC indicates LVPECL compliant, differential clock outputs.
Rev. 0 | Page 17 of 20
AD9572 NOTES
Rev. 0 | Page 18 of 20
AD9572 NOTES
Rev. 0 | Page 19 of 20
AD9572 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07498-0-7/09(0)
Rev. 0 | Page 20 of 20

▲Up To Search▲

Price & Availability of AD9572ACPZPEC-R7

	To Download AD9572ACPZPEC-R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .