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| MCP6566/6R/6U/7/9 1.8V Low Power Open-Drain Output Comparator Features * Propagation Delay at 1.8VDD: - 56 ns (typical) High to Low * Low Quiescent Current: 100 A (typical) * Input Offset Voltage: 3 mV (typical) * Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V * Open-Drain Output * Wide Supply Voltage Range: 1.8V to 5.5V * Available in Single, Dual, and Quad * Packages: SC70, SOT-23-5, SOIC, MSOP, TSSOP Description The Microchip Technology, Inc. MCP6566/6R/6U/7/9 families of Open-Drain output comparators are offered in single, dual and quad configurations. These comparators are optimized for low power 1.8V, single-supply applications with greater than rail-to-rail input operation. The internal input hysteresis eliminates output switching due to internal input noise voltage, reducing current draw. The open-drain output of the MCP6566/6R/6U/7/9 family requires a pull up resistor and it supports pull-up voltages above and below VDD which can be used to level shift. The output toggle frequency can reach a typical of 4 MHz (typical) while limiting supply current surges and dynamic power consumption during switching. This family operates with single supply voltage of 1.8V to 5.5V while drawing less than 100 A/comparator of quiescent current (typical). Typical Applications * * * * * * * Laptop computers Mobile Phones Hand-held Electronics RC Timers Alarm and Monitoring Circuits Window Comparators Multi-vibrators Package Types MCP6566 SOT-23-5, SC70-5 OUT 1 VSS 2 +IN 3 MCP6568 SOIC, MSOP 8 VDD -+ +- Design Aids * Microchip Advanced Part Selector (MAPS) * Analog Demostration and Evaluation Boards * Application Notes 5 VDD OUTA 1 -INA 2 4 -IN 7 OUTB 6 -INB 5 +INB MCP6566R SOT-23-5 OUT 1 VDD 2 +IN 3 5 VSS + - + - +INA 3 VSS 4 MCP6569 SOIC, TSSOP OUTA 1 -INA 2 4 -IN -+ +- Related Device * Push-Pull Output: MCP6561/1R/1U/2/4 14 OUTD 13 -IND 12 +IND 11 VSS 10 +INC -+ +- Typical Application +3VPU VIN VDD R2 RF +5VDD VOUT MCP656X +INA 3 VDD 4 +INB 5 -INB 6 MCP6566U SOT-23-5 + VIN+ 1 VSS 2 VIN- 3 9 -INC 8 OUTC 5 VDD OUTB 7 4 OUT R3 (c) 2009 Microchip Technology Inc. DS22143B-page 1 MCP6566/6R/6U/7/9 NOTES: DS22143B-page 2 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings* VDD - VSS ....................................................................... 6.5V Open-Drain Output.............................................VSS + 10.5V All other inputs and outputs...........VSS - 0.3V to VDD + 0.3V Difference Input voltage ......................................|VDD - VSS| Output Short Circuit Current .................................... 25 mA Current at Input Pins .................................................. 2 mA Current at Output and Supply Pins .......................... 50 mA Storage temperature ................................... -65C to +150C Ambient temp. with power applied .............. -40C to +125C Junction temp............................................................ +150C ESD protection on all pins (HBM/MM) ................. 4 kV/300V *Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = VSS, and RPull-Up = 20 k to VPU = VDD (see Figure 1-1). Parameters Power Supply Supply Voltage Quiescent Current per comparator Power Supply Rejection Ratio Input Input Offset Voltage Input Offset Drift Input Offset Current Input Bias Current VOS VOS/T IOS IB -10 -- -- -- -- -- Input Hysteresis Voltage Input Hysteresis Linear Temp. Co. Input Hysteresis Quadratic Temp. Co. Common-Mode Input Voltage Range Common-Mode Rejection Ratio VHYST TC1 TC2 VCMR CMRR 1.0 -- -- VSS-0.2 VSS-0.3 54 50 54 Common Mode Input Impedance Differential Input Impedance Note 1: 2: 3: 4: ZCM ZDIFF -- -- VDD IQ PSRR 1.8 60 63 -- 100 70 5.5 130 -- +10 -- -- -- -- 5000 5.0 -- -- VDD+0.2 VDD+0.3 -- -- -- -- -- V A dB mV V/C pA pA pA pA mV V/C V/C2 V V dB dB dB ||pF ||pF VDD = 1.8V VDD = 5.5V VCM= -0.3V to VDD+0.3V, VDD = 5.5V VCM= VDD/2 to VDD+0.3V, VDD = 5.5V VCM= -0.3V to VDD/2, VDD = 5.5V IOUT = 0 VCM = VSS VCM = VSS (Note 1) VCM = VSS VCM = VSS TA = +25C, VIN- = VDD/2 TA = +85C, VIN- = VDD/2 TA = +125C, VIN- = VDD/2 VCM = VSS (Notes 1, 2) Symbol Min Typ Max Units Conditions 3 2 1 1 60 1500 -- 10 0.3 -- -- 66 63 65 1013||4 1013||2 The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points. VHYST at different temperatures is estimated using VHYST (TA) = VHYST @ +25C + (TA - 25C) TC1 + (TA - 25C)2 TC2. Limit the output current to Absolute Maximum Rating of 50 mA. The pull up voltage for the open drain output VPULL_UP can be as high as the absolute maximum rating of 10.5V. In this case, IOH_leak can be higher than 1 A (see Figure 2-30). (c) 2009 Microchip Technology Inc. DS22143B-page 3 MCP6566/6R/6U/7/9 DC CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = VSS, and RPull-Up = 20 k to VPU = VDD (see Figure 1-1). Parameters Push-Pull Output Pull-up Voltage High Level Output Voltage High Level Output Current leakage Low Level Output Voltage Short Circuit Current (Notes 3) Output Pin Capacitance Note 1: 2: 3: 4: VPULL_UP VOH IOH_leak VOL ISC COUT 1.6 -- -- -- -- -- -- -- -- -- 30 8 5.5 VPULL_UP 1 0.6 -- -- V V A V mA pF (see Figure 1-1) (Notes 3, 4) Note 4 IOUT = 3 mA/8 mA @ VDD = 1.8V/5.5V Not to exceed Absolute Max. Rating Symbol Min Typ Max Units Conditions The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points. VHYST at different temperatures is estimated using VHYST (TA) = VHYST @ +25C + (TA - 25C) TC1 + (TA - 25C)2 TC2. Limit the output current to Absolute Maximum Rating of 50 mA. The pull up voltage for the open drain output VPULL_UP can be as high as the absolute maximum rating of 10.5V. In this case, IOH_leak can be higher than 1 A (see Figure 2-30). AC CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated,: Unless otherwise indicated,: VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = VSS, RPull-Up = 20 k to VPU = VDD, and CL = 25 pf (see Figure 1-1). Parameters Propagation Delay High-to-Low,100 mV Overdrive Output Fall Time Maximum Toggle Frequency Input Voltage Noise Note 1: 2: tF fTG ENI -- -- -- -- 20 4 2 350 -- -- -- -- ns MHz MHz VP-P VDD = 5.5V VDD = 1.8V 10 Hz to 10 MHz (Note 1) tPHL -- -- 56 34 80 80 ns ns VCM= VDD/2, VDD = 1.8V VCM= VDD/2, VDD = 5.5V Symbo l Min Typ Max Units Conditions ENI is based on SPICE simulation. Rise time tR and tPLH depend on the load (RL and CL). These specification are valid for the specified load only. TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V and VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, SC70-5 Thermal Resistance, SOT-23-5 Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-SOIC Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP JA JA JA JA JA JA -- -- -- -- -- -- 331 220.7 211 149.5 95.3 100 -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C Symbo l Min Typ Max Units Conditions DS22143B-page 4 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 1.2 Test Circuit Configuration This test circuit configuration is used to determine the AC and DC specifications. VDD MCP656X VPU = VDD IOUT RPU 20 k VOUT 25 pF VSS = 0V 200 k 200 k VIN = VSS FIGURE 1-1: AC and DC Test Circuit for the Open-Drain Output Comparators. (c) 2009 Microchip Technology Inc. DS22143B-page 5 MCP6566/6R/6U/7/9 NOTES: DS22143B-page 6 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = GND, RL = 20 k to VPU = VDD, and CL = 25 pF. 30% Occurrences (%) VDD = 1.8V VCM = VSS Avg. = -0.1 mV StDev = 2.1 mV 3588 units VDD = 5.5V VCM = VSS Avg. = -0.9 mV StDev = 2.1 mV 3588 units 50% Occurrences (%) 40% 30% 20% 10% 0% 25% 20% 15% 10% 5% 0% VDD = 1.8V Avg. = 3.4 mV StDev = 0.2 mV 3588 units VDD = 5.5V Avg. = 3.6 mV StDev = 0.1 mV 3588 units -10 -8 -6 -4 -2 0 2 VOS (mV) 4 6 8 10 1.0 1.5 2.0 2.5 3.0 3.5 VHYST (mV) 4.0 4.5 5.0 FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Hysteresis Voltage. 60% Occurrences (%) 50% 40% 30% 20% 10% 0% Occurrences (%) VCM = VSS Avg. = 0.9 V/C StDev = 6.6 V/C 1380 Units TA = -40C to +125C 60% 50% 40% 30% 20% 10% 0% 0 1380 Units TA = -40C to 125C VCM = VSS VDD = 5.5V Avg. = 10.4 V/C StDev = 0.6 V/C VDD = 1.8V Avg. = 12 V/C StDev = 0.6 V/C -60 -48 -36 -24 -12 0 12 24 VOS Drift (V/C) 36 48 60 2 4 6 8 10 12 14 16 VHYST Drift, TC1 (V/C) 18 20 FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Hysteresis Voltage Drift - Linear Temp. Co. (TC1). 7.0 6.0 5.0 VOUT (V) 4.0 3.0 2.0 1.0 0.0 -1.0 VDD = 5.5V VIN+ = VDD /2 30% Occurrences (%) VDD = 5.5V VDD = 1.8V Avg. = 0.3 V/C StDev = 0.2 V/C 2 2 VIN - VOUT 20% Avg. = 0.25 V/C 2 2 StDev = 0.1 V/C 10% 1380 Units TA = -40C to +125C VCM = VSS 0% -0.50 Time (3 s/div) -0.25 0.00 0.25 0.50 0.75 VHYST Drift, TC2 (V/C2) 1.00 FIGURE 2-3: Phase Reversal. Input vs. Output Signal, No FIGURE 2-6: Input Hysteresis Voltage Drift - Quadratic Temp. Co. (TC2). (c) 2009 Microchip Technology Inc. DS22143B-page 7 MCP6566/6R/6U/7/9 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = GND, RL = 20 k to VPU = VDD, and CL = 25 pF. 3.0 2.0 V OS (mV) 1.0 0.0 -1.0 -2.0 -3.0 -50 -25 0 25 50 75 Temperature (C) 100 125 VDD = 5.5V VDD = 1.8V VCM = VSS 5.0 VCM = VSS 4.0 VHYST (mV) 3.0 2.0 1.0 -50 VDD= 5.0V VDD= 1.8V -25 0 25 50 75 Temperature (C) 100 125 FIGURE 2-7: Temperature. Input Offset Voltage vs. FIGURE 2-10: Temperature. Input Hysteresis Voltage vs. 4.0 2.0 VOS (mV) 0.0 -2.0 -4.0 -0.3 VDD = 1.8V TA= +125C TA= +85C 5.0 TA= +125C 4.0 V HYST (mV) 3.0 2.0 VDD = 1.8V TA= +25C TA= +85C TA= -40C TA= +25C TA= -40C 0.0 0.3 0.6 0.9 1.2 VCM (V) 1.5 1.8 2.1 1.0 -0.3 0.0 0.3 0.6 0.9 1.2 VCM (V) 1.5 1.8 2.1 FIGURE 2-8: Input Offset Voltage vs. Common-mode Input Voltage. FIGURE 2-11: Input Hysteresis Voltage vs. Common-mode Input Voltage. 3.0 2.0 VDD = 5.5V TA= -40C TA= +25C 5.0 4.0 V HYST (mV) 3.0 2.0 1.0 -0.5 TA= -40C TA= +25C TA= +85C TA= +125C VOS (mV) 1.0 0.0 -1.0 -2.0 -3.0 -1.0 TA= +85C TA= +125C VDD = 5.5V 0.0 1.0 2.0 3.0 VCM (V) 4.0 5.0 6.0 0.5 1.5 2.5 3.5 VCM (V) 4.5 5.5 FIGURE 2-9: Input Offset Voltage vs. Common-mode Input Voltage. FIGURE 2-12: Input Hysteresis Voltage vs. Common-mode Input Voltage. DS22143B-page 8 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = GND, RL = 20 k to VPU = VDD, and CL = 25 pF. 3.0 2.0 V HYST (mV) VOS (mV) 1.0 0.0 -1.0 -2.0 -3.0 1.5 2.5 3.5 VDD (V) 4.5 5.5 TA= -40C TA= +25C TA= +85C TA= +125C 5.0 4.0 3.0 2.0 1.0 1.5 2.5 TA= +125C TA= +85C TA= +25C TA= -40C 3.5 V DD (V) 4.5 5.5 FIGURE 2-13: Input Offset Voltage vs. Supply Voltage vs. Temperature. 50% Occurrences (%) 40% 30% 20% 10% 0% 60 70 80 90 100 IQ (A) 110 120 130 VDD = 1.8V Avg. = 88 A StDev= 4 A 1794 units VDD = 5.5V Avg. = 97 A StDev= 4 A 1794 units FIGURE 2-16: Input Hysteresis Voltage vs. Supply Voltage vs. Temperature. 140.0 120.0 100.0 IQ (A) 80.0 60.0 40.0 20.0 0.0 0.0 1.0 2.0 3.0 V DD (V) 4.0 5.0 6.0 TA= -40C TA= +25C TA= +85C TA= +125C FIGURE 2-14: Quiescent Current. FIGURE 2-17: Quiescent Current vs. Supply Voltage vs Temperature. 130 120 110 IQ (A) VDD = 1.8V 130 120 110 IQ (A) Sweep VIN+ ,VIN- = VDD/2 VDD = 5.5V Sweep VIN+ ,VIN - = VDD/2 100 90 80 70 60 -0.5 0.0 0.5 100 90 80 70 Sweep VIN - ,VIN+ = VDD/2 Sweep VIN- ,VIN+ = VDD/2 V /2 1.0 VCM (V) 1.5 2.0 2.5 60 -1.0 0.0 1.0 2.0 3.0 VCM (V) 4.0 5.0 6.0 FIGURE 2-15: Quiescent Current vs. Common-mode Input Voltage. FIGURE 2-18: Quiescent Current vs. Common-mode Input Voltage. (c) 2009 Microchip Technology Inc. DS22143B-page 9 MCP6566/6R/6U/7/9 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = GND, RL = 20 k to VPU = VDD, and CL = 25 pF. 150 125 IQ (A) 100 75 50 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 V PU (V) VDD = 2.5V VDD = 2.0V VDD = 1.8V IDD Spike near VPU = 0.9V VDD = 5.5V VDD = 4.5V VDD = 3.5V 150 VDD = 5.5 V 125 IQ (A) 100 75 VDD = 2.5 V VDD = 2.0 V VDD = 1.8 V VDD = 4.5 V VDD = 3.5 V 50 -4.5 -2.5 -0.5 1.5 3.5 VPU - VDD (V) 5.5 7.5 9.5 FIGURE 2-19: Pull-up Voltage. 400 350 300 IQ (A) 250 200 150 100 50 10 10 100 100 Quiescent Current vs. FIGURE 2-22: Quiescent Current vs. Pull-up to Supply Voltage Difference. 100,000 10,000 IOH_leak (pA) 100 mV Over-Drive VCM = VDD/2 RL = Open 0dB Output Attenuation TA = VDD = 5.5V 1,000 TA = +85C 100 10 1 VDD = 1.8V TA = +25C 1k 10k 100k 1M 10M 1000 10000 100000 100000 1E+07 Toggle Frequency (Hz) 0 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 VPU (V) FIGURE 2-20: Quiescent Current vs. Toggle Frequency. 1000 800 VOL (mV) 600 400 200 0 0.0 3.0 6.0 9.0 IOUT (mA) 12.0 15.0 TA = +125C TA = +85C TA = +25C TA = -40C FIGURE 2-23: Pull-up Voltage. 1000 800 VOL (mV) 600 400 200 0 0 5 Output Leakage Current vs. VDD= 1.8V VDD= 5.5V TA = 125C +125C TA = +85C TA = +25C TA = -40C 10 15 IOUT (mA) 20 25 FIGURE 2-21: Current. Output Headroom vs Output FIGURE 2-24: Current. Output Headroom Vs Output DS22143B-page 10 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = GND, RL = 20 k to VPU = VDD, and CL = 25 pF. 50% Occurrences (%) 40% 30% 20% 10% 0% 30 35 40 45 50 55 60 65 70 75 80 Prop. Delay (ns) 50% Occurrences (%) 40% 30% 20% 10% 0% 30 35 40 45 50 55 60 65 Prop. Delay (ns) 70 75 80 tPHL Avg. = 33 ns StDev= 1 ns 198 units VDD = 1.8V 100 mV Over-Drive VCM = VDD /2 tPHL Avg. = 54.4 ns StDev= 2 ns 198 units VDD= 5.5V 100mV Over-Drive VCM = VDD/2 FIGURE 2-25: Delays. 260 High-to-Low Propagation FIGURE 2-28: Delays. 80 High-to-Low Propagation VCM = VDD/2 Prop. Delay (ns) Prop. Delay (ns) 210 160 110 60 10 1 10 100 1000 Over-Drive (mV) tPHL , VDD = 1.8V tPHL , VDD = 5.5V 70 60 50 40 30 20 100 mV Over-Drive VCM = VDD/2 tPHL , VDD = 1.8V tPHL , VDD = 5.5V -50 -25 0 25 50 75 Temperature (C) 100 125 FIGURE 2-26: Over-Drive. Propagation Delay vs. Input FIGURE 2-29: Temperature. 120 Propagation Delay vs. 140 Prop. Delay (ns) 120 VCM = VDD /2 80 ISC (mA) 40 0 -40 -80 -120 100 80 60 40 20 1.5 2.5 TA= -40C TA= +25C TA= +85C TA= +125C tPHL , 10 mV Over-Drive tPHL , 100 mV Over-Drive TA= -40C TA= +25C TA= +85C TA= +125C 3.5 V DD (V) 4.5 5.5 0.0 1.0 2.0 3.0 VDD (V) 4.0 5.0 6.0 FIGURE 2-27: Supply Voltage. Propagation Delay vs. FIGURE 2-30: Short Circuit Current vs. Supply Voltage vs. Temperature. (c) 2009 Microchip Technology Inc. DS22143B-page 11 MCP6566/6R/6U/7/9 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = GND, RL = 20 k to VPU = VDD, and CL = 25 pF. 80 70 Prop. Delay (ns) 60 50 40 30 20 0.00 tPHL 80 Prop. Delay (ns) VDD= 1.8V 100 mV Over-Drive 70 60 50 40 30 20 VDD= 5.5V 100 mV Over-Drive tPHL 0.50 1.00 VCM (V) 1.50 2.00 0.0 1.0 2.0 3.0 VCM (V) 4.0 5.0 6.0 FIGURE 2-31: Propagation Delay vs. Common-mode Input Voltage. 1000 100 10 1 0.1 0.01 0.001 1 100mV Over-Drive VCM = VDD /2 VDD = 1.8V, tPHL FIGURE 2-34: Propagation Delay vs. Common-mode Input Voltage. 10000 100 mV Over-Drive VCM = VDD/2 Prop. Delay (s) Prop. Delay (ns) 1000 tPLH tPHL VDD = 5.5V, tPHL 100 0.01 10 0.1 1 10 100 1000 100 1000 10000 100000 1E+06 Capacitive Load (nf) 10 0.1 1.0 RPU (k) 10.0 100.0 FIGURE 2-32: Capacitive Load. 10m 1E+11 Propagation Delay vs. FIGURE 2-35: Pull-up Resistor. 10000 Propagation Delay vs. Input Current (A) 1E+09 1m Prop. Delay (ns) 10 1E+07 100n 1E+05 1n 1E+03 10p 1E+01 0.1p 1E-01 -0.8 TA= -40C TA= +25C TA= +85C TA= +125C 100 mV Over-Drive VCM = VDD /2 tPLH, VDD = 5.5V 1000 tPLH, VDD = 1.8V 100 tPHL, VDD = 1.8V tPLH, VDD = 5.5V 10 -0.6 -0.4 Input Voltage (V) -0.2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V PU (V) FIGURE 2-33: Input Bias Current vs. Input Voltage vs Temperature. FIGURE 2-36: Pull-up Voltage. Propagation Delay vs. DS22143B-page 12 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = GND, RL = 20 k to VPU = VDD, and CL = 25 pF. 80 Input Referred 30% Occurrences (%) VCM = VSS VDD = 1.8V to 5.5V CMRR/PSRR (dB) 78 76 74 72 70 -50 -25 0 PSRR VCM = VDD/2 to VDD+ 0.2V Avg. = 0.7 mV StDev= 1 mV VCM = -0.2V to VDD + 0.2V Avg. = 0.6 mV StDev= 0.1 mV 20% VCM = -0.2V to VDD /2 Avg. = 0.5 mV StDev= 0.1 mV CMRR VCM = -0.3V to VDD + 0.3V VDD = 5.5V 10% VDD = 1.8V 3588 units 0% 25 50 75 Temperature (C) 100 125 -5 -4 -3 -2 -1 0 1 2 3 4 5 CMRR (mV/V) FIGURE 2-37: Common-mode Rejection Ratio and Power Supply Rejection Ratio vs. Temperature. 30% 25% Occurrences (%) 20% 15% 10% 5% 0% -600 -400 -200 0 200 400 600 PSRR (V/V) FIGURE 2-40: Ratio (CMRR). Common-mode Rejection Occurrences (%) VCM = VSS Avg. = 200 V/V StDev= 94 V/V 3588 units 30% VCM = VDD/2 to VDD+ 0.3V Avg. = 0.03 mV StDev= 0.7 mV VCM = -0.3V to V DD + 0.3V Avg. = 0.1 mV StDev= 0.4 mV 20% VCM = -0.3V to VDD/2 Avg. = 0.2 mV StDev= 0.4 mV 10% VDD = 5.5V 3588 units 0% -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 CMRR (mV/V) FIGURE 2-38: Ratio (PSRR). 1000 100 IB Power Supply Rejection FIGURE 2-41: Ratio (CMRR). 10000 1000 Common-mode Rejection IB @ TA= +125C IB @ TA= +85C VDD = 5.5V IOS and IB (pA) IOS and IB (pA) 100 10 1 0.1 0.01 0.001 10 1 |I OS| |IOS| @ TA= +125C |IOS |@ TA= +85C 0.1 25 50 75 100 Temperature (C) 125 0 1 2 3 V CM (V) 4 5 6 FIGURE 2-39: Input Offset Current and Input Bias Current vs. Temperature. FIGURE 2-42: Input Offset Current and Input Bias Current vs. Common-mode Input Voltage vs. Temperature. (c) 2009 Microchip Technology Inc. DS22143B-page 13 MCP6566/6R/6U/7/9 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25C, VIN+ = VDD/2, VIN- = GND, RL = 20 k to VPU = VDD, and CL = 25 pF. 10000 Output Jitter pk-pk (ns) VDD = 5.5V 1000 100 10 1 0.1 100 100 VIN+ = 2Vpp (sine) 1k 1000 10k 100k 1M 10000 100000 100000 Input Frequency (Hz) 0 10M 1E+07 FIGURE 2-43: Frequency. Output Jitter vs. Input DS22143B-page 14 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: MCP6566 SC70-5, SOT-23-5 PIN FUNCTION TABLE MCP6568 MSOP, SOIC MCP6569 SOIC, TSSOP Symbol Description SOT-23-5 MCP6566R MCP6566U SOT-23-5 1 4 3 5 -- -- -- -- -- -- 2 -- -- -- 1 4 3 2 -- -- -- -- -- -- 5 -- -- -- 5 3 1 4 -- -- -- -- -- -- 2 -- -- -- 1 2 3 8 5 6 7 -- -- -- 4 -- -- -- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OUT, OUTA Digital Output (comparator A) VIN-, VINA- VDD VINB+ VINB- OUTB OUTC VINC- VINC+ VSS VIND+ VIND- OUTD Inverting Input (comparator A) Positive Power Supply Non-inverting Input (comparator B) Inverting Input (comparator B) Digital Output (comparator B) Digital Output (comparator C) Inverting Input (comparator C) Non-inverting Input (comparator C) Negative Power Supply Non-inverting Input (comparator D) Inverting Input (comparator D) Digital Output (comparator D) VIN+, VINA+ Non-inverting Input (comparator A) 3.1 Analog Inputs 3.3 Power Supply (VSS and VDD) The comparator non-inverting and inverting inputs are high-impedance CMOS inputs with low bias currents. 3.2 Digital Outputs The positive power supply pin (VDD) is 1.8V to 5.5V higher than the negative power supply pin (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need a local bypass capacitor (typically 0.01 F to 0.1 F) within 2 mm of the VDD pin. These can share a bulk capacitor with nearby analog parts (within 100 mm), but it is not required. The comparator outputs are CMOS, open-drain digital outputs. They are designed to make level shifting and wired-OR easy to implement. (c) 2009 Microchip Technology Inc. DS22143B-page 15 MCP6566/6R/6U/7/9 NOTES: DS22143B-page 16 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 4.0 APPLICATIONS INFORMATION 4.1.2 The MCP6566/6R/6U/7/9 family of open-drain output comparators are fabricated on Microchip's state-ofthe-art CMOS process. They are suitable for a wide range of high speed applications requiring low power consumption. INPUT VOLTAGE AND CURRENT LIMITS 4.1 4.1.1 Comparator Inputs NORMAL OPERATION The ESD protection on the inputs can be depicted as shown in Figure 4-2. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass ESD events within the specified limits. VDD Bond Pad The input stage of this family of devices uses two differential input stages in parallel. This configuration provides three regions of operation, one operates at low input voltages, one at high input voltages, and one at mid input voltage. With this topology, the input voltage range is 0.3V above VDD and 0.3V below VSS, while providing low offset voltage through out the common mode range. The input offset voltage is measured at both VSS - 0.3V and VDD + 0.3V to ensure proper operation. The MCP6566/6R/6U/7/9 family has internally-set hysteresis VHYST that is small enough to maintain input offset accuracy and large enough to eliminate output chattering caused by the comparator's own input noise voltage ENI. Figure 4-1 depicts this behavior. Input offset voltage (VOS) is the center (average) of the (input-referred) low-high and high-low trip points. Input hysteresis voltage (VHYST) is the difference between the same trip points. 8 7 6 5 4 3 2 1 0 -1 -2 -3 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 Input Voltage (10 mV/div) VIN+ Bond Pad Input Stage Bond Pad VIN- VSS Bond Pad FIGURE 4-2: Structures. Simplified Analog Input ESD VDD = 5.0V VIN- VOUT Hysteresis In order to prevent damage and/or improper operation of these amplifiers, the circuits they are in must limit the currents (and voltages) at the VIN+ and VIN- pins (see Section 1.1 "Maximum Ratings*" at the beginning of Section 1.0 "Electrical Characteristics"). Figure 4-3 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pin. Diodes D1 and D2 prevent the input pin (VIN+ and VIN-) from going too far above VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD D1 V1 R1 D2 V2 R2 R1 R2 R3 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) 2 mA + MCP656X - VPU R4 VOUT Output Voltage (V) Time (100 ms/div) FIGURE 4-1: The MCP6566/6R/6U/7/9 comparators' internal hysteresis eliminates output chatter caused by input noise voltage. FIGURE 4-3: Inputs. (c) 2009 Microchip Technology Inc. Protecting the Analog DS22143B-page 17 MCP6566/6R/6U/7/9 It is also possible to connect the diodes to the left of the resistors R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistor then serves as in-rush current limiter; the DC current into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs when the common mode voltage (VCM) is below ground (VSS); see Figure 4-3. Applications that are high impedance may need to limit the useable voltage range. 4.3.1 NON-INVERTING CIRCUIT Figure 4-4 shows a non-inverting circuit for singlesupply applications using just two resistors. The resulting hysteresis diagram is shown in Figure 4-5. VPU RPU VOUT VDD VREF MCP656X + 4.1.3 PHASE REVERSAL VIN R1 RF The MCP6566/6R/6U/7/9 comparator family uses CMOS transistors at the input. They are designed to prevent phase inversion when the input pins exceed the supply voltages. Figure 2-3 shows an input voltage exceeding both supplies with no resulting phase inversion. FIGURE 4-4: Non-Inverting Circuit with Hysteresis for Single-Supply. VOUT VDD VOH High-to-Low VOL VSS VSS Low-to-High VIN VTHL VTLH VDD 4.2 Open-Drain Output The open-drain output is designed to make level-shifting and wired-OR logic easy to implement. The output stage minimizes switching current (shoot-through current from supply-to-supply) when the output changes state. See Figures 2-15, 2-18, 2-35 and 2-36, for more information. 4.3 Externally Set Hysteresis Greater flexibility in selecting hysteresis (or input trip points) is achieved by using external resistors. Hysteresis reduces output chattering when one input is slowly moving past the other. It also helps in systems where it is best not to cycle between high and low states too frequently (e.g., air conditioner thermostatic control). Output chatter also increases the dynamic supply current. FIGURE 4-5: Hysteresis Diagram for the Non-Inverting Circuit. The trip points for Figures 4-4 and 4-5 are: EQUATION 4-1: R1 R 1 V TLH = V REF 1 + ------ - V OL ------ RF R F R1 R1 V THL = V REF 1 + ------ - V OH ------ RF R F Where: VTLH VTHL = = trip voltage from low-to-high trip voltage from high-to-low DS22143B-page 18 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 4.3.2 INVERTING CIRCUIT Where: R2 R3 R 23 = -----------------R2 + R3 R3 V 23 = ------------------ x V DD R2 + R3 Using this simplified circuit, the trip voltage can be calculated using the following equation: Figure 4-6 shows an inverting circuit for single-supply using three resistors. The resulting hysteresis diagram is shown in Figure 4-7. VDD VIN VDD R2 RF MCP656X VPU RPU VOUT EQUATION 4-2: RF R 23 V THL = V OH ---------------------- + V 23 --------------------- R 23 + R F R 23 + R F RF R 23 V TLH = V OL ---------------------- + V 23 --------------------- R 23 + R F R 23 + R F R3 FIGURE 4-6: Hysteresis. VOUT VDD VOH Low-to-High VOL VSS VSS Inverting Circuit with Where: VTLH VTHL = = trip voltage from low-to-high trip voltage from high-to-low High-to-Low VIN Figure 2-21 and Figure 2-24 can be used to determine typical values for VOH and VOL. 4.4 VTLH VTHL VDD Bypass Capacitors FIGURE 4-7: Inverting Circuit. Hysteresis Diagram for the With this family of comparators, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good edge rate performance. In order to determine the trip voltages (VTHL and VTLH) for the circuit shown in Figure 4-6, R2 and R3 can be simplified to the Thevenin equivalent circuit with respect to VDD, as shown in Figure 4-8. VPU RPU VOUT 4.5 Capacitive Loads VDD MCP656X + V23 R23 RF VSS Reasonable capacitive loads (e.g., logic gates) have little impact on propagation delay (see Figure 2-32). The supply current increases with increasing toggle frequency (Figure 2-20), especially with higher capacitive loads. The output slew rate and propogation delay performance will be reduced with higher capacitive loads. FIGURE 4-8: Thevenin Equivalent Circuit. (c) 2009 Microchip Technology Inc. DS22143B-page 19 MCP6566/6R/6U/7/9 4.6 PCB Surface Leakage 4.7 PCB Layout Technique In applications where low input bias current is critical, PCB (Printed Circuit Board) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow. This is greater than the MCP6566/6R/6U/7/9 family's bias current at +25C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-9. ININ+ VSS When designing the PCB layout it is critical to note that analog and digital signal traces are adequately separated to prevent signal coupling. If the comparator output trace is at close proximity to the input traces then large output voltage changes from, VSS to VDD or visa versa, may couple to the inputs and cause the device output to oscillate. To prevent such oscillation, the output traces must be routed away from the input pins. The SC70-5 and SOT-23-5 are relatively immune because the output pin OUT (pin 1) is separated by the power pin VDD/VSS (pin 2) from the input pin +IN (as long as the analog and digital traces remain separated through out the PCB). However, the pinouts for the dual and quad packages (SOIC, MSOP, TSSOP) have OUT and -IN pins (pin 1 and 2) close to each other. The recommended layout for these packages is shown in Figure 4-10. OUTA -INA +INA Guard Ring VSS VDD OUTB -INB +INB FIGURE 4-9: Example Guard Ring Layout for Inverting Circuit. 1. Inverting Configuration (Figures 4-6 and 4-9): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the comparator (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN-) to the input pad without touching the guard ring. Non-inverting Configuration (Figure 4-4): a) Connect the non-inverting pin (VIN+) to the input pad without touching the guard ring. b) Connect the guard ring to the inverting input pin (VIN-). FIGURE 4-10: Recommended Layout. 4.8 Unused Comparators 2. An unused amplifier in a quad package (MCP6569) should be configured as shown in Figure 4-11. This circuit prevents the output from toggling and causing crosstalk. It uses the minimum number of components and draws minimal current (see Figure 2-15 and Figure 2-15). 1/4 MCP6569 VDD - + FIGURE 4-11: Unused Comparators. DS22143B-page 20 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 4.9 4.9.1 Typical Applications PRECISE COMPARATOR 4.9.3 BISTABLE MULTI-VIBRATOR Some applications require higher DC precision. An easy way to solve this problem is to use an amplifier (such as the MCP6291) to gain-up the input signal before it reaches the comparator. Figure 4-12 shows an example of this approach. VDD VREF MCP6291 VDD VIN R1 R2 VREF MCP656X VOUT VPU RPU A simple bistable multi-vibrator design is shown in Figure 4-14. VREF needs to be between the power supplies (VSS = GND and VDD) to achieve oscillation. The output duty cycle changes with VREF. VPU R1 VREF VDD MCP656X VOUT R2 RPU C1 R3 FIGURE 4-12: Comparator. 4.9.2 Precise Inverting FIGURE 4-14: Bistable Multi-vibrator. WINDOWED COMPARATOR Figure 4-13 shows one approach to designing a windowed comparator. The AND gate produces a logic `1' when the input voltage is between VRB and VRT (where VRT > VRB). VPU 1/2 MCP6567 RPU VOUT VIN VRT VRB 1/2 MCP6567 FIGURE 4-13: Windowed Comparator. (c) 2009 Microchip Technology Inc. DS22143B-page 21 MCP6566/6R/6U/7/9 NOTES: DS22143B-page 22 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 5.0 5.1 DESIGN AIDS Microchip Advanced Part Selector (MAPS) 5.3 Application Notes MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts. The following Microchip Application Notes are available on the Microchip web site at www.microchip.com and are recommended as supplemental reference resources: * AN895, "Oscillator Circuit For RTD Temperature Sensors", DS00895. 5.2 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/ analogtools. Three of our boards that are especially useful are: * 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV * 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N SOIC14EV * 5/6-Pin SOT23 Evaluation Board, P/N VSUPEV2 (c) 2009 Microchip Technology Inc. DS22143B-page 23 MCP6566/6R/6U/7/9 NOTES: DS22143B-page 24 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 6.0 6.1 PACKAGING INFORMATION Package Marking Information 5-Lead SC70 (MCP6566) Example: XXNN BJ25 5-Lead SOT-23 (MCP6566, MCP6566R) Device MCP6566T Code JYNN JZNN WLNN Example: XXNN MCP6566RT MCP6566UT JY25 Note: Applies to 5-Lead SOT-23. 8-Lead MSOP (MCP6567) XXXXXX YWWNNN Example: 6567E 934256 8-Lead SOIC (150 mil) (MCP6567) Example: XXXXXXXX XXXXYYWW NNN MCP6567E e3 SN^^0934 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2009 Microchip Technology Inc. DS22143B-page 25 MCP6566/6R/6U/7/9 Package Marking Information (Continued) 14-Lead SOIC (150 mil) (MCP6569) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6569 E/SL^^ e3 0934256 14-Lead TSSOP (MCP6569) Example: XXXXXXXX YYWW NNN MCP6569E 0934 256 DS22143B-page 26 (c) 2009 Microchip Technology Inc. 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DS22143B-page 29 MCP6566/6R/6U/7/9 /HDG 3ODVWLF 0LFUR 6PDOO 2XWOLQH 3DFNDJH 06 >0623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 e b A2 c A A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H $ $ $ ( ( ' / / I F L1 0,//,0(7(56 0,1 120 %6& %6& %6& %6& 5() 0$; L /HDG :LGWK E 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS22143B-page 30 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2009 Microchip Technology Inc. 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DS22143B-page 33 MCP6566/6R/6U/7/9 /HDG 3ODVWLF 6PDOO 2XWOLQH 6/ 1DUURZ 1RWH PP %RG\ >62,&@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 b h 3 e h c A A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK &KDPIHU RSWLRQDO )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' K / / I F E D E 0,1 0,//,0(7(56 120 %6& %6& %6& %6& 5() 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & PP SHU VLGH % DS22143B-page 34 (c) 2009 Microchip Technology Inc. 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MCP6566/6R/6U/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2009 Microchip Technology Inc. DS22143B-page 37 MCP6566/6R/6U/7/9 NOTES: DS22143B-page 38 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 APPENDIX A: REVISION HISTORY Revision B (August 2009) The following is the list of modifications: 1. 2. Added MCP6566U throughout the document. Updated package outline drawings. Revision A (March 2009) * Original Release of this Document. (c) 2009 Microchip Technology Inc. DS22143B-page 39 MCP6566/6R/6U/7/9 NOTES: DS22143B-page 40 (c) 2009 Microchip Technology Inc. MCP6566/6R/6U/7/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device - X /XX Package Examples: a) MCP6566T-E/LT: Tape and Reel, Extended Temperature, 5LD SC70 package. Tape and Reel Extended Temperature, 5LD SOT-23 package. Temperature Range MCP6566T: b) Device Single Comparator (Tape and Reel) (SC70, SOT-23) MCP6566RT: Single Comparator (Tape and Reel) (SOT-23 only) MCP6566UT: Single Comparator (Tape and Reel) (SOT-23 only) MCP6567: Dual Comparator MCP6567T: Dual Comparator(Tape and Reel) MCP6569: Quad Comparator MCP6569T: Quad Comparator(Tape and Reel) MCP6566T-E/OT: a) MCP6566RT-E/OT: Tape and Reel Extended Temperature, 5LD SOT-23 package. MCP6566UT-E/OT: Tape and Reel Extended Temperature, 5LD SOT-23 package. MCP6567-E/MS: MCP6567-E/SN: Extended Temperature 8LD MSOP package. Extended Temperature 8LD SOIC package. Tape and Reel Extended Temperature 14LD SOIC package. Tape and Reel Extended Temperature 14LD TSSOP package. a) Temperature Range E = -40C to +125C a) b) Package LT OT MS SN ST SL = = = = = = Plastic Small Outline Transistor (SC70), 5-lead Plastic Small Outline Transistor (SOT-23), 5-lead Plastic Micro Small Outline Transistor, 8-lead Plastic Small Outline Transistor, 8-lead Plastic Thin Shrink Small Outline Transistor, 14-lead Plastic Small Outline Transistor, 14-lead a) MCP6569T-E/SL: b) MCP6569T-E/ST: (c) 2009 Microchip Technology Inc. DS22143B-page 41 MCP6566/6R/6U/7/9 NOTES: DS22143B-page 42 (c) 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2009 Microchip Technology Inc. DS22143B-page 43 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 03/26/09 DS22143B-page 44 (c) 2009 Microchip Technology Inc. |
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