 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Audio Driver for TV CXA3785R Description The CXA3785R is an integrated audio sub-system designed for TV audio application. It has a stereo headphone amplifier, and 4 stereo amplifiers. It also integrated gain control, mute control, input selector, and voltage detectors. Each settable value is controlled through I2C compatible interface. Features 4 stereo audio amplifiers (HP, AMP1, AMP2, AMP3) with programmable gain control Cap less headphone amplifier 2 amplifiers (HP and AMP1) with 3rd order LPF for PWM input AMP3 with 2 stereo input multiplexer and LL/RR output AMP4 for Digital Media Port (DMP) with differential input 4 voltage detection circuits for VUNREG (un-regulated power supply voltage), REGAUD (audio amp power supply voltage), REG33 (DSP power supply voltage) and speaker output 3 muting circuits with external mute control and buffer transistor REGAUD output for supply voltage of 4 stereo audio amplifiers and DMP REG33 output for supply voltage of DSP and PWM output stage I2C control Package size: 64pin LQFP (Body size: 10mm x 10mm) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E08906 CXA3785R Absolute Maximum Ratings Item Symbol VCC Supply voltage VUNREG DVDD Operating temperature range Storage temperature range Junction temperature Power dissipation Thermal impedance *1 Rating 24.0 24.0 4.5 -25 to +85 -55 to +125 +125 (TJ(max) - TA) / JA*1 80 20 Unit V V V C C C TA Tstg TJ(max) PD JA JC -- C/W C/W Glass fabric base epoxy two-layer board, 76mm x 114mm, t = 1.6mm Recommended Operating Conditions Item Symbol VCC Supply voltage VUNREG DVDD Operating ambient temperature Topt Min. 8.0 11.5 3.0 -25 Typ. 12.0 15.0 3.3 -- Max. 13.0 18.0 3.6 +85 Condition VCC = REGAUD VUNREG - REGAUD 2.5V Unit V V V C -2- CXA3785R Block Diagram X_PROTECTOUT MTSEL_CNT AMP4INR_N AMP4INR_P GND_AMP4 AMP4INL_N AMP4OUTR AMP4INL_P AMP4OUTL VCC_AMP4 SEL2INR 34 48 SCL 49 SDA 50 47 46 45 44 43 42 41 40 39 23 37 36 35 33 32 VCC_AMP3 AMP4 (Differential input amp) SEL1INR 31 AMP3OUTR 30 GND_AMP3 29 AMP3OUTL 28 SEL2INL 27 SEL1INL 26 CREFH 25 CREF 24 REF 23 VCC_AMP2 22 AMP2INR 21 AMP2OUTR 20 GND_AMP2 19 AMP2OUTL 18 AMP2INL 17 AMP1INR_P 16 AMP1INR_N MT_CNT VFAULT DGND DVDD BGR REG33 51 REG33NFB 52 GND_REF 53 BGR Logic SELECTOR 4:1 AMP3AG (+4 to +16dB/1dB) REGAUD 54 VUNREG_REF 55 AMP1_MT 56 DETAUD Bandgap reference DETUNREG Current reference 30k DET33 30k 60k AMP2_MT 57 AMP3_MT 58 VUNREG_MT 59 GND_MT 60 SPLN 61 SPLP 62 SPRN 63 SPRP 64 1 HPINL_N Mute control SPDET_L SPDET_R 3rd order LPF 3rd order LPF AMP2AG (+4 to +16dB/1dB) 3rd order LPF 3rd order LPF REF AMP1AG (+4 to +16dB/1dB) HPAG (+8 to +20dB/1dB) 2 HPINL_P 3 HPOUTL 4 GND_HP 5 HPBIASOUT 6 VCC_HP 7 HPOUTR 8 HPINR_N 9 HPINR_P 10 AMP1INL_N 11 AMP1INL_P 12 VCC_AMP1 13 AMP1OUTL SELECTOR 4:1 14 GND_AMP1 15 AMP1OUTR -3- CXA3785R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Pin name HPINL_N HPINL_P HPOUTL GND_HP HPBIASOUT VCC_HP HPOUTR HPINR_N HPINR_P AMP1INL_N AMP1INL_P VCC_AMP1 AMP1OUTL GND_AMP1 AMP1OUTR AMP1INR_N AMP1INR_P AMP2INL AMP2OUTL GND_AMP2 AMP2OUTR AMP2INR VCC_AMP2 REF CREF CREFH SEL1INL SEL2INL AMP3OUTL GND_AMP3 AMP3OUTR VCC_AMP3 SEL1INR SEL2INR AMP4INL_N AMP4INL_P VCC_AMP4 Direction I I O -- O -- O I I I I -- O -- O I I I O -- O I -- O O O I I O -- O -- I I I I -- Description Headphone amp Lch negative input Headphone amp Lch positive input Headphone amp Lch output Headphone amp GND Headphone amp bias output Headphone amp power Headphone amp Rch output Headphone amp Rch negative input Headphone amp Rch positive input AMP1 Lch negative input AMP1 Lch positive input AMP1 power AMP1 Lch output AMP1 GND AMP1 Rch output AMP1 Rch negative input AMP1 Rch positive input AMP2 Lch input AMP2 Lch output AMP2 GND AMP2 Rch output AMP2 Rch input AMP2 power All Amp reference Reference capacitor "H" reference capacitor AMP3 Lch selector input 1 AMP3 Lch selector input 2 AMP3 Lch output AMP3 GND AMP3 Rch output AMP3 power AMP3 Rch selector input 1 AMP3 Rch selector input 2 AMP4 Lch negative input AMP4 Lch positive input AMP4 power -4- CXA3785R Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin name AMP4OUTL GND_AMP4 AMP4OUTR AMP4INR_N AMP4INR_P X_PROTECTOUT VFAULT MT_CNT MTSEL_CNT DVDD DGND SCL SDA REG33 REG33NFB GND_REF REGAUD VUNREG_REF AMP1_MT AMP2_MT AMP3_MT VUNREG_MT GND_MT SPLN SPLP SPRN SPRP Direction O -- O I I O I I I -- -- I I/O O O -- O -- O O O -- -- I I I I Description AMP4 Lch output AMP4 GND AMP4 Rch output AMP4 Rch negative input AMP4 Rch positive input Protect signal output Fault signal input All amp mute control signal input Selected amp mute control signal input Logic power Logic GND I2C clock I2C data REG33 external FET control signal output REG33 negative feedback output Reg/reference GND Regulator output for audio amp Un-regulated power for reg/reference AMP1 mute control signal output AMP2 mute control signal output AMP3 mute control signal output Un-regulated power for mute circuit Mute circuit GND Speaker Lch negative input Speaker Lch positive input Speaker Rch negative input Speaker Rch positive input -5- CXA3785R Pin Circuit Pin Symbol Equivalent circuit VCC_HP REF VCC_HP 20pF 20k 20k 20k 28pF 20k 3pF 20pF 30k 2.5k VCC_HP 30k 2 1 2 8 9 HPINL_N HPINL_P HPINR_N HPINR_P 9 GND_HP VCC_HP 28pF 20k 20k 2.5k 1 8 GND_HP GND_HP 3pF VCC_HP VCC_HP VCC_HP 10pF 5k 3 7 HPOUTL HPOUTR 3 5k 10pF 20pF 100k 20 7 24.9k GND_HP GND_HP GND_HP GND_HP REF VCC_HP VCC_HP VCC_HP 8pF 1k 8pF 1k 5 HPBIASOUT 1k 8pF 1k 8pF GND_HP 50 5 GND_HP GND_HP GND_HP -6- CXA3785R Pin Symbol Equivalent circuit VCC_AMP1 REF VCC_AMP1 20pF 20k 20k 20k 28pF 20k 20k 3pF 20pF 30k 2.5k VCC_AMP1 30k 11 10 11 16 17 AMP1INL_N AMP1INL_P AMP1INR_N AMP1INR_P 17 GND_HP VCC_HP 28pF 20k 2.5k 10 16 GND_AMP1 GND_AMP1 3pF VCC_AMP1 VCC_AMP1 VCC_AMP1 10pF 1k 10pF 1k 13 15 AMP1OUTL AMP1OUTR 13 1k 10pF 1k 10pF 18k GND_AMP1 50pF 40k 20 15 GND_AMP1 GND_AMP1 GND_AMP1 REF VCC_AMP2 VCC_AMP2 18 22 AMP2INL AMP2INR 18 22 GND_AMP2 60k REF VCC_AMP2 VCC_AMP2 VCC_AMP2 10pF 1k 10pF 1k 19 21 AMP2OUTL AMP2OUTR 19 1k 10pF 1k 10pF 50pF 40k 21 18k GND_AMP2 GND_AMP2 GND_AMP2 REF -7- CXA3785R Pin Symbol Equivalent circuit VCC_AMP2 VCC_AMP2 VCC_AMP2 24 REF 5k GND_AMP2 GND_AMP2 24 VCC_AMP2 VCC_AMP2 30k 30k 26 25 26 CREF CREFH 60k GND_AMP2 VCC_AMP2 GND_AMP2 25 GND_AMP2 VCC_AMP3 VCC_AMP3 27 28 33 34 SEL1INL SEL2INL SEL1INR SEL2INR 27 28 33 34 REF GND_AMP3 60k VCC_AMP3 VCC_AMP3 VCC_AMP3 10pF 1k 10pF 1k 29 31 AMP3OUTL AMP3OUTR 29 1k 10pF 1k 10pF 50pF 40k 18k 20 31 GND_AMP3 GND_AMP3 GND_AMP3 GND_AMP3 REF -8- CXA3785R Pin Symbol Equivalent circuit VCC_AMP4 CC VCC_AMP4 15pF 60k REF 42.48k VCC_AMP4 60k VCC_AMP4 36 35 36 41 42 AMP4INL_N AMP4INL_P AMP4INR_N AMP4INR_P 42 GND_AMP4 VCC_AMP4 10pF 15pF 42.48k 1k 2pF 1k 1k 1k 2pF 35 41 10pF GND_AMP4 GND_AMP4 GND_AMP4 VCC_AMP4 VCC_AMP4 VCC_AMP4 2pF 1k 10pF 1k 38 40 AMP4OUTL AMP4OUTR 38 1k 2pF 1k 10pF 60k GND_AMP4 GND_AMP4 15pF 42.48k 20 40 35 GND_AMP4 GND_AMP4 41 DVDD DVDD 43 X_PROTECTOUT 43 DGND DGND DVDD DVDD DVDD 400k DVDD 44 VFAULT 44 200k 1M DGND DGND DGND -9- CXA3785R Pin Symbol Equivalent circuit DVDD DVDD 45 46 MT_CNT MTSEL_CNT 45 46 100k DGND DGND DGND DVDD 500 49 SCL 49 DGND DGND DVDD 500 50 DVDD 50 SDA 2k DGND 2pF DGND 10k DGND DGND VUNREG_REF VUNREG_REF 1k 51 REG33 2.5k 10pF GND_REF GND_REF 51 VUNREG_REF VUNREG_REF 52 52 REG33NFB 40k GND_REF GND_REF 26k - 10 - CXA3785R Pin Symbol Equivalent circuit VUNREG_REF VUNREG_REF VUNREG_REF 10pF 40k 54 REGAUD 56k GND_REF GND_REF GND_REF 54 VUNREG_MT 60k 56 57 58 AMP1_MT AMP2_MT AMP3_MT 120k GND_MT VUNREG_MT 56 57 58 REGAUD VUNREG_MT 61 62 63 64 SPLN SPLP SPRN SPRP 61 62 63 64 GND_MT 150k - 11 - CXA3785R Block Diagram (Regulator, Reference) VUNREG_REF BGR REG33 2SJ668 REG33NFB 10F Bandgap reference Current reference GND_REF GND_REF VUNREG_REF REGAUD 100F GND_REF REGAUD[1:0] 9V to 12V/1V GND_REF - 12 - CXA3785R Electrical Spec. (HP Amp) Electrical Characteristics (Regulator, Reference) (Unless otherwise specified; Ta = 25C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item REG33NFB output voltage Symbol VREG33NFB Condition ILOAD = 1mA ILOAD = 1mA, REG33NFB = REG33NFB (ILOAD = 1mA) + 25mV ILOAD = 1mA, REG33NFB = REG33NFB (ILOAD = 1mA) - 25mV ILOAD = 1mA, REG33 = 10V, REG33NFB = REG33NFB (ILOAD = 1mA) + 25mV ILOAD = 1mA, REG33 = 10V REG33NFB = REG33NFB (ILOAD = 1mA) - 25mV ILOAD = 100mA, VCC = REGAUD = 12V ILOAD = 100mA, VCC = REGAUD = 11V ILOAD = 100mA, VCC = REGAUD = 10V ILOAD = 100mA, VCC = REGAUD = 9V ILOAD = 1m - 100mA, VCC = REGAUD = 12V VUNREG = 14.5 - 18V, ILOAD = 100mA VCC = REGAUD = 12V ILOAD = 100mA Min. 3.0 VUNREG - 2.0 Typ. 3.3 VUNREG - 1.0 Max. 3.6 Unit V VREG33SW1 REG33 output voltage swing VREG33SW2 -- V -- 3.0 6.0 V REG33 sourcing current IREG33SOURCE 10 20 40 A REG33 sinking current REGAUD output voltage 1 REGAUD output voltage 2 REGAUD output voltage 3 REGAUD output voltage 4 REGAUD load regulation REGAUD line regulation REGAUD PSRR CREF output voltage CREFH output voltage REF output voltage IREG33SINK 1.5 3.0 6.0 mA VAUD1 VAUD2 VAUD3 VAUD4 VLO_AUD 11.0 10.0 9.0 8.0 -- 12.0 11.0 10.0 9.0 -- 13.0 12.0 11.0 10.0 0.3 V V V V V VLI_AUD PSRRAUD VCREF VCREFH VREF -- 40 (VCC/2) x 0.9 (3 x VCC/4) x 0.9 (VCC/2) x 0.9 -- 60 VCC/2 3 x VCC/4 VCC/2 0.3 -- (VCC/2) x 1.1 (3 x VCC/4) x 1.1 (VCC/2) x 1.1 V dB V V V - 13 - CXA3785R Design Procedure (REG33) Regulator Compensation VUNREG_REF BGR FET VIN The compensation network (C1, R1) is customizable and depends on load and MOSFET characteristics: REG33 REG33NFB C1 GND_REF R1 10F GND_REF GND_REF Strength of the external p-channel MOSFET (gm), it's forward transconductance (gfs), and the gateto-source capacitance (Cgs). The driver transconductance (gmdrv) of the integrated circuit driver. Load current range (including the minimum load): Imin to Imax External MOSFET Selection The selected MOSFET must have a gate threshold voltage (at the required max load) that meets the following criteria: Vgs_min < VIN - VREG33SW2 - 14 - CXA3785R Block Diagram (HP Amp) 20pF 30k VCC_HP VCC_HP 28pF 20k 20k 28pF 20k GND_HP 20pF 30k GND_HP AMPEN VCC_HP HPAG[3:0] 8 to 20dB/1dB 100 2.2F 20k 20k 20k HPINL_N HPINL_P 2.2F HPOUTL AMPEN 20pF 30k VCC_HP VCC_HP 2.2F 28pF 20k 20k 28pF 20k GND_HP 20pF 30k AMPEN GND_HP HPAG[3:0] 8 to 20dB/1dB BIASEN VCC_AMP2 100 GND_HP HPERR to detector block HPBIASOUT 2.2F 20k 20k 20k HPINR_N HPINR_P HPOUTR 30k CREFH 0.1F VCC_AMP2 30k GND_AMP2 REF 60k 10F GND_AMP2 AMPEN GND_AMP2 GND_AMP2 CREF 4.7F GND_AMP2 - 15 - CXA3785R Electrical Spec. (HP Amp) Electrical Characteristics (HP Block) (Unless otherwise specified; Ta = 25C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Input impedance Output DC voltage (HPOUT, HPBIASOUT) Gain adjustment range Gain adjustment step LPF cutoff frequency Symbol RINHP VOUTHP GAINHP STPHP LPFHP VOMHP_1 Maximum output level VOMHP_2 VO = 55kHz/1kHz Gain = 14dB, THD = 1.0%, RL = 100 + 32, VCC = REGAUD = 12.0V Gain = 14dB, THD = 1.0%, RL = 100 + 32, VCC = REGAUD = 9.0V Gain = 14dB, LPF RL = 100 + 32, VIN = 0.1Vrms Gain = 14dB, RL = 100 + 32, Measured at RL of 32 Gain = 14dB, RL = 1k Gain = 14dB, VIN = 0.4Vrms Gain = 14dB, Output level = 2.8Vrms fsig = 1kHz Gain = 14dB, AC coupled input fsig = 1kHz Condition Min. 48.0 (VCC/2) x 0.9 8.0 0 -5.5 2.8 Typ. 60.0 VCC/2 -- 1.0 -3.0 -- Max. 72.0 (VCC/2) x 1.1 20.0 2.0 -0.5 -- Vrms 2.1 -- -- Unit k V dB dB dB THD+N THDHP -- 0.10 0.50 % Output noise level Gain error Channel separation Mute level PSRR VNHP GEHP CTHP MTHP PSRRHP -- -1.0 70.0 -- 30.0 -92.0 0 80.0 -90.0 40.0 -82.0 1.0 -- -80.0 -- dBV dB dB dB dB - 16 - CXA3785R Block Diagram (AMP1 Amp) 20pF 30k VCC_AMP1 2.2F 20k 28pF 20k 20k 20k 20k 28pF 20k GND_AMP1 20pF 30k GND_AMP1 AMPEN 20pF 30k VCC_AMP1 20k 28pF 20k 20k 20k 20k 28pF 20k GND_AMP1 20pF 30k AMPEN GND_AMP1 AMP1AG[3:0] 4 to 16dB/1dB BIASEN 30k 30k VCC_AMP2 VCC_AMP1 AMP1AG[3:0] 4 to 16dB/1dB AMP1INL_N 2.2F VCC_AMP1 AMP1OUTL 10F 1k AMP1INL_P External audio power amplifier 2.2F AMP1INR_N 2.2F AMP1OUTR 10F 1k AMP1INR_P CREFH 0.1F GND_AMP2 VCC_AMP2 REF 10F GND_AMP2 AMPEN GND_AMP2 60k GND_AMP2 CREF 4.7F GND_AMP2 - 17 - CXA3785R Electrical Spec. (AMP1 Amp) Electrical Characteristics (AMP1 Block) (Unless otherwise specified; Ta = 25C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Input impedance Output DC voltage Gain adjustment range Gain adjustment step LPF cutoff frequency Symbol RINAMP1 VOUTAMP1 GAINAMP1 STPAMP1 LPFAMP1 VOMAMP1_1 Maximum output level VOMAMP1_2 VO = 55kHz/1kHz Gain = 10dB, THD = 1.0%, RL = 1k VCC = REGAUD = 12.0V Gain = 10dB, THD = 1.0%, RL = 1k VCC = REGAUD = 9.0V Gain = 10dB, RL = 1k, VIN = 0.2Vrms Gain = 10dB, RL = 1k Gain = 10dB, RL = 1k Gain = 10dB, VIN = 1.0Vrms fsig = 1kHz Gain = 10dB, AC coupled input fsig = 1kHz Condition Min. 48.0 (VCC/2) x 0.9 4.0 0 -5.5 2.8 Typ. 60.0 VCC/2 -- 1.0 -3.0 -- Max. 72.0 (VCC/2) x 1.1 16.0 2.0 -0.5 -- Vrms 2.1 -- -- Unit k V dB dB dB THD+N Output noise level Gain error Channel separation PSRR THDAMP1 VNAMP1 GEAMP1 CTAMP1 PSRRAMP1 -- -- -1.0 70.0 30.0 0.01 -90.0 0 80.0 40.0 0.10 -80.0 1.0 -- -- % dBV dB dB dB - 18 - CXA3785R Block Diagram (AMP2 Amp) VCC_AMP2 2.2F AMP2INL 60k AMP2OUTL 10F 1k GND_AMP2 AMP2EN VCC_AMP2 AMP2AG[3:0] 4 to 16dB/1dB External audio power amplifier AMP2OUTR 10F 2.2F AMP2INR 60k VCC_AMP2 1k GND_AMP2 AMP2EN AMP2AG[3:0] 4 to 16dB/1dB BIASEN VCC_AMP2 30k CREFH 0.1F 30k GND_AMP2 REF 60k 10F GND_AMP2 GND_AMP2 GND_AMP2 AMPEN CREF 4.7F GND_AMP2 - 19 - CXA3785R Electrical Spec. (AMP2 Amp) Electrical Characteristics (AMP2 Block) (Unless otherwise specified; Ta = 25C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Input impedance Output DC voltage Gain adjustment range Gain adjustment step Symbol RINAMP2 VOUTAMP2 GAINAMP2 STPAMP2 VOMAMP2_1 Maximum output level VOMAMP2_2 Gain = 10dB, THD = 1.0%, RL = 1k VCC = REGAUD = 12.0V Gain = 10dB, THD = 1.0%, RL = 1k VCC = REGAUD = 9.0V Gain = 10dB, RL = 1k, VIN = 0.2Vrms Gain = 10dB, RL = 1k Gain = 10dB, RL = 1k Gain = 10dB, VIN = 1.0Vrms fsig = 1kHz Gain = 10dB, AC coupled input fsig = 1kHz Condition Min. 48.0 (VCC/2) x 0.9 4.0 0 2.8 Typ. 60.0 VCC/2 -- 1.0 -- Max. 72.0 (VCC/2) x 1.1 16.0 2.0 -- Vrms 2.1 -- -- Unit k V dB dB THD+N Output noise level Gain error Channel separation PSRR THDAMP2 VNAMP2 GEAMP2 CTAMP2 PSRRAMP2 -- -- -1.0 70.0 30.0 0.01 -95.0 0 80.0 40.0 0.10 -85.0 1.0 -- -- % dBV dB dB dB - 20 - CXA3785R Block Diagram (AMP3 Amp) VCC_AMP3 2.2F AMP3OUTL 10F SEL1INL SEL2INL 2.2F 60k 60k GND_AMP3 AMPEN 2.2F AMP3AG[3:0] 4 to 16dB/1dB 1k SEL1INR SEL2INR VCC_AMP3 External audio power amplifier AMP3OUTR 10F 2.2F 60k 60k VCC_AMP2 AMP3AG[3:0] 4 to 16dB/1dB BIASEN 30k 1k GND_AMP3 AMPEN 30k CREFH 0.1F GND_AMP2 VCC_AMP2 REF 60k 10F GND_AMP2 GND_AMP2 GND_AMP2 AMPEN CREF 4.7F GND_AMP2 - 21 - CXA3785R Electrical Spec. (AMP3 Amp) Electrical Characteristics (AMP3 Block) (Unless otherwise specified; Ta = 25C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Input impedance Output DC voltage Gain adjustment range Gain adjustment step Symbol RINAMP3 VOUTAMP3 GAINAMP3 STPAMP3 VOMAMP3_1 Maximum output level VOMAMP3_2 Gain = 10dB, THD = 1.0%, RL = 1k VCC = REGAUD = 12.0V Gain = 10dB, THD = 1.0%, RL = 1k VCC = REGAUD = 9.0V Gain = 10dB, RL = 1k, VIN = 0.2Vrms Gain = 10dB, RL = 1k Gain = 10dB, RL = 1k Gain = 10dB, VIN = 1.0Vrms fsig = 1kHz Gain = 10dB, AC coupled input fsig = 1kHz Condition Min. 48.0 (VCC/2) x 0.9 4.0 0 2.8 Typ. 60.0 VCC/2 -- 1.0 -- Max. 72.0 (VCC/2) x 1.1 16.0 2.0 -- Vrms 2.1 -- -- Unit k V dB dB THD+N Output noise level Gain error Channel separation PSRR THDAMP3 VNAMP3 GEAMP3 CTAMP3 PSRRAMP3 -- -- -1.0 70.0 30.0 0.01 -95.0 0 80.0 40.0 0.10 -85.0 1.0 -- -- % dBV dB dB dB - 22 - CXA3785R Block Diagram (AMP4 Amp) 15pF 42.48k VCC_AMP4 60k 2.2F AMP4INL_N 2.2F 60k AMP4OUTL 10F 20k AMPEN GND_AMP4 AMP4INL_P 15pF 42.48k 15pF 42.48k VCC_AMP4 External audio power amplifier AMP4OUTR 10F 2.2F 60k AMP4INR_N 2.2F 60k VCC_AMP2 AMPEN GND_AMP4 15pF 42.48k BIASEN 30k AMP4INR_P 20k CREFH 0.1F VCC_AMP2 30k GND_AMP2 REF 10F GND_AMP2 AMPEN GND_AMP2 CREF 60k 4.7F GND_AMP2 GND_AMP2 - 23 - CXA3785R Electrical Spec. (AMP4 Amp) Electrical Characteristics (AMP4 Block) (Unless otherwise specified; Ta = 25C, VCC = REGAUD = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Input impedance Output DC voltage Gain Symbol RINAMP4 VOUTAMP4 GAINAMP4 VOMAMP4_1 Maximum output level VOMAMP4_2 THD+N Output noise level Gain error Channel separation PSRR THDAMP4 VNAMP4 GEAMP4 CTAMP4 PSRRAMP4 AC coupled input Single Input, fsig = 1kHz Gain = 10dB, THD = 1.0%, RL = 1k VCC = REGAUD = 12.0V Gain = 10dB, THD = 1.0%, RL = 1k VCC = REGAUD = 9.0V RL = 20k, VIN = 1.0Vrms RL = 20k RL = 20k VIN = 1.0Vrms fsig = 1kHz Condition Min. 48.0 (VCC/2) x 0.9 -4.0 2.8 Typ. 60.0 VCC/2 -3.0 -- Max. 72.0 (VCC/2) x 1.1 -2.0 -- Vrms 2.1 -- -- -1.0 70.0 30.0 -- 0.01 -95.0 0 80.0 40.0 -- 0.10 -85.0 1.0 -- -- % dBV dB dB dB Unit k V dB - 24 - CXA3785R Block Diagram (Detector) VUNREG_REF DETUNREG[1:0] 6.0V to 12.0V/2.0V DVDD DETUNREG GND_MT GND_MT VCC_AMP2 DETAUD GND_MT GND_MT REG33NFB DVDD DET33 GND_MT GND_MT HPBIAS grounding error HPERREN HPBIAS "L": Normal "H": Error Reset logic X_PROTECTOUT COM PROMSK Power amplifier VFAULT REGAUD "L": Error "H": Normal SPDETL 100k SPLN 4.7F 100k Power amplifier SPLP 150k 150k GND_MT REGAUD GND_MT 100k SPDETR SPRN 4.7F 100k Power amplifier SPRP 150k 150k GND_MT GND_MT - 25 - CXA3785R Block Diagram (Mute Control) COM MT_CNT MTSEL_CNT AMP1MTSEL AMP1MT DETUNREG VUNREG_MT AMP1_MT AMP1OUT GND_MT VUNREG_MT AMP2MTSEL AMP2MT AMP2_MT AMP2OUT GND_MT VUNREG_MT AMP3MTSEL AMP3MT AMP3_MT AMP3OUT GND_MT - 26 - CXA3785R Electrical Spec. (Detector 1) Electrical Characteristics (Detector Block1) (Unless otherwise specified; Ta = 25C, VCC = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item Detection voltage 1_1 *1 Symbol VDET1_1 VREL1_1 VDET1_1 VREL1_2 VDET1_3 VREL1_3 VDET1_4 VREL1_4 VDET2 VREL2 VDET3 VREL3 VIN_SPP/N Condition VUNREG voltage detection (set: 6.0V) VUNREG voltage detection (set: 8.0V) VUNREG voltage detection (set: 10.0V) VUNREG voltage detection (set: 12.0V) REGAUD voltage detection REG33NFB voltage detection SPP/N minimum input voltage Speaker out (|SPP - SPN|) voltage detection Rin = 100k + 150k Input voltage (SPxP/N) is over 3.0V necessary. HPBIAS voltage detection, HPERREN = "1" Min. 4.8 -- 7.0 -- 9.0 -- 10.8 -- 5.4 -- 1.44 -- 3.0 Typ. 6.0 -- 8.0 -- 10.0 -- 12.0 -- 6.0 -- 1.60 -- -- Max. 6.6 7.0 8.8 9.5 11.0 12.0 13.2 14.0 6.6 7.0 1.76 1.80 -- Unit V Release voltage 1_1 *1 Detection voltage 1_1 Release voltage 1_1 Detection voltage 1_2 Release voltage 1_2 Detection voltage 1_3 Release voltage 1_3 Detection voltage 2 Release voltage 2 Detection voltage 3 Release voltage 3 Minimum input voltage (SPP/N) V V V V V V Detection voltage 4_2*2,*3 VDET4 1.10 1.45 1.80 V Detection voltage 5 *1 *2 *3 VDET5 1.50 2.50 3.50 V This is not tested. Therefore the characteristics is guaranteed by design. X_PROTECTOUT outputs "L" when input voltage (SPxP/N) become under 3.0V. Next page shows the measurement circuit example. - 27 - CXA3785R SPDET Measurement Circuit REGAUD SPDETx 100k SPxN SPxP 150k 150k 100k SPK_SPxN SPK_SPxP GND_MT GND_MT Input pin (SPxN/P) is should be biased to over 3.0V. Electrical Spec. (Detector 2) Electrical Characteristics (Detector Block2) (Unless otherwise specified; Ta = 25C, VCC = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item VFAULT High level input voltage VFAULT Low level input voltage X_PROTECTOUT High level output voltage X_PROTECTOUT Low level output voltage MT_CNT / MTSEL_CNT High level input voltage MT_CNT / MTSEL_CNT Low level input voltage MT output voltage (Low: OFF) MT output voltage (High: ON) MT output current (OFF) MT output current (ON) Symbol VFAULTH VFAULTL VOPROH VOPROL VIMT_CNT VIMT_CNT VMT_L VMT_H IOMTH IOMTL Condition Input: High level Input: Low level Output: High level, RL = 1M Output: Low level, RL = 1M Input: High level Input: Low level Rout = 10k Rout = 10k Rout = 10k Rout = 10k Min. 2.5 0 2.5 0 2.5 0 -- 13.0 -- 1.4 Typ. -- -- -- -- -- -- 0 VUNREG 0 1.5 Max. 18.0 0.5 DVDD 0.5 DVDD 0.5 0.5 -- 3.0 -- Unit V V V V V V V V A mA - 28 - CXA3785R Detector Waveform VUNREG_REF (Pin; DETUNREG) Detect Voltage VCC_AMP2 (Pin; DETAUD) 6V REG33 (Pin; DET33) 1.6V HPBIAS (Pin) 2.5V SPDETL/R (Pin: SP(L/R) P-SP(L/R)N) Detect Voltage VFAULT (Pin) DETUNREG[1:0] (Register) Default Det. voltage setting Default PROMSK (Register) HPERREN (Register) X_PROTECTOUT (External Output Pin) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) Description of Detector Waveform (1) to (8) Despite each voltage falls below detect voltage, X_PROTECTOUT keeps "H" because PROMSK is "H". (9) (10) (11) (12) (13) (14) (15) (16) When difference voltage between SPxP and SPxN rise over detect voltage, X_PROTECTOUT is "L". Same as (9). When VUNREG_REF is falls below detect voltage, X_PROTECTOUT is "L". When VCC_AMP2 falls below the detect voltage, X_PROTECTOUT is "L". When REG33 falls below the DETAUD detect voltage, X_PROTECTOUT is "L". When HPBIAS falls below the detect voltage but HPEREN is "L", X_PROTECTOUT keeps "H". When HPBIAS falls below the detect voltage, X_PROTECTOUT is "L". When VFAULT is "H", X_PROTECTOUT is "L". - 29 - CXA3785R Mute Control Waveform VUNREG_REF (Pin) MT_CNT (Pin) MTSEL_CNT (Pin) HPMTCNT (Register) AMP1MT (Register) AMP2MT (Register) AMP3MT (Register) HPMTSEL (Register) AMP1MTSEL (Register) AMP2MTSEL (Register) AMP3MTSEL (Register) HPMT (Internal) Un-Mute Mute Un-Mute Mute Un-Mute Mute Un-Mute Mute Hi-Z AMP1_MT (Pin) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z AMP2_MT (Pin) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z AMP3_MT (Pin) Hi-Z (1) Hi-Z (2) (3) (4) Hi-Z (5) (6) (7) Hi-Z (8) Hi-Z Description of Mute Control Waveform (1) (2) (3) (4) (5) (6) (7) (8) When MT_CNT is "L", all amp output is muted except for AMP4. When MTSEL_CNT is "L" and XXSEL is "H", XXAMP output is muted. When MTSEL_CNT is "L" and XXSEL is "L", XXAMP keeps un-mute. When HPMTCNT is "H", HPAMP output is muted. When AMP1MTCNT is "H", AMP1AMP output is muted. When AMP2MTCNT is "H", AMP2AMP output is muted. When AMP3MTCNT is "H", AMP3AMP output is muted. When VUNREG_REF is fall below the VUNREG detector voltage, all amp output is muted except for AMP4. - 30 - CXA3785R Amp Sequence with Mute Transistor (HP, AMP1-3) REGAUD (Register) 9V 12V 9V BIASEN (Register) OFF ON OFF AMPEN (Register) OFF ON OFF HPAG (Register) 0dB XXdB 0dB HPMTCNT (Register) MUTE >1s UN-MUTE MUTE >1ms HPOUT (Pin) (1) (2) (3)(4) (1) (2) (3) (4) BIASEN and AMPEN set on, REGAUD and HPAG set intended value. MTCNT should be set un-mute at least 1s after (1). When shut off the AMP, MTCNT should be set mute at first. All settings set off or set default at least 1ms after (3). - 31 - CXA3785R Amp Sequence without Mute Transistor (HP) REGAUD (Register) 9V 12V 9V BIASEN (Register) OFF ON OFF AMPEN (Register) OFF ON OFF HPAG (Register) 0dB XXdB 0dB HPMTCNT (Register) MUTE >1ms >2s UN-MUTE MUTE >1ms >1ms HPOUT (Pin) (1)(2) (3) (4)(5)(6) (1) (2) (3) (4) (5) REGAUD set intended value and BIASEN set on. AMPEN should be set on at least 1ms after (1). HPAG set intended value and HPMTCNT set un-mute at least 2s after (2). When shut off HPAMP, first HPAG set 0dB and HPMTCNT set mute at the same time. BIASEN and AMPEN set off at least 1ms after (4). (6) REGAUD set default value at least 1ms after (5) if needed. - 32 - CXA3785R Power-On/Power-Off Sequence Recommended Power-On Sequence VUNREG REGAUD DVDD Internal RST >1ms I2C should be controlled at least 1ms after DVDD is supplied. Power-Off Sequence (with Mute Transistor) Power-Off Sequence (without Mute Transistor) VUNREG VUNREG REGAUD REGAUD DVDD >1ms VUNREG should be turn off at least 1ms after DVDD turn off. DVDD >2s DVDD should be turn off at least 2s after VUNREG turn off. - 33 - CXA3785R Electrical Spec. (I2C BUS Block) Electrical Characteristics (I2C BUS Block) (Unless otherwise specified; Ta = 25C, VCC = 12.0V, VUNREG = 15.0V, DVDD = 3.3V, fsignal = 1kHz, measurement band width = 20 to 20kHz) Item High level input voltage Low level input voltage High level input current Low level input current Low level output voltage Clock frequency Data change minimum waiting time Data transfer start waiting time Low level clock pulse width High level clock pulse width Start setup waiting time Data hold time Data setup time Rise time Fall time Stop setup waiting time Symbol VIH VIL IIH IIL VOL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO with SDA 3mA current supplied Condition Min. 2.5 0 -- -- 0 0 1.3 0.6 1.3 0.6 0.6 0 100 -- -- 0.6 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. DVDD 0.5 10.0 10.0 0.4 400 -- -- -- -- -- -- -- 300 300 -- Unit V V A A V kHz s s s s s s ns ns ns s SDA tBUF tR tF SCL tHD;STA tLOW P S tHD;DAT tHIGH tSU;DAT tSU;STA S tSU:STO P Fig. I2C BUS Control Signal Timing Chart - 34 - CXA3785R Measurement Circuit 20k 20k 2.2F 2.2F 2.2F 2.2F 2.2F DVDD Rp 48 49 50 47 46 45 44 43 42 41 10F 40 39 10F 23 37 36 35 34 2.2F I2C control DVDD Rp AMP4 (Differential input amp) SELECTOR 4:1 31 30 AMP3AG (+4 to +16dB/1dB) BGR 2SJ668 51 52 53 BGR Logic 1k SELECTOR 4:1 10F M 29 28 2.2F 1k 100F M 54 55 DETAUD Bandgap reference DETUNREG Current reference 30k 30k 2.2F 27 0.1F 26 4.7F 56 DET33 25 Over 10F 57 58 59 60 Mute control 60k 24 23 2.2F SPDET_L SPDET_R 3rd order LPF 3rd order LPF AMP2AG (+4 to +16dB/1dB) 22 21 20 19 2.2F AMP1AG (+4 to +16dB/1dB) 100k 61 62 63 64 100k 3rd order LPF 3rd order LPF 1k 100k 100k REF 1k 18 2.2F HPAG (+8 to +20dB/1dB) 17 7 2.2F 1 2.2F 2.2F 2 100 3 4 5 6 100 8 2.2F 9 10 2.2F 11 2.2F 12 13 14 15 10F 16 2.2F 1k 1k M M M 32 M 32 M - 35 - M 10F M 10F M 10F M M M M M M M 33 32 10F CXA3785R I2C BUS Interface Description The bus protocol conforms to the I2C bus specifications, but the following restrictions are applied. Bus slave operation only Supports fast mode only The general call address and start byte of the slave address are not supported. CBUS compatibility is not supported. 10-bit slave addresses are not supported. Write mode and read mode (only 1bit: sub add "00", S7) are supported. Slave Address Transmit the 7-bit slave address and the 1-bit read/write code following the START condition. Write operation to this IC is allowed only when the input slave address and the device code match. When the slave address dose not match the device code, an ACK (acknowledge response) is not generated and the IC dose not respond. Slave Address Slave address word (8bits) Device code (fixed) S7 1 S6 0 S5 0 S4 1 S3 1 S2 1 S1 0 R/W code (fixed) S0 0/1 - 36 - CXA3785R Register Function (Write Register) Write Cycle After providing slave address from master, set next transfer cycle data as write start sub address of control register to internal control register address. After that, cycle write the data providing from master to sub address indicated by control register address. Designated control register address is incremented automatically every one byte transfer completion. See the control register map for writable control register. Slave address ACK ACK ACK ACK STOP 1 S7 START 0 S6 0 S5 1 S4 1 S3 1 S2 0 S1 0 R/W Start sub address Write data Write data from Master to Slave from Slave to Master - 37 - CXA3785R Register Function (Read Register) Read Cycle The sub address that can read is only 00hex. To be operated read, transfer sub address (00hex) in the same procedure of write cycle. After that, re-transfer slave address from master in read mode and then the CXA3785R is in a read mode, data from sub address (00hex) accessed by control register address is returned to host. Also, data from sub address (00hex) is returned to host continuously, until stop condition is transferred. Slave address ACK Sub address ACK RTEST ACK STOP Read data D7 RTEST ACK 1 S2 0 S1 1 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACK 0 1 STOP RTEST 1 S7 START 0 S6 0 S5 1 S4 1 S3 1 S2 0 S1 0 R/W 0 0 0 0 0 0 0 0 Slave address 1 START S7 0 S6 0 S5 1 S4 1 S3 0 0 0 0 0 0 from Master to Slave from Slave to Master - 38 - CXA3785R Register Map Write Register Address 00 R/W Default Register name AMP ENABLE PROTECTOR READ REGISTER D7 RTEST R/W 0 D6 D5 D4 D3 D2 D1 D0 AMPEN W 0 AMP2EN PROMSK HPERREN HPOLPEN REGOLPEN BIASEN W 0 W 1 W 1 W 1 W 1 W 0 Address 01 R/W Default Register name D7 D6 D5 D4 D3 D2 D1 D0 HPAG[3:0] HP/AMP1 GAIN W 0 W 0 W 0 W 0 W 0 AMP1AG[3:0] W 0 W 0 W 0 Address 02 R/W Default Register name D7 D6 D5 D4 D3 D2 D1 D0 AMP2AG[3:0] AMP2/AMP3 GAIN W 0 W 0 W 0 W 0 W 0 AMP3AG[3:0] W 0 W 0 W 0 Address 03 R/W Default Register name DETUNREG AMP3SEL D7 D6 D5 D4 D3 D2 D1 D0 AMP3SEL_R[1:0] W 0 W 0 AMP3SEL_L[1:0] W 0 W 0 REGAUD[1:0] W 0 W 0 DETUNREG[1:0] W 0 W 0 Address 04 R/W Default Register name D7 D6 D5 D4 D3 D2 D1 AMP2MT W 0 D0 AMP3MT W 0 HPMTSEL AMP1MTSEL AMP2MTSEL AMP3MTSEL HPMTCNT AMP1MT MUTE CONTROL W 0 W 0 W 0 W 0 W 0 W 0 Read Register Address 00 Register name READ REGISTER D7 RTEST D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 - 39 - CXA3785R Register Function (ADD: 00) Address 00 R/W Default Register name AMP ENABLE PROTECTOR READ REGISTER D7 RTEST R/W 0 D6 AMP2EN W 0 D5 D4 D3 D2 D1 BIASEN W 0 D0 AMPEN W 0 PROMSK HPERREN HPOLPEN REGOLPEN W 1 W 1 W 1 W 1 D7: RTEST Read register D6: AMP2EN AMP2 enable "0" OFF (default) "1" ON D5: PROMSK X_PROTECTOUT mask control "0" Mask OFF "1" Mask ON (default) (X_PROTECTOUT function OFF) D4: HPERREN HP bias short error to VFAULT enable "0" OFF "1" ON (default) D3: HPOLPEN HP bias over load protect "0" OFF "1" ON (default) D2: REGOLPEN REGAUD over load protect "0" OFF "1" ON (default) D1: BIASEN Amp bias enable "0" OFF (default) "1" ON D0: AMPEN HPAMP, AMP1, AMP3, AMP4 enable "0" OFF (default) "1" ON - 40 - CXA3785R Register Function (ADD: 01) Address 01 R/W Default HP/AMP1 GAIN W 0 Register name D7 D6 D5 D4 D3 D2 D1 D0 HPAG[3:0] W 0 W 0 W 0 W 0 AMP1AG[3:0] W 0 W 0 W 0 D7-4: HPAG[3:0] HP gain control "0000" 0dB (default) "0001" 8dB "0010" 9dB "0011" 10dB "0100" 11dB "0101" 12dB "0110" 13dB "0111" 14dB "1000" 15dB "1001" 16dB "1010" 17dB "1011" 18dB "1100" 19dB "1101" 20dB "1110" Don't care "1111" Don't care D3-0: AMP1AG[3:0] AMP1 gain control "0000" 0dB (default) "0001" 4dB "0010" 5dB "0011" 6dB "0100" 7dB "0101" 8dB "0110" 9dB "0111" 10dB "1000" 11dB "1001" 12dB "1010" 13dB "1011" 14dB "1100" 15dB "1101" 16dB "1110" Don't care "1111" Don't care - 41 - CXA3785R Register Function (ADD: 02) Address 02 R/W Default AMP2/AMP3 GAIN W 0 Register name D7 D6 D5 D4 D3 D2 D1 D0 AMP2AG[3:0] W 0 W 0 W 0 W 0 AMP3AG[3:0] W 0 W 0 W 0 D7-4: AMP2AG[3:0] AMP2 gain control "0000" 0dB (default) "0001" 4dB "0010" 5dB "0011" 6dB "0100" 7dB "0101" 8dB "0110" 9dB "0111" 10dB "1000" 11dB "1001" 12dB "1010" 13dB "1011" 14dB "1100" 15dB "1101" 16dB "1110" Don't care "1111" Don't care D3-0: AMP3AG[3:0] AMP3 gain control "0000" 0dB (default) "0001" 4dB "0010" 5dB "0011" 6dB "0100" 7dB "0101" 8dB "0110" 9dB "0111" 10dB "1000" 11dB "1001" 12dB "1010" 13dB "1011" 14dB "1100" 15dB "1101" 16dB "1110" Don't care "1111" Don't care - 42 - CXA3785R Register Function (ADD: 03) Address 03 R/W Default DETUNREG AMP3SEL Register name D7 D6 D5 D4 D3 D2 D1 D0 AMP3SEL_R[1:0] W 0 W 0 AMP3SEL_L[1:0] W 0 W 0 REGAUD[1:0] W 0 W 0 DETUNREG[1:0] W 0 W 0 D7-6: AMP3SEL_R[1:0] AMP3 Rch selector control "00" SEL1INL (default) "01" SEL2INL "10" SEL1INR "11" SEL2INR D5-4: AMP3SEL_L[1:0] AMP3 Lch selector control "00" SEL1INL (default) "01" SEL2INL "10" SEL1INR "11" SEL2INR D3-2: REGAUD[1:0] REGAUD output voltage control "00" 9V (default) "01" 10V "10" 11V "11" 12V D1-0: DETUNREG[1:0] UNREG detector voltage control "00" 6V (default) "01" 8V "10" 10V "11" 12V - 43 - CXA3785R Register Function (ADD: 04) Address 04 R/W Default MUTE CONTROL Register name D7 D6 D5 D4 D3 D2 D1 AMP2MT W 0 D0 AMP3MT W 0 HPMTSEL AMP1MTSEL AMP2MTSEL AMP3MTSEL HPMTCNT AMP1MT W 0 W 0 W 0 W 0 W 0 W 0 D7: HPMTSEL HP select mute control "0" no select (default) "1" select D6: AMP1MTSEL AMP1 select mute control "0" no select (default) "1" select D5: AMP2MTSEL AMP2 select mute control "0" no select (default) "1" select D4: AMP3MTSEL AMP3 select mute control "0" no select (default) "1" select D3: HPMTCNT HP mute control "0" Mute (default) "1" Un-mute D2: AMP1MT AMP1 mute control "0" Mute (default) "1" Un-mute D1: AMP2MT AMP2 mute control "0" Mute (default) "1" Un-mute D0: AMP3MT AMP3 mute control "0" Mute (default) "1" Un-mute - 44 - CXA3785R Register Function (Read Register) Address 00 Register name READ REGISTER D7 RTEST D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 D7: RTEST Read register - 45 - CXA3785R Application Circuit External audio power amplifier COM REGAUD 2.2F 2.2F 2.2F 2.2F 2.2F 10F 48 DVDD Rp 47 46 45 44 43 42 41 40 39 10F 23 37 36 35 34 2.2F 33 External audio power amplifier External audio power amplifier 49 Rp AMP4 (Differential input amp) 32 SELECTOR 4:1 REGAUD 10F DVDD 50 BGR 31 30 AMP3AG (+4 to +16dB/1dB) 2SJ668 51 52 53 BGR Logic 10F 10F SELECTOR 4:1 29 2.2F 28 27 2.2F 0.1F VCC_XXXX 100F 54 55 56 DETAUD Bandgap reference AMP1OUT DETUNREG Current reference 30k DET33 30k 26 4.7F 25 Over 10F AMP2OUT 57 AMP3OUT Mute control 60k 24 23 REGAUD 2.2F 58 59 SPDET_L SPDET_R 3rd order LPF 3rd order LPF 3rd order LPF 3rd order LPF AMP2AG (+4 to +16dB/1dB) 22 21 20 19 AMP1AG (+4 to +16dB/1dB) Speaker amplifier 60 100k 10F 61 4.7F 100k 100k 4.7F 62 63 64 10F 2.2F REF Speaker amplifier 18 2.2F HPAG (+8 to +20dB/1dB) 17 7 2.2F 100k 1 2.2F 2.2F 2 100 3 4 5 6 REGAUD 100 8 2.2F 9 10 2.2F 11 2.2F 12 REGAUD 13 10F 14 15 10F 16 2.2F External audio power amplifier Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 46 - CXA3785R Package Outline (Unit: mm) - 47 - Sony Corporation |
Price & Availability of CXA3785R
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |