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19-4121; Rev 2; 6/09
KIT ATION EVALU BLE AVAILA
Quad-Output Controller for Low-Power Architecture
General Description Features
o Fixed-Frequency, Current-Mode Controllers o 5.5V to 28V Input Range (Step-Down) or 3V to 5V Input Range (Step-Up) o 1x Step-Up or Step-Down Controller o 1x Internal 5AP-P Step-Down Regulator o 1x Internal 3AP-P Step-Down Regulator o 1x 2A Source/Sink Linear Regulator with Dynamic REFIN o Internal BST Diodes o Internal 5V, 50mA Linear Regulator o Fault Protection--Undervoltage, Overvoltage, Thermal, Peak Current Limit o Independent Enable Inputs and Power-Good Outputs o Voltage-Controlled Soft-Start o High-Impedance Shutdown o 10A (typ) Shutdown Current
MAX17017
The MAX17017 is a quad-output controller for ultramobile portable computers (UMPCs) that rely on a lowpower architecture. The MAX17017 provides a compact, low-cost controller capable of providing four independent regulators--a main stage, a 3AP-P internal stepdown, a 5AP-P internal step-down, and a 2A source/sink linear regulator. The main regulator can be configured as either a stepdown converter (for 2 to 4 Li+ cell applications) or as a step-up converter (for 1 Li+ cell applications). The internal switching regulators include 5V synchronous MOSFETs that can be powered directly from a single Li+ cell or from the main 3.3V/5V power stages. Finally, the linear regulator is capable of sourcing and sinking 2A to support DDR termination requirements or to generate a fixed output voltage. The step-down converters use a peak current-mode, fixed-frequency control scheme--an easy to implement architecture that does not sacrifice fast-transient response. This architecture also supports peak currentlimit protection and pulse-skipping operation to maintain high efficiency under light-load conditions. Separate enable inputs and independent open-drain power-good outputs allow flexible power sequencing. A soft-start function gradually ramps up the output voltage to reduce the inrush current. Disabled regulators enter high-impedance states to avoid negative output voltage created by rapidly discharging the output through the low-side MOSFET. The MAX17017 also includes output undervoltage, output overvoltage, and thermal-fault protection. The MAX17017 is available in a 48-pin, 6mm x 6mm thin QFN package.
Ordering Information
PART TEMP RANGE PIN-PACKAGE MAX17017GTM+ -40C to +105C 48 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Pin Configuration
TOP VIEW
POKB POKA 26 BSTB BSTA DHA DLA FBB LXB LXB LXB LXA FBA 25 24 CSPA 23 CSNA 22 AGND 21 REF 20 FREQ 19 UP/DN 18 INA 17 VCC 16 BYP 15 LDO5 14 INLDO EXPOSED PAD = GND 1 POKC 2 BSTC 3 LXC 4 LXC 5 LXC 6 LXC 7 OUTD 8 OUTD 9 IND 10 FBD 11 VTTR 12 REFIND 13 SHDN
36 ONB 37 SYNC 38 ONA 39 INBC 40 INBC 41 INBC 42 INBC 43 VDD 44 POKD 45 OND 46 ONC 47 FBC 48
35
34
33
32
31
30
29
28
27
Applications
1-to-4 Li+ Cell Battery-Powered Devices Low-Power Architecture Ultra-Mobile PC (UMPC) Portable Gaming Notebook and Subnotebook Computers PDAs and Mobile Communicators
MAX17017
+
THIN QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quad-Output Controller for Low-Power Architecture MAX17017
ABSOLUTE MAXIMUM RATINGS
INLDO, SHDN to GND............................................-0.3V to +28V LDO5, INA, VDD, VCC to GND ..................................-0.3V to +6V DHA to LXA .............................................-0.3V to (VBSTA + 0.3V) ONA, ONB, ONC, OND to GND ...............................-0.3V to +6V POKA, POKB, POKC, POKD to GND .........-0.3V to (VCC + 0.3V) REF, REFIND, FREQ, UP/DN, SYNC to GND ........................................-0.3V to (VCC + 0.3V) FBA, FBB, FBC, FBD to GND .....................-0.3V to (VCC + 0.3V) BYP to GND ............................................-0.3V to (VLDO5 + 0.3V) CSPA, CSNA to GND .................................-0.3V to (VCC + 0.3V) DLA to GND................................................-0.3V to (VDD + 0.3V) INBC, IND to GND....................................................-0.3V to +6V OUTD to GND............................................-0.3V to (VIND + 0.3V) VTTR to GND.............................................-0.3V to (VBYP + 0.3V) LXB, LXC to GND ....................................-1.0V to (VINBC + 0.3V) BSTB to GND ....................................(VDD - 0.3V) to (VLXB + 6V) BSTC to GND ....................................(VDD - 0.3V) to (VLXC + 6V) BSTA to GND ....................................(VDD - 0.3V) to (VLXA + 6V) REF Short-Circuit Current......................................................1mA Continuous Power Dissipation (TA = +70C) Multilayer PCB: 48-Pin 6mm x 6mm2 TQFN (T4866-2 derated 37mW/C above +70C) ....................2.9W Operating Temperature Range .........................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS UP/DN = GND (step-up), INA Input Voltage Range UP/DN = LDO5 (step-down), INLDO, INA = LDO5 UP/DN = GND (step-up), INA = INLDO, rising edge hysteresis = 100mV INA Undervoltage Threshold VINA(UVLO) UP/DN = LDO5 (step-down), INA = VCC, rising edge, hysteresis = 160mV TA = 0C to +85C MIN 3.0 5.5 2.5 4.0 2.3 UP/DN = GND (step-up) 2.9 3.0 2.7 4.2 TYP MAX 5.0 24 2.9 V 4.4 5.5 V V V UNITS
INBC Input Voltage Range Minimum Step-Up Startup Voltage SUPPLY CURRENTS VINLDO Shutdown Supply Current VINLDO Suspend Supply Current VCC Shutdown Supply Current VDD Shutdown Supply Current INA Shutdown Current VCC Supply Current Main Step-Down Only IINA IIN(SHDN) IIN(SUS) VIN = 5.5V to 26V, SHDN = GND VINLDO = 5.5V to 26V, ON_ = GND, SHDN = INLDO SHDN = ONA = ONB = ONC = OND = GND, TA = +25C SHDN = ONA = ONB = ONC = OND = GND, TA = +25C SHDN = ONA = ONB = ONC = OND = GND, UP/DN = VCC ONA = VCC, ONB = ONC = OND = GND; does not include switching losses, measured from VCC
10 50 0.1 0.1 7
15 80 1 1 10
A A A A A
210
300
A
2
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Quad-Output Controller for Low-Power Architecture
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER VCC Supply Current Main Step-Down and Regulator B VCC Supply Current Main Step-Down and Regulator C VCC Supply Current Main Step-Down and Regulator D INA Supply Current (Step-Down) INA + VCC Step-Up Supply Current 5V LINEAR REGULATOR (LDO5) LDO5 Output Voltage LDO5 Short-Circuit Current Limit BYP Switchover Threshold LDO5-to-BYP Switch Resistance 1.25V REFERENCE Reference Output Voltage Reference Load Regulation Reference Undervoltage Lockout OSCILLATOR FREQ = VCC Oscillator Frequency fOSC fSWA Switching Frequency Maximum Duty Cycle (All Switching Regulators) Minimum On-Time (All Switching Regulators) fSWB fSWC DMAX tON(MIN) FREQ = VCC or GND FREQ = REF FREQ = REF FREQ = GND Main step-up/step-down (regulator A) Regulator B Regulator C 90 0.9 500 750 1.0 1/2 fOSC fOSC 1/2 fOSC 93.5 90 75 VCC + 0.3 V Step-down configuration (UP/DN = VCC) 1.0 VCC + 0.3 % ns MHz 1.1 kHz MHz VREF _VREF VREF(UVLO) No load IREF = -1A to +50A 1.237 1.25 3 1.0 1.263 10 V mV V VBYP RBYP VLDO5 VINLDO = 5.5V to 26V, ILDO5 = 0 to 50mA, BYP = GND LDO5 = BYP = GND Rising edge LDO5 to BYP, VBYP = 5V, ILDO5 = 50mA 4.8 70 5.0 160 4.65 1.5 4 5.2 250 V mA V _ IINA IINA SYMBOL CONDITIONS ONA = ONB = VCC, ONC = OND = GND; does not include switching losses, measured from VCC ONA = ONC = VCC, ONB = OND = GND; does not include switching losses, measured from VCC ONA = OND = VCC, ONB = ONC = GND; does not include switching losses; measured from VCC ONA = VCC, UP/DN = VCC (step-down) ONA = VCC, UP/DN = GND (step-up) TA = 0C to +85C MIN TYP 280 MAX 350 UNITS
MAX17017
A
280
350
A
2.2 40 320
3 60 410
mA A A
REGULATOR A (Main Step-Up/Step-Down) Step-up configuration (UP/DN = GND) Output-Voltage Adjust Range 3.0
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Quad-Output Controller for Low-Power Architecture MAX17017
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS Step-up configuration (UP/DN = GND), VCSPA - VCSNA = 0 to 20mV, 90% duty cycle Step-down configuration (UP/DN = VCC), VCSPA - VCSNA = 0mV, 90% duty cycle Step-up configuration (UP/DN = GND), VCSPA - VCSNA = 0mV, 90% duty cycle VFBA Step-down configuration (UP/DN = VCC), VCSPA - VCSNA = 0 to 20mV, 90% duty cycle Step-up configuration (UP/DN = GND), VCSPA - VCSNA = 0 to 20mV Step-down configuration (UP/DN = VCC), VCSPA - VCSNA = 0 to 20mV UP/DN = GND or VCC, 0 to 100% duty cycle IFBA VCSA ICSA VILIMA VIDLEA VIZX RDH RDL IDH IDL(SRC) IDL(SNK) RBSTA DHA forced high and low DLA forced high DLA forced low DHA forced to 2.5V DLA forced to 2.5V DLA forced to 2.5V TA = +25C 18 Step-up (UP/DN = GND) Step-down (UP/DN = VCC) 5 10 -100 0 40 20 4 1 2.5 2.5 1.5 0.7 0.7 1.5 5 5 5 3 TA = 0C to +85C MIN 0.975 TYP 0.99 MAX 1.013 V 0.968 0.959 0.97 1.003 1.013 V 0.930 1.003 UNITS
FBA Regulation Voltage
VFBA
FBA Regulation Voltage (Overload)
-20 mV -40 10 16 -5 16 mV 22 +100 VCC + 0.3V 60 22 nA V A mV mV mV A A
FBA Load Regulation
VFBA
FBA Line Regulation
FBA Input Current Current-Sense Input CommonMode Range Current-Sense Input Bias Current Current-Limit Threshold (Positive) Idle ModeTM Threshold Zero-Crossing Threshold DHA Gate Driver On-Resistance DLA Gate Driver On-Resistance DHA Gate Driver Source/Sink Current DLA Gate Driver Source/Sink Current BSTA Switch On-Resistance
UP/DN = GND or VCC, TA = +25C
Idle Mode is a trademark of Maxim Integrated Products, Inc.
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Quad-Output Controller for Low-Power Architecture MAX17017
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS TA = 0C to +85C MIN 0.747 0.720 -5 7 -100 8 -5 75 40 3.0 3.45 0.8 100 ONB = GND, VLXB = GND or 5V; VINBC = 5V at TA = +25C ILXC = 0A, 0% duty cycle (Note 2) VFBC ILXC = 0 to 4A, 0% duty cycle (Note 2) 0 to 100% duty cycle IFBC TA = +25C High-side n-channel Low-side n-channel IPKC IIDLEC IZXC ILXC ONC = GND, VLXC = GND or 5V; VINBC = 5V at TA = +25C -20 5.0 VFBC/ILXC ILXC = 0 to 4A 12 -100 -20 +20 10 +100 150 80 4.0 TYP 0.755 MAX 0.762 0.762 UNITS
REGULATOR B (Internal 3A Step-Down Converter) FBB Regulation Voltage FBB Regulation Voltage (Overload) FBB Load Regulation FBB Line Regulation FBB Input Current Internal MOSFET On-Resistance LXB Peak Current Limit LXB Idle-Mode Trip Level LXB Zero-Crossing Trip Level LXB Leakage Current IPKB IIDLEB IZXB ILXB IFBB VFBB ILXB = 0% duty cycle (Note 2) ILXB = 0 to 2.5A, 0% duty cycle (Note 2) 0 to 100% duty cycle TA = +25C High-side n-channel Low-side n-channel VFBB/ILXB ILXB = 0 to 2.5A V V mV/A mV nA m A A mA A
REGULATOR C (Internal 5A Step-Down Converter) FBC Regulation Voltage FBC Regulation Voltage (Overload) FBC Load Regulation FBC Line Regulation FBC Input Current Internal MOSFET On-Resistance LXC Peak Current Limit LXC Idle-Mode Trip Level LXC Zero-Crossing Trip Level LXC Leakage Current 0.747 0.710 -7 14 -5 50 25 5.75 1.2 100 +20 16 +100 100 40 6.5 0.755 0.762 0.762 V V mV/A mV nA m A A mA A
REGULATOR D (Source/Sink Linear Regulator and VTTR Buffer) IND Input Voltage Range IND Supply Current IND Shutdown Current REFIND Input Range REFIND Input Bias Current OUTD Output Voltage Range VOUTD VFBD with respect to VREFIND, OUTD = FBD, IOUTD = +50A (source load) VFBD with respect to VREFIND, OUTD = FBD, IOUTD = -50A (sink load) IOUTD = 1A VREFIND = 0 to 1.5V, TA = +25C VIND OND = VCC OND = GND, TA = +25C 0.5 -100 0.5 -10 0 -17 -13 1 10 2.8 50 10 1.5 +100 1.5 0 mV +10 mV/A V A A V nA V
FBD Output Accuracy
VFBD
FBD Load Regulation
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Quad-Output Controller for Low-Power Architecture MAX17017
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER FBD Line Regulation FBD Input Current OUTD Linear Regulator Current Limit Current-Limit Soft-Start Time Internal MOSFET On-Resistance VTTR Output Accuracy VTTR Maximum Current Rating FAULT PROTECTION Upper threshold rising edge, hysteresis = 50mV Lower threshold falling edge, hysteresis = 50mV Upper threshold rising edge, hysteresis = 50mV Lower threshold falling edge, hysteresis = 50mV tPOK tOVP tUVP tUVP VPOK IPOK TSHDN FB_ forced 50mV beyond POK_ trip threshold FB_ forced 50mV above POK_ upper trip threshold FBA, FBB, or FBC forced 50mV below POK_ lower trip threshold FBD forced 50mV below POKD lower trip threshold ISINK = 3mA VFBA = 1.05V, VFBB = VFBC = 0.8V, VFBD = VREFIND + 50mV (POK high impedance); POK_ forced to 5V, TA = +25C Hysteresis = 15C Hysteresis = 20mV TA = +25C Hysteresis = 170mV TA = +25C TA = +25C 0.5 -1 0.5 -1 0.5 -1 160 1.6 +1 1.6 +1 1.6 +1 9 -14 6 -16 12 -12 12 -12 5 5 5 5000 0.4 1 14 % -9 16 % -6 s s s s V A C V A V A V A SYMBOL CONDITIONS VIND = 1.0V to 2.8V, IOUTD = 200mA VFBD = 0 to 1.5V, TA = +25C Source load Sink load With respect to internal OND signal High-side on-resistance Low-side on-resistance REFIND to VTTR IVTTR = 0.5mA IVTTR = 3mA -10 -20 5 +2 -2 160 120 180 250 450 +10 +20 TA = 0C to +85C MIN TYP 1 0.1 0.5 +4 -4 MAX UNITS mV A A s m mV mA
SMPS POK and Fault Thresholds
VTT LDO POKD and Fault Threshold
POK Propagation Delay Overvoltage Fault Latch Delay SMPS Undervoltage Fault Latch Delay VTT LDO Undervoltage Fault Latch Delay POK Output Low Voltage POK Leakage Currents Thermal-Shutdown Threshold GENERAL LOGIC LEVELS SHDN Input Logic Threshold SHDN Input Bias Current ON_ Input Logic Threshold ON_ Input Bias Current UP/DN Input Logic Threshold UP/DN Input Bias Current
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Quad-Output Controller for Low-Power Architecture
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL High (VCC) FREQ Input Voltage Levels FREQ Input Bias Current SYNC Input Logic Threshold SYNC Input Bias Current TA = +25C Unconnected/REF Low (GND) TA = +25C -2 1.5 -1 CONDITIONS TA = 0C to +85C MIN VCC - 0.4V 1.65 3.8 0.5 +2 3.5 +1 A V A V TYP MAX UNITS
MAX17017
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = -40C to +105C.) (Note 1)
PARAMETER SYMBOL CONDITIONS UP/DN = GND (step-up), INA Input Voltage Range UP/DN = LDO5 (step-down), INLDO, INA = LDO5 VINA(UVLO
)
TA = -40C to +105C MIN 3.0 5.5 2.4 3.9 2.3 TYP MAX 5.0 24 3.0
UNITS
V
UP/DN = GND (step-up), INA = INLDO, rising edge, hysteresis = 100mV UP/DN = LDO5 (step-down), INA = VCC, rising edge, hysteresis = 160mV UP/DN = GND (step-up)
INA Undervoltage Threshold
V 4.5 5.5 V V 15 80 10 A A A
INBC Input Voltage Range Minimum Step-Up Startup Voltage SUPPLY CURRENTS VINLDO Shutdown Supply Current VINLDO Suspend Supply Current INA Shutdown Current VCC Supply Current Main Step-Down Only VCC Supply Current Main Step-Down and Regulator B VCC Supply Current Main Step-Down and Regulator C IIN(SHDN) IIN(SUS) IINA VIN = 5.5V to 26V, SHDN = GND VINLDO = 5.5V to 26V, ON_ = GND, SHDN = INLDO SHDN = ONA = ONB = ONC = OND = GND, UP/DN = VCC ONA = VCC, ONB = ONC = OND = GND; does not include switching losses, measured from VCC ONA = ONB = VCC, ONC = OND = GND; does not include switching losses, measured from VCC ONA = ONC = VCC, ONB = OND = GND, does not include switching losses, measured from VCC
3.0
350
A
400
A
400
A
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Quad-Output Controller for Low-Power Architecture MAX17017
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = -40C to +105C.) (Note 1)
PARAMETER VCC Supply Current Main Step-Down and Regulator D INA Supply Current (Step-Down) INA + VCC Step-Up Supply Current 5V LINEAR REGULATOR (LDO5) LDO5 Output Voltage LDO5 Short-Circuit Current Limit 1.25V REFERENCE Reference Output Voltage Reference Load Regulation OSCILLATOR Oscillator Frequency Maximum Duty Cycle (All Switching Regulators) fOSC DMAX FREQ = GND 0.9 89 1.1 MHz % VREF VREF No load IREF = -1A to +50A 1.237 1.263 12 V mV VLDO5 VINLDO = 5.5V to 26V, ILDO5 = 0 to 50mA, BYP = GND LDO5 = BYP = GND 4.75 55 5.25 V mA IINA IINA SYMBOL CONDITIONS ONA = OND = VCC, ONB = ONC = GND, does not include switching losses, measured from VCC ONA = VCC, UP/DN = VCC (step-down) ONA = VCC, UP/DN = GND (step-up) TA = -40C to +105C MIN TYP MAX 3.5 75 475 UNITS
mA
A
REGULATOR A (Main Step-Up/Step-Down) Step-up configuration (UP/DN = GND) Output-Voltage Adjust Range Step-down configuration (UP/DN = VCC) Step-up configuration, VCSPA - VCSNA = 0mV, 90% duty cycle Step-down configuration, VCSPA - VCSNA = 0mV, 90% duty cycle Step-up configuration (UP/DN = GND), VCSPA - VCSNA = 0 to 20mV, 90% duty cycle Step-down configuration (UP/DN = VCC), VCSPA - VCSNA = 0 to 20mV, 90% duty cycle Step-up (UP/DN = GND) Step-down (UP/DN = VCC) VCSA VILIMA 1.0 0.970 0.963 0.954 0.925 5 10 0 17 3.0 VCC + 0.3V VCC + 0.3V 1.018 V 1.008 1.018 V 1.008 19 23 VCC + 0.3V 23 mV V mV
V
FBA Regulation Voltage
FBA Regulation Voltage (Overload)
VFBA
FBA Line Regulation Current-Sense Input CommonMode Range Current-Limit Threshold (Positive)
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Quad-Output Controller for Low-Power Architecture
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = -40C to +105C.) (Note 1)
PARAMETER SYMBOL CONDITIONS TA = -40C to +105C MIN 0.742 0.715 6 IPKB ILXC = 0A, 0% duty cycle (Note 2) VFBC IPKC VIND OND = VCC 0.5 VOUTD VFBD with respect to VREFIND, OUTD = FBD, IOUTD = +50A (source load) VFBD with respect to VREFIND, OUTD = FBD, IOUTD = -50A (sink load) IOUTD = 1A Source load Sink load High-side on-resistance Low-side on-resistance REFIND to VTTR IVTTR = 3mA -20 0.5 -12 0 -20 +2 -2 +4 -4 300 475 +20 ILXC = 0 to 4A, 0% duty cycle (Note 2) 2.7 0.742 0.705 11 5.0 1 TYP MAX 0.766 0.766 12 4.2 0.766 0.766 20 6.5 2.8 70 1.5 1.5 0 mV +12 mV/A A m mV UNITS
MAX17017
REGULATOR B (Internal 3A Step-Down Converter) FBB Regulation Voltage FBB Regulation Voltage (Overload) FBB Line Regulation LXB Peak Current Limit FBC Regulation Voltage FBC Regulation Voltage (Overload) FBC Line Regulation LXC Peak Current Limit IND Input Voltage Range IND Supply Current REFIND Input Range OUTD Output Voltage Range REGULATOR D (Source/Sink Linear Regulator and VTTR Buffer) V A V V REGULATOR C (Internal 5A Step-Down Converter) V V mV A VFBB ILXB = 0A, 0% duty cycle (Note 2) ILXB = 0 to 2.5A , 0% duty cycle (Note 2) V V mV A
FBD Output Accuracy
VFBD
FBD Load Regulation OUTD Linear Regulator Current Limit Internal MOSFET On-Resistance VTTR Output Accuracy
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Quad-Output Controller for Low-Power Architecture MAX17017
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN = VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA = -40C to +105C.) (Note 1)
PARAMETER FAULT PROTECTION Upper threshold rising edge, hysteresis = 50mV SMPS POK and Fault Thresholds Lower threshold falling edge, hysteresis = 50mV Upper threshold rising edge, hysteresis = 50mV Lower threshold falling edge, hysteresis = 50mV VPOK I SINK = 3mA Hysteresis = 20mV Hysteresis = 170mV High (VCC) FREQ Input Voltage Levels SYNC Input Logic Threshold Unconnected/REF Low (GND) 1.5 0.5 0.5 0.5 VCC - 0.4V 1.65 3.8 0.5 3.5 V V -16 6 -16 -8 16 % -6 0.4 1.6 1.6 1.6 V V V V 8 16 % SYMBOL CONDITIONS TA = -40C to +105C MIN TYP MAX UNITS
VTT LDO POKD and Fault Threshold POK Output Low Voltage GENERAL LOGIC LEVELS SHDN Input Logic Threshold ON_ Input Logic Threshold UP/DN Input Logic Threshold
Note 1: Limits are 100% production tested at TA = +25C. Maximum and minimum limits are guaranteed by design and characterization. Note 2: Regulation voltage tested with slope compensation. The typical value is equivalent to 0% duty cycle. In real application, the regulation voltage is higher due to the line regulation times the duty cycle.
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Quad-Output Controller for Low-Power Architecture
Typical Operating Characteristics
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
SMPS REGULATOR A EFFICIENCY vs. LOAD CURRENT
MAX17017 toc01
MAX17017
SMPS REGULATOR A OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17017 toc02
SMPS REGULATOR B EFFICIENCY vs. LOAD CURRENT
95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 VIN = 5V VIN = 3.3V VIN = 2.5V
MAX17017 toc03
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0.001 VIN = 12V VIN = 20V VIN = 8V
5.05 5.00 OUTPUT VOLTAGE (V) 4.95 VIN = 12V 4.90 4.85 VIN = 8V 4.80 4.75 VIN = 20V
100
0.01
0.1 LOAD CURRENT (A)
1
10
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOAD CURRENT (A)
50 0.001
0.01
0.1 LOAD CURRENT (A)
1
10
SMPS REGULATOR B OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17017 toc04
SMPS REGULATOR C EFFICIENCY vs. LOAD CURRENT
85 80 EFFICIENCY (%) 75 70 65 60 55 VIN = 5V VIN = 3.3V VIN = 2.5V
MAX17017 toc05
1.82
90
OUTPUT VOLTAGE (V)
VIN = 5V
1.77 VIN = 2.5V VIN = 3.3V
1.72 0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (A)
50 0.001
0.01
0.1 LOAD CURRENT (A)
1
10
SMPS REGULATOR C OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17017 toc06
REGULATOR D VOLTAGE vs. SOURCE/SINK LOAD CURRENT
0.925 0.920 VTT VOLTAGE (V) 0.915 0.910 0.905 0.900 0.895
MAX17017 toc07
1.05 1.04 OUTPUT VOLTAGE (V) 1.03 1.02 1.01 1.00 0.99 0.98 0 VIN = 2.5V VIN = 3.3V VIN = 5V
0.930
0.890 0.885 0.880 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOAD CURRENT (A)
LOAD CURRENT (A)
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11
Quad-Output Controller for Low-Power Architecture MAX17017
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
REG A STARTUP WAVEFORM (HEAVY LOAD)
MAX17017 toc08
REG A SHUTDOWN WAVEFORM
MAX17017 toc09
REG B STARTUP WAVEFORM (HEAVY LOAD)
MAX17017 toc10
ONA ONA OUTA POKA ILA ILA LXA LXA 400s/div ONA: 5V/div OUTA: 5V/div POKA: 5V/div ILA: 5A/div LXA: 10V/div RLOAD = 1.6 ONA: 5V/div OUTA: 5V/div POKA: 5V/div ILA: 5A/div LXA: 10V/div 400s/div RLOAD = 2.5 ONB: 5V/div OUTB: 2V/div POKB: 5V/div ILB: 2A/div LXB: 5V/div LXB 400s/div RLOAD = 1.01 ILB OUTA POKA ONB OUTB POKB
REG B SHUTDOWN WAVEFORM
MAX17017 toc11
REG C STARTUP WAVEFORM (HEAVY LOAD)
MAX17017 toc12
REG C SHUTDOWN
MAX17017 toc13
ONB OUTB POKB ONC OUTC POKC ILB ILC LXB LXC 400s/div ONB: 5V/div OUTB: 2V/div POKB: 5V/div ILB: 2A/div LXB: 5V/div RLOAD = 0.8 ONC: 5V/div OUTC: 1V/div POKC: 5V/div ILC: 5A/div LXC: 5V/div 400s/div RLOAD = 0.25
ONC OUTC POKC
ILC
LXC
100s/div ONC: 5V/div OUTC: 1V/div POKC: 5V/div ILC: 5A/div LXC: 5V/div RLOAD = 0.25
12
______________________________________________________________________________________
Quad-Output Controller for Low-Power Architecture MAX17017
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
REG A LOAD TRANSIENT (1A TO 3.2A)
MAX17017 toc14
REG B LOAD TRANSIENT (0.4A TO 2A)
MAX17017 toc15
REG C LOAD TRANSIENT (0.8A TO 3A)
MAX17017 toc16
OUTA
OUTB
OUTC
LXA
LXB
LXC
ILA ILB IOUTA 20s/div OUTA: 100mV/div LXA: 10V/div ILA: 2A/div IOUTA: 2A/div VINA = 12V, LOAD TRANSIENT IS FROM 1A TO 3.2A OUTB: 50mV/div LXB: 5V/div ILB: 1A/div IOUTB: 2A/div IOUTB 20s/div VINBC = 5V, 0.4A TO 2.0A LOAD TRANSIENT
ILC IOUTC 20s/div OUTC: 50mV/div LXC: 5V/div ILC: 2A/div IOUTC: 2A/div VINBC = 5V, 0.8A TO 3.0A LOAD TRANSIENT
REG D LOAD TRANSIENT (SOURCE/SINK)
MAX17017 toc17
REG D LOAD TRANSIENT (SINK)
MAX17017 toc18
REG D LOAD TRANSIENT (SOURCE)
MAX17017 toc19
OUTD OUTD OUTD
IOUTD
IOUTD IOUTD
20s/div OUTD: 20mV/div IOUTD: 1A/div IND = 1.8V, REFIND = 0.9V, COUT = 2 x 10F, LOAD TRANSIENT IS FROM 1A SOURCING TO 1A SINKING OUTD: 10mV/div IOUTD: 1A/div
20s/div IND = 1.8V, REFIND = 0.9V, COUT = 2 x 10F, LOAD TRANSIENT IS FROM 0 TO 1A SINKING OUTD: 10mV/div IOUTD: 1A/div
20s/div IND = 1.8V, REFIND = 0.9V, COUT = 2 x 10F, LOAD TRANSIENT IS FROM 0 TO 1A SOURCING
______________________________________________________________________________________
13
Quad-Output Controller for Low-Power Architecture MAX17017
Pin Description
PIN 1 NAME POKC FUNCTION Open-Drain Power-Good Output for the Internal 5A Step-Down Converter. POKC is low if FBC is more than 12% (typ) above or below the nominal 0.75V feedback regulation threshold. POKC is held low during startup and in shutdown. POKC becomes high impedance when FBC is in regulation. Boost Flying Capacitor Connection for the Internal 5A Step-Down Converter. The MAX17017 includes an internal boost switch/diode connected between VDD and BSTC. Connect to an external capacitor as shown in Figure 1. Inductor Connection for the Internal 5A Step-Down Converter. Connect LXC to the switched side of the inductor. Source/Sink Linear Regulator Output. Bypass OUTD with 2x 10F or greater ceramic capacitors to ground. Dropout needs additional output capacitance (see the VTT LDO Output Capacitor Selection (COUTD) section). Source/Sink Linear Regulator Input. Bypass IND with a 10F or greater ceramic capacitor to ground. Feedback Input for the Internal Source/Sink Linear Regulator. FBD tracks and regulates to the REFIND voltage. Ouput of Reference Buffer. Bypass with 0.22F for 3mA of output current. Dynamic Reference Input Voltage for the Source/Sink Linear Regulator and the Reference Buffer. The linear regulator feedback threshold (FBD) tracks the REFIND voltage. Shutdown Control Input. The device enters its 5A supply current shutdown mode if VSHDN is less than the SHDN input falling edge trip level and does not restart until VSHDN is greater than the SHDN input rising edge trip level. Connect SHDN to VINLDO for automatic startup of LDO5. Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to GND with a 0.1F or greater ceramic capacitor close to the controller. In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply. Connect BYP and INLDO to the system's 5V supply to effectively disable the linear regulator. 5V Internal Linear Regulator Output. Bypass with a 4.7F or greater ceramic capacitor. The 5V linear regulator provides the bias power for the gate drivers (VDD) and analog control circuitry (VCC). The linear regulator sources up to 50mA (max guaranteed). When BYP exceeds 4.65V (typ), the MAX17017 bypasses the linear regulator through a 1.5_ bypass switch. When the linear regulator is bypassed, LDO5 supports loads up to 100mA. In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply. Bypass SHDN to ground and leave LDO5 unconnected. Connect BYP and INLDO to effectively disable the linear regulator. Linear Regulator Bypass Input. When BYP exceeds 4.65V, the controller shorts LDO5 to BYP through a 1.5_ bypass switch and disables the linear regulator. When BYP is low, the linear regulator remains active. The BYP input also serves as the VTTR buffer supply, allowing VTTR to remain active even when the source/sink linear regulator (OUTD) has been disabled under system standby/suspend conditions. In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply. Bypass LDO5 to ground with a 1F capacitor and leave this output unconnected. Connect BYP and INLDO to the system's 5V supply to effectively disable the linear regulator.
2
BSTC
3-6
LXC
7, 8 9 10 11 12
OUTD IND FBD VTTR REFIND
13
SHDN
14
INLDO
15
LDO5
16
BYP
14
______________________________________________________________________________________
Quad-Output Controller for Low-Power Architecture
Pin Description (continued)
PIN 17 NAME VCC FUNCTION 5V Analog Bias Supply. VCC powers all the analog control blocks (error amplifiers, current-sense amplifiers, fault comparators, etc.) and control logic. Connect VCC to the 5V system supply with a series 10_ resistor, and bypass to analog ground using a 1F or greater ceramic capacitor. Input to the Circuit in Reg A in Boost Mode. Connect INA to the input in step-up mode (UP/DN = GND) and connect INA to LDO5 in step-down mode (UP/DN = VCC). Converter Configuration Selection Input for Regulator A. When UP/DN is pulled high (UP/DN = VCC), regulator A operates as a step-down converter (Figure 1). When UP/DN is pulled low (UP/DN = GND), regulator A operates as a step-up converter. Trilevel Oscillator Frequency Selection Input. FREQ = VCC: RegA = 250kHz, RegB = 500kHz, RegC = 250kHz FREQ = REF: RegA = 375kHz, RegB = 750kHz, RegC = 375kHz FREQ = GND: RegA = 500kHz, RegB = 1MHz, RegC = 500kHz 1.25V Reference-Voltage Output. Bypass REF to analog ground with a 0.1F ceramic capacitor. The reference sources up to 50A for external loads. Loading REF degrades output voltage accuracy according to the REF load-regulation error. The reference shuts down when the system pulls SHDN low in buck mode (UP/DN = GND) or when the system pulls ONA low in boost mode (UP/DN = VCC). Analog Ground Negative Current-Sense Input for the Main Switching Regulator. Connect to the negative terminal of the currentsense resistor. Due to the CSNA bias current requirements, limit the series impedance to less than 10. Positive Current-Sense Input for the Main Switching Regulator. Connect to the positive terminal of the currentsense resistor. Due to the CSPA bias current requirements, limit the series impedance to less than 10. Feedback Input for the Main Switching Regulator. FBA regulates to 1.0V. Open-Drain Power-Good Output for the Main Switching Regulator. POKA is low if FBA is more than 12% (typ) above or below the nominal 1.0V feedback regulation point. POKA is held low during soft-start and in shutdown. POKA becomes high impedance when FBA is in regulation. High-Side Gate-Driver Output for the Main Switching Regulator. DHA swings from LXA to BSTA. Inductor Connection of Converter A. Connect LXA to the switched side of the inductor. Boost Flying Capacitor Connection of Converter A. The MAX17017 includes an internal boost switch/diode connected between VDD and BSTA. Connect to an external capacitor as shown in Figure 1. Low-Side Gate-Driver Output for the Main Switching Regulator. DLA swings from GND to VDD. Inductor Connection for the Internal 3A Step-Down Converter. Connect LXB to the switched side of the inductor. Boost Flying Capacitor Connection for the Internal 3A Step-Down Converter. The MAX17017 includes an internal boost switch/diode connected between VDD and BSTB. Connect to an external capacitor as shown in Figure 1. Open-Drain Power-Good Output for the Internal 3A Step-Down Converter. POKB is low if FBB is more than 12% (typ) above or below the nominal 0.75V feedback-regulation threshold. POKB is held low during softstart and in shutdown. POKB becomes high impedance when FBB is in regulation.
MAX17017
18
INA
19
UP/DN
20
FREQ
21
REF
22 23 24 25 26 27 28 29 30 31, 32, 33 34
AGND CSNA CSPA FBA POKA DHA LXA BSTA DLA LXB
BSTB
35
POKB
______________________________________________________________________________________
15
Quad-Output Controller for Low-Power Architecture MAX17017
Pin Description (continued)
PIN 36 37 38 39 NAME FBB ONB SYNC ONA FUNCTION Feedback Input for the Internal 3A Step-Down Converter. FBB regulates to 0.75V. Switching Regulator B Enable Input. When ONB is pulled low, LXB is high impedance. When ONB is driven high, the controller enables the 3A internal switching regulator. External Synchronization Input. Used to override the internal switching frequency. Switching Regulator A Enable Input. When ONA is pulled low, DLA and DHA are pulled low. When ONA is driven high, the controller enables the step-up/step-down converter. Input for Regulators B and C. Power INBC from a 2.5V to 5.5V supply. Internally connected to the drain of the high-side MOSFETs for both regulator B and regulator C. Bypass to PGND with 2x 10F or greater ceramic capacitors to support the RMS current. 5V Bias Supply Input for the Internal Switching Regulator Drivers. Bypass with a 1F or greater ceramic capacitor. Provides power for the BSTB and BSTC driver supplies. Open-Drain Power-Good Output for the Internal Source/Sink Linear Regulator. POKD is low if FBD is more than 10% (typ) above or below the REFIND regulation threshold. POKD is held low during soft-start and in shutdown. POKD becomes high impedance when FBD is in regulation. Source/Sink Linear Regulator (Regulator D) and Reference Buffer Enable Input. When OND is pulled low, OUTD is high impedance. When OND is driven high, the controller enables the source/sink linear regulator. Switching Regulator C Enable Input. When ONC is pulled low, LXC is high impedance. When ONC is driven high, the controller enables the 5A internal switching regulator. Feedback Input for the Internal 5A Step-Down Converter. FBC regulates to 0.75V. Power Ground. The source of the low-side MOSFETs (REG B and REG C), the drivers for all switching regulators, and the sink MOSFET of the VTT LDO are all internally connected to the exposed pad. Connect the exposed backside pad to system power ground planes through multiple vias.
40-43
INBC
44
VDD
45
POKD
46 47 48 EP
OND ONC FBC PGND
Detailed Description
The MAX17017 standard application circuit (Figure 1) provides a 5V/5AP-P main stage, a 1.8V/3AP-P VDDQ and 0.9A/2A VTT outputs for DDR, and a 1.05V/5AP-P chipset supply. The MAX17017 supports four power outputs--one highvoltage step-down controller, two internal MOSFET step-down switching regulators, and one high-current source/sink linear regulator. The step-down switching regulators use a current-mode fixed-frequency architecture compensated by the output capacitance. An internal 50mA 5V linear regulator provides the bias supply and driver supplies, allowing the controller to power up from input supplies greater than 5.5V.
Fixed 5V Linear Regulator (LDO5)
An internal linear regulator produces a preset 5V lowcurrent output from INLDO. LDO5 powers the gate drivers for the external MOSFETs, and provides the bias
supply required for the SMPS analog controller, reference, and logic blocks. LDO5 supplies at least 50mA for external and internal loads, including the MOSFET gate drive, which typically varies from 5mA to 15mA per switching regulator, depending on the switching frequency. Bypass LDO5 with a 4.7F or greater ceramic capacitor to guarantee stability under the fullload conditions. The MAX17017 switch-mode step-down switching regulators require a 5V bias supply in addition to the mainpower input supply. This 5V bias supply is generated by the controller's internal 5V linear regulator (LDO5). This boot-strappable LDO allows the controller to power up independently. The gate-driver VDD input supply is typically connected to the fixed 5V linear regulator output (LDO5). Therefore, the 5V LDO supply must provide LDO5 (PWM controller) and the gatedrive power during power-up.
16
______________________________________________________________________________________
Quad-Output Controller for Low-Power Architecture MAX17017
13 C1 4.7F, 6V 0603 SHDN INLDO 14 C7 1F, 16V 0603 24 23 28 30 PWR C4 0.1F, 6V 0402 PWR C8 4.7F, 16V 1206 C9 4.7F, 16V 1206 PWR C10 22F, 16V C-CASE 16TQC22M 6V TO 16V
15 44 19
LDO5 VDD UP/DN
BSTA DHA LXA DLA
PWR
PWR L1 3.3H, 6A, 30m 6.7mm x 7.7mm x 3.0mm R15 4m (NEC/TOKIN: NH1 1% MPLC0730L3R3)
C2 1.0F, 6V 0402
R1 10 5%, 0402 17 18 VCC INA
NL1 PWR C21 OPEN 0402 C21 680pF, 6V 0402 AGND C12 1F, 16V 0402 PWR PWR C5 L2 0.1F, 6V 1.0H, 6.8A, 14.2m 0402 5.8mm x 6.2mm x 3.0mm (NEC/TOKIN: MPLC0525L1RO) R5 14k 1%, 0402 R6 10.0k 1%, 0402 C13 10F, 6V 0805 C16 OPEN 0402 AGND PWR R3 40k 1%, 0402
5V, 4A C14 150F, 35m, 6V B2 CASE
AGND ON OFF ON OFF ON OFF ON OFF 39 37 47 46 ONA ONB ONC OND
29 CSPA 27 CSNA 25 16 40-43 AGND
FBA BYP 4x INBC
R4 10k 1%, 0402 AGND
5V SMPS OUTPUT R9 100k 5%, 0402
MAX17017
R10 100k 5%, 0402 R11 100k 5%, 0402 R12 100k 5%, 0402 BSTB 26 35 1 45 38 AGND 3x LXB 34
POKA POKB POKC POKD SYNC
31, 32, 33 36
1.8V, 2.5A C14 330F 18m, 2.5V, B2 CASE PWR
FBB
R2 0 1%, 0402 20
BSTC FREQ 4x LXC
2
C22 1000pF, 6V 0402 AGND L3 C6 1.0H, H6.8A, 14.2m 0.1F, 5.8mm x 8.2mm x 3.0mm 6V 0402 (NEC/TOKIN: MPLC0525L1R0) R7 3.01k 1%, 0402 C23 2200pF, 6V 0402 AGND C17 1F, 6V 0402 C18 10F, 6V 0805 PWR C19 10F, 6V 0805 PWR PWR
AGND
3-6
C3 AGND 0.1F, 6V 0402 21 REF AGND C23 0.1F, 6V 0402 11
FBC
48
R8 10.0k 1%, 0402
PWR
C16 330F 18m, 2.5V, B2 CASE
1.05V, 4A
AGND
VTTR
IND 9
1.8V SMPS OUTPUT
R13 15k 1%, 0402
AGND
2x OUTD 12 R14 15.0k 1%, 0402 REFIND PGND
7, 8 PWR
FBD 10 AGND 22
C20 10F, 6V 0805
0.9A, 1A
AGND
PWR
AGND
Figure 1. Standard Application Circuit
______________________________________________________________________________________
17
Quad-Output Controller for Low-Power Architecture MAX17017
UP/DN UP/DN = VCC [BUCK], LOW BUCK MODE BYP LDO5 INLDO TSDN TSDN VCC VDD
MAX17017
INA
SHDN BYP_OK
VCC BSTA FB SW EN DRV VCC_OK REF_OK ONLDO CSPA CSNA EN VCC LDO5 VCCOK *ONA (SHDN) EN VCC VCC EN REF REFOK OSC EN SYNC OND VCC CSB EN SSDA+ FBA BSTB INBC UVLO REG A ANALOG ONA
DHA LXA VDD DLA
BIAS
REF
IND VCC
OUTD
REG D ANALOG ONB INBC_OK
REG B ANALOG EN FBB
LXB VDD
PGND FBD
REG D PWR BSTC + ON_VTTR REFIND ONA ONB ONC OND VCC CSC REG C ANALOG ONC INBC_OK EN FBC *BUCK REF ENABLED BY SHDN; BOOST REF ENABLED BY ONA. +SSDA ONLY USED IN STEP-UP MODE. SSDA = HIGH IN STEP-DOWN MODE. LXC VDD INBC_OK UVLO INBC INBC
BYP VTTR
REFIND POKX PGOOD AND FAULT PROTECTION FAULTX ONX
Figure 2. MAX17017 Block Diagram
18 ______________________________________________________________________________________
Quad-Output Controller for Low-Power Architecture
LDO5 Bootstrap Switchover When the bypass input (BYP) exceeds the LDO5 bootstrap switchover threshold for more than 500s, an internal 1.5 (typ) p-channel MOSFET shorts BYP to LDO5, while simultaneously disabling the LDO5 linear regulator. This bootstraps the controller, allowing power for the internal circuitry and external LDO5 loading to be generated by the output of a 5V switching regulator. Bootstrapping reduces power dissipation due to driver and quiescent losses by providing power from a switch-mode source, rather than from a much-less-efficient linear regulator. The current capability increases from 50mA to 100mA when the LDO5 output is switched over to BYP. When BYP drops below the bootstrap threshold, the controller immediately disables the bootstrap switch and reenables the 5V LDO.
SMPS Detailed Description
Fixed-Frequency, Current-Mode PWM Controller
The heart of each current-mode PWM controller is a multi-input, open-loop comparator that sums multiple signals: the output-voltage error signal with respect to the reference voltage, the current-sense signal, and the slope compensation ramp (Figure 3). The MAX17017 uses a direct-summing configuration, approaching ideal cycle-to-cycle control over the output voltage without a traditional error amplifier and the phase shift associated with it.
MAX17017
Reference (REF)
The 1.25V reference is accurate to 1% over temperature and load, making REF useful as a precision system reference. Bypass REF to GND with a 0.1F or greater ceramic capacitor. The reference sources up to 50A and sinks 5A to support external loads. If highly accurate specifications are required for the main SMPS output voltages, the reference should not be loaded. Loading the reference slightly reduces the output voltage accuracy because of the reference load-regulation error.
Frequency Selection (FREQ) The FREQ input selects the PWM mode switching frequency. Table 1 shows the switching frequency based on the FREQ connection. High-frequency (FREQ = GND) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This might be acceptable in ultraportable devices where the load currents are lower. Low-frequency (FREQ = 5V) operation offers the best overall efficiency at the expense of component size and board space.
VL
R1
R2 TO PWM LOGIC UNCOMPENSATED HIGH-SPEED LEVEL TRANSLATOR AND BUFFER OUTPUT DRIVER
FB_
I1
I2
I3
VBIAS
REF CSH_ CSL_ SLOPE COMPENSATION
Figure 3. PWM Comparator Functional Diagram
______________________________________________________________________________________
19
Quad-Output Controller for Low-Power Architecture MAX17017
Table 1. FREQ Table
REG A AND REG C PIN SELECT SWITCHING FREQUENCY fSWA AND fSWC LDO5 REF GND SYNC 250kHz 375kHz 500kHz 0.5 x fSYNC SOFT-START TIME REG A: 1200/fSWA REG C: 900/fSWC REG A: 4.8ms REG C: 3.6ms REG A: 3.2ms REG C: 2.4ms REG A: 2.4ms REG C: 1.8ms -- STARTUP BLANKING TIME 1500/fSWA 6ms 4ms 3ms -- SWITCHING FREQUENCY fSWB 500kHz 750kHz 1MHz fSYNC REG B SOFT-START TIME 1800/fSWB 3.6ms 2.4ms 1.8ms -- STARTUP BLANKING TIME 3000/fSWB 6ms 4ms 3ms --
Light-Load Operation Control
The MAX17017 uses a light-load pulse-skipping operating mode for all switching regulators. The switching regulators turn off the low-side MOSFETs when the current sense detects zero inductor current. This keeps the inductor from discharging the output capacitors and forces the switching regulator to skip pulses under light-load conditions to avoid overcharging the output.
Idle-Mode Current-Sense Threshold When pulse-skipping mode is enabled, the on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle-mode currentsense threshold. Under light-load conditions, the ontime duration depends solely on the idle-mode current-sense threshold. This forces the controller to source a minimum amount of power with each cycle. To avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feedback threshold. Since the zero-crossing comparator prevents the switching regulator from sinking current, the MAX17017 switching regulators must skip pulses. Therefore, the controller regulates the valley of the output ripple under light-load conditions. Automatic Pulse-Skipping Crossover In skip mode, an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing
comparator senses the inductor current during the offtime. For regulator A, once VCSPA - VCSNA drops below the 1mV zero-crossing current-sense threshold, the comparator turns off the low-side MOSFET (DLA pulled low). For regulators B and C, once the current through the lowside MOSFET drops below 100mA, the zero-crossing comparator turns off the low-side MOSFET. The minimum idle-mode current requirement causes the threshold between pulse-skipping PFM operation and constant PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The load-current level at which PFM/PWM crossover occurs (ILOAD(SKIP)) is equivalent to half the idle-mode current threshold (see the Electrical Characteristics table for the idle-mode thresholds of each regulator). The switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels).
20
______________________________________________________________________________________
Quad-Output Controller for Low-Power Architecture
SMPS POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when VCC rises above approximately 1.9V, resetting the undervoltage, overvoltage, and thermal-shutdown fault latches. The POR circuit also ensures that the low-side drivers are pulled low until the SMPS controllers are activated. The VCC input undervoltage lockout (UVLO) circuitry prevents the switching regulators from operating if the 5V bias supply (VCC and VDD) is below its 4.2V UVLO threshold. becomes high impedance as long as the output remains within 8% (min) of the nominal regulation voltage set by FB_. POK_ goes low once its corresponding output drops 12% (typ) below its nominal regulation point, an output overvoltage fault occurs, or the output is shut down. For a logic-level POK_ output voltage, connect an external pullup resistor between POK_ and LDO5. A 100k pullup resistor works well in most applications.
MAX17017
SMPS Fault Protection
Output Overvoltage Protection (OVP) If the output voltage rises above 112% (typ) of its nominal regulation voltage, the controller sets the fault latch, pulls POK_ low, shuts down the respective regulator, and immediately pulls the output to ground through its low-side MOSFET. Turning on the low-side MOSFET with 100% duty cycle rapidly discharges the output capacitors and clamps the output to ground. However, this commonly undamped response causes negative output voltages due to the energy stored in the output LC at the instant the OVP occurs. If the load cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse-polarity clamp. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the input source also fails (short-circuit fault). Cycle VCC below 1V or toggle the respective enable input to clear the fault latch and restart the regulator. Output Undervoltage Protection (UVP) Each MAX17017 includes an output undervoltage (UVP)-protection circuit that begins to monitor the output once the startup blanking period has ended. If any output voltage drops below 88% (typ) of its nominal regulation voltage, the UVP protection immediately sets the fault latch, pulls the respective POK output low, forces the high-side and low-side MOSFETs into highimpedance states (DH = DL = low), and shuts down the respective regulator. Cycle VCC below 1V or toggle the respective enable input to clear the fault latch and restart the regulator. Thermal-Fault Protection The MAX17017 features a thermal-fault-protection circuit. When the junction temperature rises above +160C, a thermal sensor activates the fault latch, pulls all POK outputs low, and shuts down all regulators. Toggle SHDN to clear the fault latch and restart the controllers after the junction temperature cools by 15C.
Regulator A Startup Once the 5V bias supply rises above this input UVLO threshold and ONA is pulled high, the main step-down controller (regulator A) is enabled and begins switching. The internal voltage soft-start gradually increments the feedback voltage by 10mV every 12 switching cycles. Therefore, OUTA reaches its nominal regulation voltage 1200/fSWA after regulator A is enabled (see the REG A Startup Waveform (Heavy Load) graph in the Typical Operating Characteristics). Regulator B and C Startup The internal step-down controllers start switching and the output voltages ramp up using soft-start. If the bias supply voltage drops below the UVLO threshold, the controller stops switching and disables the drivers (LX_ becomes high impedance) until the bias supply voltage recovers. Once the 5V bias supply and INBC rise above their respective input UVLO thresholds (SHDN must be pulled high to enable the reference), and ONB or ONC is pulled high, the respective internal step-down controller (regulator B or C) becomes enabled and begins switching. The internal voltage soft-start gradually increments the feedback voltage by 10mV every 24 switching cycles for regulator B or every 12 switching cycles for regulator C. Therefore, OUTB reaches its nominal regulation voltage 1800/fSWB after regulator B is enabled, and OUTC reaches its nominal regulation voltage 900/fSWC after regulator C is enabled (see the REG B Startup Waveform (Heavy Load) and REG C Startup Waveform (Heavy Load) graphs in the Typical Operating Characteristics).
SMPS Power-Good Outputs (POK)
POKA, POKB, and POKC are the open-drain outputs of window comparators that continuously monitor each output for undervoltage and overvoltage conditions. POK_ is actively held low in shutdown (SHDN = GND), standby (ONA = ONB = ONC = GND), and soft-start. Once the soft-start sequence terminates, POK_
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Quad-Output Controller for Low-Power Architecture MAX17017
VTT LDO Detailed Description
VTT LDO Power-Good Output (POKD)
POKD is the open-drain output of a window comparator that continuously monitors the VTT LDO output for undervoltage and overvoltage conditions. POKD is actively held low when the VTT LDO is disabled (OND = GND) and soft-start. Once the startup blanking time expires, POKD becomes high impedance as long as the output remains within 6% (min) of the nominal regulation voltage set by REFIND. POKD goes low once its corresponding output drops or rises 12% (typ) beyond its nominal regulation point or the output is shut down. For a logic-level POKD output voltage, connect an external pullup resistor between POKD and LDO5. A 100k pullup resistor works well in most applications. due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum load current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. * Switching frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. * Inductor operating point. This choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency, higher output ripple, and lower maximum load current, and due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (light loads), the inductor value also determines the loadcurrent value at which PFM/PWM switchover occurs.
VTT LDO Fault Protection
LDO Output Overvoltage Protection (OVP) If the output voltage rises above 112% (typ) of its nominal regulation voltage, the controller sets the fault latch, pulls POKD low, shuts down the source/sink linear regulator, and immediately pulls the output to ground through its low-side MOSFET. Turning on the low-side MOSFET with 100% duty cycle rapidly discharges the output capacitors and clamps the output to ground. Cycle VCC below 1V or toggle OND to clear the fault latch and restart the linear regulator. LDO Output Undervoltage Protection (UVP) Each MAX17017 includes an output undervoltage protection (UVP) circuit that begins to monitor the output once the startup blanking period has ended. If the source/sink LDO output voltage drops below 88% (typ) of its nominal REFIND regulation voltage for 5ms, the UVP protection sets the fault latch, pulls the POKD output low, forces the output into a high-impedance state, and shuts down the linear regulator. Cycle VCC below 1V or toggle OND to clear the fault latch and restart the regulator.
Step-Down Inductor Selection
The switching frequency and inductor operating point determine the inductor value as follows: L= VOUT ( VIN - VOUT ) VINfSWILOAD(MAX)LIR
SMPS Design Procedure (Step Down Regulators)
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input voltage range. The maximum value (VIN(MAX)) must accommodate the worst-case, high ACadapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops
22
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Most inductor manufacturers provide inductors in standard values, such as 1.0H, 1.5H, 2.2H, 3.3H, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For
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Quad-Output Controller for Low-Power Architecture
the selected inductance value, the actual peak-to-peak inductor ripple current (IINDUCTOR) is defined by: V (V - V ) IINDUCTOR = OUT IN OUT VINfSWL Ferrite cores are often the best choice, although soft saturating molded core inductors are inexpensive and can work well at 500kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): I IPEAK = ILOAD(MAX) + INDUCTOR 2
Electrical Characteristics table, and fSW is the switching frequency selected by the FREQ setting (see Table 1).
When using only polymer capacitors on the output, the additional ESR of the output (RESR) must be taken into consideration. For duty cycles less than 40% using polymer capacitors:
VFB VOUT 1 COUT > 1 + V 2fSW (RDROOP + RESR x VFB / VOUT) VOUT IN
MAX17017
For duty cycles above 40% using polymer capacitors, the ESR and COUT must meet the conditions listed below:
V RESR < RDROOP OUT VFB
SMPS Output Capacitor Selection
The output filter capacitor selection requires careful evaluation of several different design requirements-- stability, transient response, and output ripple voltage--that place limits on the output capacitance and ESR. Based on these requirements, the typical application requires a low-ESR polymer capacitor (lower cost but higher output-ripple voltage) or bulk ceramic capacitors (higher cost but low output-ripple voltage).
VFB VOUT 1 COUT > V 1 + V 2fSW RDROOP OUT IN When the ESR condition described above is not satisfied, or when using a mix of ceramic and polymer capacitors on the output, an additional feedback polecapacitor from FB to analog ground (CFB) is necessary to cancel the output capacitor ESR zero:
C R CFB > OUT ESR RFB
SMPS Loop Compensation Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the loop gain. This reduces the output capacitance requirement (stability and transient) and output power dissipation requirements as well. The load-line is generated by sensing the inductor current through the high-side MOSFET on-resistance, and is internally preset to -5mV/A (typ) for regulator B and -7mV/A (typ) for regulator C. The loadline ensures that the output voltage remains within the regulation window over the full-load conditions.
The load line of the internal SMPS regulators also provides the AC ripple voltage required for stability. To maintain stability, the output capacitive ripple must be kept smaller than the internal AC ripple voltage, and crossover must occur before the Nyquist pole-- (2fSW)/(1+D) occurs. Based on these loop requirements, a minimum output capacitance can be determined from the following: When using only ceramic capacitors on the output, the required output capacitance is: VFB VOUT 1 COUT > V 1 + V 2fSW RDROOP OUT IN where RDROOP is 2RSENSE for regulator A, 5mV/A for regulator B, or 7mV/A for regulator C as defined in the
where RFB is the parallel impedance of the FB resistive divider.
SMPS Output Ripple Voltage With polymer capacitors, the effective series resistance (ESR) dominates and determines the output ripple voltage. The step-down regulator's output ripple voltage (V RIPPLE ) equals the total inductor ripple current (IINDUCTOR) multiplied by the output capacitor's ESR. Therefore, the maximum ESR to meet the output ripple voltage requirement is:
VINfSWL RESR VRIPPLE (VIN - VOUT )VOUT where fSW is the switching frequency. The actual capacitance value required relates to the physical case size needed to achieve the ESR requirement, as well as to the capacitor chemistry. Thus, polymer capacitor selection is usually limited by ESR and voltage rating rather than by capacitance value. Alternatively, combining ceramics (for the low ESR) and polymers (for the bulk capacitance) helps balance the output capacitance vs. output ripple voltage requirements.
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Quad-Output Controller for Low-Power Architecture
Internal SMPS Transient Response The load-transient response depends on the overall output impedance over frequency, and the overall amplitude and slew rate of the load step. In applications with large, fast load transients (load step > 80% of full load and slew rate > 10A/s), the output capacitor's high-frequency response--ESL and ESR--needs to be considered. To prevent the output voltage from spiking too low under a load-transient event, the ESR is limited by the following equation (ignoring the sag due to finite capacitance):
VSTEP RESR - RPCB ILOAD(MAX) where VSTEP is the allowed voltage drop, ILOAD(MAX) is the maximum load step, and RPCB is the parasitic board resistance between the load and output capacitor. The capacitance value dominates the midfrequency output impedance and dominates the load-transient response as long as the load transient's slew rate is less than two switching cycles. Under these conditions, the sag and soar voltages depend on the output capacitance, inductance value, and delays in the transient response. Low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sudden load step, especially with low differential voltages across the inductor. The sag voltage (VSAG) that occurs after applying the load current can be estimated by the following:
VSAG = L ILOAD(MAX) ILOAD(MAX) (T - T) + COUT 2COUT (VIN x DMAX - VOUT )
MAX17017
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The IRMS requirements of an individual regulator can be determined by the following equation: I IRMS = LOAD VOUT (VIN - VOUT ) VIN The worst-case RMS current requirement occurs when operating with VIN = 2VOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD. However, the MAX17017 uses an interleaved fixed-frequency architecture, which helps reduce the overall input RMS current on the INBC input supply. For the MAX17017 system (INA) supply, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. For the MAX17017 INBC input supply, ceramic capacitors are preferred on input due to their low parasitic inductance, which helps reduce the high-frequency ringing on the INBC supply when the internal MOSFETs are turned off. Choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit longevity.
BST Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate charging requirements of the high-side MOSFETs. For these low-power applications, 0.1F ceramic capacitors work well.
(
)2
Regulator A Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D2PAK),
where D MAX is the maximum duty factor (see the Electrical Characteristics table), T is the switching period (1/fOSC), and T equals VOUT/VIN x T when in PWM mode, or L x IIDLE/(VIN - VOUT) when in pulse-skipping mode. The amount of overshoot voltage (VSOAR) that occurs after load removal (due to stored inductor energy) can be calculated as: VSOAR
(ILOAD(MAX) )2L
2COUT VOUT
When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem.
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Quad-Output Controller for Low-Power Architecture
and is reasonably priced. Ensure that the MAX17017 DLA gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems might occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology. For the low-side MOSFET (NL) the worst-case power dissipation always occurs at maximum battery voltage: V 2 PD(NL Re sistive) = 1 - OUT (ILOAD ) RDS(ON) VIN(MAX) The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX), but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, "overdesign" the circuit to tolerate: I ILOAD = ILIMIT - INDUCTOR 2 where ILIMIT is the peak current allowed by the currentlimit circuit, including threshold tolerance and senseresistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage drop low enough to prevent the low-side MOSFET's body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current. This diode is optional and can be removed if efficiency is not critical.
MAX17017
Power-MOSFET Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage:
V 2 PD(NH Re sistive) = OUT (ILOAD ) RDS(ON) VIN Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board (PCB) layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD (NH Switching) = ILOADQG(SW) COSS VIN(MAX) + VIN(MAX)fSW IGATE 2 where COSS is the output capacitance of NH, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance.
Regulator A Step-Up Converter Configuration
Regulator A can be configured as a step-up converter (Figure 4). When UP/DN is pulled low, regulator A operates as a step-up converter (for 1 Li+ cell applications). It typically generates a 5V output voltage from a 3V to 5V battery input voltage. The step-up converter uses a current-mode architecture; the difference between the feedback voltage and a 1V reference signal generates an error signal that programs the peak inductor current to regulate the output voltage. The step-up converter is internally compensated, reducing external component requirements. When regulator A is configured as a step-up converter, SHDN should be connected to GND. ONA is the master enable switch. ONA rising enables REF and the bias block. Connect LDO5 and INLDO together with OUTA and connect BYP to either OUTA or INA. At light loads, efficiency is enhanced by an idle mode in which switching occurs only as needed to service the load. This idle-mode threshold is determined by comparing the current-sense signal to an internal reference. In idle mode, the synchronous rectifier shuts off once the current-sense voltage (CSPA - CSNA) drops below 1mV, preventing negative inductor current.
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Quad-Output Controller for Low-Power Architecture MAX17017
13 38 19 15 AGND 5V SMPS OUTPUT 44 R1 C1 10 PWR 4.7F, 6V 0603 5%, 0402 C2 1.0F, 6V 0402 VDD LXA DLA 17 VCC 28 30 NL1 14 SHDN SYNC UP/DN LDO5 INLDO CSPA 24 PWR INA 18 C7 1F, 16V 0603 R15 0.01 1%, 0612 C8 4.7F, 16V 1206 PWR C9 150F, 35m 6V B2 CASE 3V TO 4.5V
PWR
CSNA 23
L1 3.3H, 6.8A, 14.2m 5.8mm x 6.2mm x 3.0mm (NEC/TOKIN: MPLC0525L1R0) R3 40k 1%, 0402 R4 10k 1%, 0402 C11 220F, 35m 6V B2 C4SE
5V, 1A
AGND ON OFF ON OFF ON OFF ON OFF 5V SMPS OUTPUT
39 37 47 46
29 BSTA 27 DHA 25 FBA BYP 16
PWR
C10 NH1 0.1F, 6V, 0402
PWR
ONA ONB ONC OND
C11 680pF, 6V 0402 C12 1F, 16V 0402 PWR PWR C5 L2 0.1F, 6V 1.0H, 6.8A, 14.2m 0402 6.7mm x 7.7mm x 3.0mm (NEC/TOKIN: MPLC0730L3R3) R5 21.0k 1%, 0402 C15 1000pF, 6V 0402 R6 15.0k 1%, 0402 C13 10F, 6V 0805
AGND
AGND
4x INBC 40-43
R9 100k 5%, 0402
R10 100k 5%, 0402
R11 100k 5%, 0402
R12 100k 5%, 0402
MAX17017
BSTB 26 35 1 45 3x LXB
34
POKA POKB POKC POKD
31, 32, 33 36
C14 220F 18m, 2.5V, B2 CASE PWR
1.8V, 2.5A
FBB
R2 0 1%, 0402 20
FREQ
BSTC 4x LXC
2
AGND L3 C6 1.0H, 6.8A, 14.2m 0.1F, 6V 5.8mm x 8.2mm x 3.0mm 0402 (NEC/TOKIN: MPLC0525L1R0) R7 6.04k 1%, 0402 C18 2200pF, 6V 0402 AGND C19 1F, 6V 0402 C20 10F, 6V 0805 PWR C21 10F, 6V 0805 PWR PWR
AGND
AGND
C3 10nF , 6V 0402 21 REF
3-6
FBC
48
R8 15.0k 1%, 0402
C16 C17 220F 10F, 6V 18m, 0805 2.5V, B2 PWR CASE PWR
1.05V, 4A
AGND 11 C4 0.1F, 6V 0402 VTTR IND 9
AGND
1.8V SMPS OUTPUT
AGND R13 15k 1%, 0402 R14 15.0k 1%, 0402
2x OUTD 12 REFIND PGND
7, 8 PWR
FBD 10 22 AGND
C22 10F, 6V 0805
0.9A, 1A
AGND
PWR
AGND
Figure 4. Standard Application Circuit 2, Regulator A Configured as Step-Up Converter
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Step-Up Configuration Inductor Selection
The switching frequency and inductor operating point determine the inductor value as follows:
2 V VOUT - VVIN L = IN VOUT ILOAD(MAX)fSWLIR
MAX17017
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) V I -V VRIPPLE(C) OUT OUT IN COUT VOUT fSW and: VRIPPLE(ESR) IPEAKRESR where IPEAK is the peak inductor current. For polymer capacitors, the output voltage ripple is typically dominated by resistive ripple voltage. The voltage rating and temperature characteristics of the output capacitor must also be considered. The output ripple voltage due to the frequency-dependent term can be compensated by using capacitors of very low ESR to maintain low ripple voltage. Note that all ceramic capacitors typically have large temperature coefficient and bias voltage coefficients. The actual capacitor value in circuit is typically significantly less than the stated value.
Choose an available inductor value from an appropriate inductor family. Calculate the maximum DC input current at the minimum input voltage VIN(MIN) using conservation of energy: IVIN(DC,MAX) = ILOAD(MAX) VOUT VIN(MIN)
Calculate the ripple current at that operating point and the peak current required for the inductor: -V ) V (V IINDUCTOR = IN OUT IN VOUT fSWL I IPEAK = ILOAD(MAX) + INDUCTOR 2 The inductor's saturation current rating and the MAX17017's LXA current limit should exceed IPEAK and the inductor's DC current rating should exceed IVIN(DC,MAX). For good efficiency, choose an inductor with less than 0.1 series resistance.
Step-Up Configuration Loop Compensation The boost converter small-signal model contains a right half-plane (RHP) zero. The presence of an RHP zero tends to destabilize wide-bandwidth feedback loop because during a transient, the output initially changes in the wrong direction. Also when an RHP zero is present, it is difficult to obtain an adequate phase margin. RHP is determined by inductance L, duty cycle Dup, and load R. The RHP is:
fRHP = (1 - DUP )2 R 2L
Step-Up Configuration Output Capacitor Selection
For boost converter, during continuous operation, the output capacitor has a trapezoidal current profile. The large RMS ripple current in the output capacitor must be rated to handle the current. The RMS current is greatest at ILOAD(MAX) and minimum input working voltage. Therefore, the output capacitor should be chosen with a rating at least ICOUT(RMS).The RMS current into the capacitor is then given by: ICOUT(RMS) ILOAD VOUT - VIN VIN
To maintain stability, crossover must occur before the RHP. To make sure the phase margin is big enough to stabilize the circuit, the converter crossover must be kept 4 ~ 10 times slower than the RHP zero. A minimum output capacitance is determined from the following: A VREF COUT > 4 STEP -UP L RCS VOUT (1 - DUP )R where ASTEP-UP is equal to 1.25, which is the error amplifier gain divided by the current-sense gain; RCS is the current-sensing resistor. Additionally, an additional feedback pole--capacitor from FB to analog ground (CFB)--might be necessary to cancel the unwanted ESR zero of the output capacitor.
The total output voltage ripple has two components: the capacitive ripple caused by the charging and discharging of the output capacitance, and the resistive ripple due to the capacitor's equivalent series resistance (ESR):
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Quad-Output Controller for Low-Power Architecture MAX17017
In general, if the ESR zero occurs before the Nyquist pole, then canceling the ESR zero is recommended: If: G V ESR > CS OUT (1 - D)AVREF then: C ESR CFB > OUT RFB where RFB is the parallel impedance of the FB resistive divider. feature makes the MAX17017 ideal for memory applications in which the termination supply must track the supply voltage.
VTT LDO Output Capacitor Selection (COUTD)
A minimum value of 20F or greater ceramic is needed to stabilize the VTT output (OUTD). This value of capacitance limits the switching regulator's unity-gain bandwidth frequency to approximately 1.2MHz (typ) to allow adequate phase margin for stability. To keep the capacitor acting as a capacitor within the switching regulator's bandwidth, it is important that ceramic capacitors with low ESR and ESL be used. Since the gain bandwidth is also determined by the transconductance of the output MOSFETs, which increases with load current, the output capacitor might need to be greater than 20F if the load current exceeds 1.5A, but can be smaller than 20F if the maximum load current is less than 1.5A. As a guideline, choose the minimum capacitance and maximum ESR for the output capacitor using the following: COUT _ MIN = 20F x and: RESR _ MAX = 5m x ILOAD 1.5A ILOAD 1.5A
Step-Up Configuration Input Capacitor Selection
The current in the boost converter input capacitor does not contain large square-wave currents as found in the output capacitor. Therefore, the input capacitor selection is less critical due to the output capacitor. However, a low ESR is recommended. The RMS input ripple current for a boost converter is: ICIN(RMS) 0.3VIN(MIN)DMAX LfSW
VTT LDO Design Procedure
IND Input Capacitor Selection (CIND) The value of the IND bypass capacitor is chosen to limit the amount of ripple and noise at IND, and the amount of voltage sag during a load transient. Typically, IND connects to the output of a step-down switching regulator, which already has a large bulk output capacitor. Nevertheless, a ceramic capacitor equivalent to half the VTT output capacitance should be added and placed as close as possible to IND. The necessary capacitance value must be increased with larger load current, or if the trace from IND to the power source is long and results in relatively high input impedance. VTT LDO Output Voltage (FBD)
The VTT output stage is powered from the IND input. The VTT output voltage is set by the REFIND input. REFIND sets the VTT LDO feedback regulation voltage (VFBD = VREFIND) and the VTTR output voltage. The VTT LDO (FBD voltage) and VTTR track the REFIND voltage over a 0.5V to 1.5V range. This reference input
RESR value is measured at the unity-gain-bandwidth frequency given by approximately: fGBW = I 36 x LOAD COUT 1.5A
Once these conditions for stability are met, additional capacitors, including those of electrolytic and tantalum types, can be connected in parallel to the ceramic capacitor (if desired) to further suppress noise or voltage ripple at the output.
VTTR Output Capacitor Selection
The VTTR buffer is a scaled-down version of the VTT regulator, with much smaller output transconductance. Therefore, the VTTR compensation requirements also scale. For typical applications requiring load currents up to 3mA, a 0.22F or greater ceramic capacitor is recommended (RESR < 0.3).
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VTT LDO Power Dissipation
Power loss in the MAX17017 VTT LDO is significant and can become a limiting design factor in the overall MAX17017 design: PDVTT = 2A x 0.9V = 1.8W The 1.8W total power dissipation is within the 40-pin TQFN multilayer board power-dissipation specification of 2.9W. The typical DDR termination application does not actually continuously source or sink high currents. The actual VTT current typically remains around 100mA to 200mA under steady-state conditions. VTTR is down in the microampere range, though the Intel specification requires 3mA for DDR1 and 1mA for DDR2. True worst-case power dissipation occurs on an output short-circuit condition with worst-case current limit. MAX17017 does not employ any foldback current limiting, and relies on the internal thermal shutdown for protection. Both the VTT and VTTR output voltages are referenced to the same REFIND input. above the feedback threshold voltage, the controller does not trigger an on-time pulse, effectively skipping a cycle. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (VIN(SKIP)): 1 VIN(SKIP) = VOUT fOSCt ON(MIN) where f OSC is the switching frequency selected by FREQ.
MAX17017
PCB Layout Guidelines
Careful PCB layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow the MAX17017 Evaluation Kit layout and use the following guidelines for good PCB layout: * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PCBs (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. * Minimize current-sensing errors by connecting CSPA and CSNA directly across the current-sense resistor (RSENSE_). * When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. * Route high-speed switching nodes (BST_, LX_, DHA, and DLA) away from sensitive analog areas (REF, REFIND, FB_, CSPA, CSNA).
Applications Information
Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the Electrical Characteristics table). For the best dropout performance, use the slowest switching frequency setting (FREQ = GND). However, keep in mind that the transient performance gets worse as the step-down regulators approach the dropout voltage, so bulk output capacitance must be added (see the voltage sag and soar equations in the Design Procedure section). The absolute point of dropout occurs when the inductor current ramps down during the off-time (IDOWN) as much as it ramps up during the on-time (IUP). This results in a minimum operating voltage defined by the following equation:
1 VIN(MIN) = VOUT + VCHG + h - 1 (VOUT + VDIS ) DMAX where VCHG and VDIS are the parasitic voltage drops in the charge and discharge paths, respectively. A reasonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1.
Maximum Input Voltage The MAX17017 controller includes a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the Electrical Characteristics table). Operation above this maximum input voltage results in pulse skipping to avoid overcharging the output. At the beginning of each cycle, if the output voltage is still
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Quad-Output Controller for Low-Power Architecture MAX17017
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE 48 TQFN PACKAGE CODE T4866-2 DOCUMENT NO. 21-0141
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Quad-Output Controller for Low-Power Architecture
Revision History
REVISION NUMBER 0 1 REVISION DATE 5/08 9/08 Initial release Updated Electrical Characteristics and added Regulator Step-Up Converter Configuration section Status changed from silent to public; added leakage current specification and updated Note 2 in Electrical Characteristics; updated Figures 1, 2, and 4; updated SMPS Loop Compensation section DESCRIPTION PAGES CHANGED -- 4, 5, 8, 9, 23, 25-29 1-6, 8-23, 25, 26, 29, 30
MAX17017
2
6/09
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(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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