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IMPORTANT NOTICE
Dear customer, As from August 2nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document.
Company name - NXP B.V. is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of each page "(c) NXP B.V. 200x. All rights reserved", shall now read: "(c) ST-NXP Wireless 200x - All rights reserved". Web site - http://www.nxp.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices previously obtained by sending an email to salesaddresses@nxp.com , is now found at http://www.stnwireless.com under Contacts.
If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless
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ISP1512A
ULPI Hi-Speed USB transceiver
Rev. 01 -- 31 July 2008 Preliminary data sheet
1. General description
The ISP1512A is a UTMI+ Low Pin Interface (ULPI) Hi-Speed Universal Serial Bus (USB) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. The ISP1512A can transmit and receive USB data at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer front-end attachment to the USB host, peripheral and OTG controller with Single Data Rate (SDR) ULPI link. The ISP1512A can transparently transmit and receive UART signaling. It is ideal for use in portable electronic devices, such as mobile phones, digital still cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs) or any system chip set to interface with the physical layer of the USB through a 12-pin SDR interface. The ISP1512A can interface to devices with digital I/O voltages in the range of 1.65 V to 1.95 V. The ISP1512A is available in WLCSP25 package.
2. Features
I Fully complies with: N USB: Universal Serial Bus Specification Rev. 2.0 N ULPI: UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 I Interfaces to USB host or peripheral cores; optimized for portable devices or system ASICs with built-in ULPI link I Complete Hi-Speed USB physical front-end solution that supports high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) N Integrated 45 10 % high-speed termination resistors, 1.5 k 5 % full-speed device pull-up resistor, and 15 k 5 % host termination resistors N Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive N USB clock and data recovery to receive USB data up to 500 ppm N USB data synchronization from 60 MHz input to 480 MHz output during transmit N Insertion of stuff bits during transmit and discarding of stuff bits during receive N Non-Return-to-Zero Inverted (NRZI) encoding and decoding N Supports bus reset, suspend, resume and high-speed detection handshake (chirp) I Partial USB OTG physical front-end support
NXP Semiconductors
ISP1512A
ULPI HS USB transceiver
I
I
I
I I
I
N Supports Session Request Protocol (SRP) that adheres to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 N Complete control over USB termination resistors N Data line and VBUS pulsing session request methods N Integrated VBUS voltage comparators Flexible system integration and very low current consumption, optimized for portable devices N 3.0 V to 4.5 V power supply input range N Internal voltage regulator supplies 2.7 V or 3.3 V and 1.8 V N Supports interfacing I/O voltage of 1.65 V to 1.95 V; separate I/O voltage supply pins minimize crosstalk N Powers down internal regulators in power-down mode when VCC(I/O) is not present or when the chip is deasserted N Typical operating current of 10 mA to 48 mA, depending on the USB speed and bus utilization N Typical suspend current of 50 A N Typical power-down state current 0.5 A, max 10 A N 3-state ULPI interface by the CHIP_SEL pin, allowing bus reuse by other applications Highly optimized ULPI compliant N 60 MHz, 12-pin interface between the core and the transceiver, including an 8-bit SDR data bus N Supports 60 MHz output clock configuration N Integrated Phase-Locked Loop (PLL) supporting input clock frequency of 19.2 MHz N Fully programmable ULPI-compliant register set N 3-pin or 6-pin full-speed or low-speed serial mode N Internal Power-On Reset (POR) circuit UART interface: N Supports transparent UART signaling on the DP and DM pins for UART accessory applications N 2.7 V UART signaling on the DP and DM pins N Entering UART mode by register setting N Exiting UART mode by asserting STP or by toggling the CHIP_SEL pin Full industrial grade operating temperature range from -40 C to +85 C ESD compliance: N JESD22-A114-B 2 kV contact Human Body Model (HBM) N JESD22-A115-A 200 V Machine Model (MM) N JESD22-C101-A 500 V Charge Device Model (CDM) N IEC 61000-4-2 8 kV contact on the DP and DM pins Available in small WLCSP25 Restriction of Hazardous Substances (RoHS) compliant, halogen-free and lead-free package
3. Applications
I Mobile phone I Digital still camera
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ISP1512A
ULPI HS USB transceiver
I I I I I I I I I
MP3 player PDA Digital TV Digital Video Disc (DVD) recorder External storage device Printer Scanner Set-Top Box (STB) Video camera
4. Ordering information
Table 1. Part Type number ISP1512AUK CHIP_SEL polarity Frequency Ordering information Package Name Description Bump pitch Version
active LOW 19.2 MHz
WLCSP25 wafer level chip-size package; 25 bumps; body 2.24 x 2.21 x 0.6 mm
0.4 mm ISP1512xUK
5. Marking
Table 2. Marking codes Marking code[1] 1512A Type number ISP1512AUK
[1]
The package marking is the first line of text on the IC package and can be used for IC identification.
ISP1512A_1
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ISP1512A
ULPI HS USB transceiver
6. Block diagram
CLOCK
8
A3 A1, A5, B1, B2, B3, B4, B5, C5 D5 D4 C4 REGISTER MAP USB DATA DESERIALIZER TERMINATION RESISTORS C1 DM ULPI INTERFACE CONTROLLER USB DATA SERIALIZER HI-SPEED USB ATX D1 DP
ULPI INTERFACE
DATA [7:0] DIR STP NXT
CHIP_SEL
A2
DATA[1:0]
UART BUFFER
AUTO CLOCK FREQUENCY SELECTION
ISP1512A
OTG MODULE VBUS COMPARATORS E2 VBUS
GLOBAL CLOCKS XTAL1 XTAL2 VCC(I/O) E3 E4 A4
PLL SRP CHARGE AND DISCHARGE RESISTORS OSCILLATOR
interface voltage internal power D3 POWER-ON RESET TEST
REG1V8 REG3V3 VCC
E5 D2 E1 VOLTAGE REGULATOR
POR BAND GAP REFERENCE VOLTAGE C2
VREF C3
RREF
GND
004aaa989
Fig 1.
Block diagram
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ISP1512A
ULPI HS USB transceiver
7. Pinning information
7.1 Pinning
ISP1512AUK
1 A B C D E 2 3 4 5
004aab156
Transparent top view
Fig 2.
Pin configuration
7.2 Pin description
Table 3. Symbol[1] DATA0 CHIP_SEL Pin description Pin A1 A2 Type[2] Description[3] I/O I ULPI data pin 0 3-state output; plain input
* *
When this pin is deasserted, ULPI pins will be in 3-state and the ISP1512A is in power-down mode. When this pin is asserted, ULPI pins will operate normally.
The ISP1512A is an active-LOW chip select input. A HIGH level on this pin sets the ISP1512A into power-down mode. If the CHIP_SEL pin is not in use, connect it to GND. plain input CLOCK VCC(I/O) DATA5 DATA1 DATA2 DATA3 DATA4 A3 A4 A5 B1 B2 B3 B4 O P I/O I/O I/O I/O I/O 60 MHz clock output 3-state output input I/O supply voltage; 1.65 V to 1.95 V ULPI data pin 5 3-state output; plain input ULPI data pin 1 3-state output; plain input ULPI data pin 2 3-state output; plain input ULPI data pin 3 3-state output; plain input ULPI data pin 4 3-state output; plain input
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ISP1512A
ULPI HS USB transceiver
Table 3. Symbol[1] DATA6 DM
Pin description ...continued Pin B5 C1 Type[2] Description[3] I/O AI/O ULPI data pin 6 3-state output; plain input connect to the D- pin of the USB connector
* *
RREF GND NXT DATA7 DP C2 C3 C4 C5 D1 AI/O P O I/O AI/O
USB mode: D- input or output UART mode: TXD output
resistor reference; connect through 12 k 1 % resistor to GND ground supply ULPI next signal 3-state output ULPI data pin 7 3-state output; plain input connect to the D+ pin of the USB connector
* *
REG3V3 D2 P
USB mode: D+ input or output UART mode: RXD input
3.3 V regulator output for USB mode or 2.7 V regulator output for UART mode; requiring parallel 0.1 F and 4.7 F capacitors; internally powers ATX and other analog circuits; must not be used to power external circuits connect to ground for normal operation ULPI stop signal plain input ULPI direction signal 3-state output input supply voltage or battery source; 3.0 V to 4.5 V Remark: Below 3.0 V, USB full-speed and low-speed transactions are not guaranteed to work, though some devices may work with the ISP1512A at these voltages.
TEST STP DIR VCC
D3 D4 D5 E1
I I O P
VBUS XTAL1 XTAL2 REG1V8
E2 E3 E4 E5
AI/O AI/O AI/O P
connect to the VBUS pin of the USB connector; if this pin is not in use, leave it open (RI(idle)(VBUS) is present on this pin) crystal oscillator or clock input; if this pin is not in use, connect it to the REG1V8 pin crystal oscillator output; if a crystal is not attached, leave this pin open 1.8 V regulator output; internally powers the digital core; must not be used to power external circuits
[1] [2] [3]
Symbol names ending with underscore N (for example, NAME_N) indicate active-LOW signals. I = input; O = output; I/O = digital input/output; AI/O = analog input/output; P = power or ground pin. A detailed description of these pins can be found in Section 8.10.
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ISP1512A
ULPI HS USB transceiver
8. Functional description
8.1 ULPI interface controller
The ISP1512A provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. This interface must be connected to a USB link. The ULPI interface controller provides the following functions:
* * * * * * * * *
ULPI-compliant interface and register set Allows full control over USB peripheral or host functionality Parses the USB transmit and receive data Prioritizes the USB receive data, USB transmit data, interrupts and register operations Low-power mode 3-pin serial mode 6-pin serial mode Generates RXCMDs (status updates) Maskable interrupts
8.2 USB serializer and deserializer
The USB data serializer prepares data to transmit on the USB bus. To transmit data, the USB link sends a transmit command and data on the ULPI bus. The serializer performs parallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a PID, the serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end of the packet. When the serializer is busy and cannot accept any more data, the ULPI interface controller deasserts NXT. The USB data deserializer decodes data received from the USB bus. When data is received, the deserializer strips the SYNC and EOP patterns, and then performs serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data payload. The ULPI interface controller sends data to the USB link by asserting DIR, and then asserting NXT whenever a byte is ready. The deserializer also detects various receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and byte-alignment errors.
8.3 Hi-Speed USB (USB 2.0) ATX
The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for USB peripheral, host or OTG implementations. The following circuitry is included:
* Differential drivers to transmit data at high-speed, full-speed and low-speed * Differential and single-ended receivers to receive data at high-speed, full-speed and
low-speed
* * * *
ISP1512A_1
Squelch circuit to detect high-speed bus activity High-speed disconnect detector 45 high-speed bus terminations on pins DP and DM 1.5 k pull-up resistor on pin DP
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ISP1512A
ULPI HS USB transceiver
* 15 k bus terminations on pins DP and DM
For details on controlling resistor settings, see Table 12.
8.4 Voltage regulator
The ISP1512A contains a built-in voltage regulator that conditions the VCC supply for use inside the ISP1512A. The voltage regulator:
* * * *
Supports input supply range 3.0 V < VCC < 4.5 V. Can be supplied from a battery with the voltage range mentioned above. Supplies internal digital circuitry with 1.8 V and analog circuitry with 3.3 V or 2.7 V. In USB mode, automatically bypasses the internal 3.3 V regulator when VCC < 3.5 V, the internal analog circuitry directly draws power from the VCC pin. In UART mode, the bypass switch will be disabled. deasserted.
* Will be shut down when VCC(I/O) is not present or when the CHIP_SEL pin is 8.5 Crystal oscillator and PLL
The ISP1512A has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock generation. When a crystal is in use, the built-in crystal oscillator generates a square wave clock for internal use. A square wave clock of the same frequency can also be driven directly into the XTAL1 pin. Using an existing square wave clock can save the cost of a crystal and also reduce the board space. The PLL takes the square wave clock from the crystal oscillator, and multiplies or divides it into various frequencies for internal use. The PLL produces the following frequencies, irrespective of the clock source:
* * * * *
1.5 MHz for low-speed USB data 12 MHz for full-speed USB data 60 MHz clock for the ULPI interface controller 480 MHz for high-speed USB data Other internal frequencies for data conversion and data recovery
8.6 UART buffer
The UART buffer includes circuits to support the transparent UART signaling between the DATA0 or DATA1 pin and the DP or DM pin. When the ISP1512A is put into UART mode, it acts as a voltage level shifter between following pins:
* From DATA0 (VCC(I/O) level) to DM (2.7 V level) for UART TXD signaling path. * From DP (2.7 V level) to DATA1 (VCC(I/O) level) for UART RXD signaling path. 8.7 OTG module
This module contains several sub-blocks that provide some functionality required by the USB OTG specification. Specifically, it provides the following circuits:
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ISP1512A
ULPI HS USB transceiver
* VBUS comparators to determine the VBUS voltage level. * Resistors to temporarily charge and discharge VBUS. This is required for SRP.
8.7.1 VBUS comparators
The ISP1512A provides three comparators to detect the VBUS voltage level. The comparators are explained in the following subsections. 8.7.1.1 VBUS valid comparator This comparator is used by hosts and A-devices to determine whether the voltage on VBUS is at a valid level for operation. The ISP1512A minimum threshold for the VBUS valid comparator is 4.4 V. Any voltage on VBUS below this threshold is considered invalid. During power-up, it is expected that the comparator output will be ignored. 8.7.1.2 Session valid comparator The session valid comparator is a TTL-level input that determines when VBUS is high enough for a session to start. Peripherals, A-devices and B-devices use this comparator to detect when a session is started. The A-device also uses this comparator to determine when a session is completed. The session valid threshold of the ISP1512A is between 0.8 V to 2.0 V. 8.7.1.3 Session end comparator The session end comparator determines when VBUS is below the B-device session end threshold of 0.2 V to 0.8 V. The B-device uses this threshold to determine when a session has ended.
8.7.2 SRP charge and discharge resistors
The ISP1512A provides on-chip resistors for short-term charging and discharging of VBUS. These are used by the B-device to request a session, prompting the A-device to restore the VBUS power. First, the B-device ensures that VBUS is fully discharged from the previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for SESS_END to be logic 1. Then the B-device charges VBUS by setting the CHRG_VBUS register bit to logic 1. The A-device sees that VBUS is charged above the session valid threshold and starts a session by turning on the VBUS power.
8.8 Band gap reference voltage
The band gap circuit provides a stable internal voltage reference to bias the analog circuitry. This band gap requires an accurate external reference resistor. Connect a 12 k 1 % resistor between the RREF pin and GND.
8.9 Power-On Reset (POR)
An internal POR pulse is generated when REG1V8 rises above VPOR(trip). The internal POR pulse will be generated whenever REG1V8 drops below VPOR(trip) for more than tw(REG1V8_L). To give a better view of the functionality, Figure 3 shows a possible curve of REG1V8. The internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip level so that a POR pulse is generated to reset all internal circuits. If REG1V8 dips from t2
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ISP1512A
ULPI HS USB transceiver
to t3 for greater than tw(REG1V8_L), another POR pulse is generated. If the dip from t4 to t5 is less than tw(REG1V8_L), the internal POR pulse will not be generated and will remain LOW.
REG1V8 VPOR(trip)
t0
t1
t2
t3
t4
t5 POR
004aab023
Fig 3.
Internal power-on reset timing
8.10 Detailed description of pins
8.10.1 DATA[7:0]
Bidirectional data bus pins. The USB link must drive DATA[7:0] to LOW when the ULPI bus is idle. When the link has data to transmit to the PHY, it drives a nonzero value. Weak pull-down resistors are incorporated into DATA[7:0] pins as part of the interface protect feature. DATA[7:0] pins can also be 3-stated when pin CHIP_SEL is deasserted. The data bus can be reconfigured to carry various data types. For details, see Section 9.2.
8.10.2 VCC(I/O)
The input power pin that sets the I/O voltage level. A 0.1 F decoupling capacitor is recommended on this pin.
8.10.3 RREF
Resistor reference analog I/O pin. A 12 k 1 % resistor must be connected between the RREF pin and GND. This provides an accurate voltage reference that biases the internal analog circuitry. Less accurate resistors cannot be used and will render the ISP1512A unusable.
8.10.4 DP and DM
When the ISP1512A is in USB mode, the DP pin functions as the USB data plus line, and the DM pin functions as the USB data minus line. When the ISP1512A is in transparent UART mode, the DP pin functions as the UART RXD input pin, and the DM pin functions as the UART TXD output pin. The DP and DM pins must be connected to the D+ and D- pins of the USB receptacle.
8.10.5 VCC
Main input supply voltage for the ISP1512A. The ISP1512A operates correctly when VCC is between 3.0 V and 4.5 V. A 0.1 F decoupling capacitor is recommended.
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ULPI HS USB transceiver
8.10.6 VBUS
This I/O pin acts as an input to VBUS comparators, and also as a power pin for SRP charge and discharge resistors. For details, see Figure 4. The VBUS pin requires a capacitive load. Table 4 provides the recommended capacitor values for various applications.
Table 4. OTG Standard host Standard peripheral Recommended VBUS capacitor value VBUS capacitor (CVBUS) 1 F to 6.5 F, 10 V 120 F 20 %, 10 V 1 F to 10 F, 10 V
Application
REG3V3
CHRG_VBUS
VBUS comparators
RUP(VBUS)
VBUS
RDN(VBUS) RI(idle)(VBUS)
DISCHRG_ VBUS
004aaa871
Fig 4.
Internal circuit of the VBUS pin
8.10.7 REG3V3 and REG1V8
These are output voltage pins from the internal regulator. These supplies are used internally to power digital and analog circuits. For proper operation of the regulator, pins REG3V3 and REG1V8 must each be connected to a 0.1 F capacitor in parallel with a 4.7 F low ESR capacitor.
8.10.8 XTAL1 and XTAL2
XTAL1 is the crystal oscillator input, and XTAL2 is the crystal oscillator output. If the link requires a 60 MHz clock from the ISP1512A, then either a crystal must be attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left unconnected. If a crystal is attached, it requires a capacitor on each terminal of the crystal to GND. The values of the maximum series resistance of the crystal and required external capacitors are given in Table 5.
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ISP1512A
ULPI HS USB transceiver
Table 5. 10 pF 20 pF
[1]
External capacitor values for 19.2 MHz clock frequency Maximum series resistance of the crystal < 180 < 100 External capacitor CXTAL value 18 pF 39 pF
Load capacitance of the crystal[1]
Specified by the crystal manufacturer.
8.10.9 CHIP_SEL
The CHIP_SEL pin has two functions: chip select and power-down control. When CHIP_SEL is deasserted, ULPI pins DATA[7:0], CLOCK, DIR and NXT are 3-stated and ignored. Internal circuits are powered-down. When CHIP_SEL is asserted, the ISP1512A will operate normally.
8.10.10 DIR
ULPI direction output pin. Synchronous to the rising edge of CLOCK. Controls the direction of the data bus. By default, the ISP1512A holds DIR at LOW, causing the data bus to be an input. When DIR is LOW the ISP1512A listens for data from the link. The ISP1512A pulls DIR to HIGH only when it has data to send to the link, which is for one of two reasons:
* To send data (USB receive or register reads) and RXCMD status updates to the link. * To block the link from driving the data bus during power-up, reset and low power mode
(suspend).
8.10.11 STP
ULPI stop input pin. Synchronous to the rising edge of CLOCK. The link must assert STP to signal the end of a USB transmit packet or a register write operation. When DIR is asserted, the link can optionally assert STP for one clock cycle to abort the ISP1512A, causing it to deassert DIR in the next clock cycle.
8.10.12 NXT
ULPI next data output pin. Synchronous to the rising edge of CLOCK. The ISP1512A holds NXT at LOW, by default. When DIR is LOW and the link is sending data to the ISP1512A, NXT will be asserted to notify the link to provide the next data byte. When DIR is HIGH and the ISP1512A is sending data to the link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not used for register read data or the RXCMD status update.
8.10.13 CLOCK
A 60 MHz interface clock to synchronize the ULPI bus. In SDR mode, all ULPI pins are synchronous to the rising edge of CLOCK. The ISP1512A provides two clocking options:
* A crystal is attached between the XTAL1 and XTAL2 pins. * A clock driven into the XTAL1 pin, with the XTAL2 pin left unconnected.
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8.10.14 GND
Global ground signal. To ensure the correct operation of the ISP1512A, GND must be soldered to the cleanest ground available.
9. Modes of operation
9.1 Power modes
When both VCC(I/O) and VCC are not powered, there will be no leakage from the VBUS pin to all the remaining pins, including VCC and VCC(I/O). Applying VBUS within the normal range will not damage the ISP1512A chip. When both VCC and VCC(I/O) are powered and are within the operating voltage range, the ISP1512A will be fully functional as in normal mode. When VCC(I/O) is powered and the VCC voltage is below the operating range of the ISP1512A, the application system must detect the low voltage condition and set the CHIP_SEL pin to deassert (that is, put the ISP1512A in power-down mode). This is to protect the ULPI and USB interfaces from driving wrong levels. Under this condition, the VCC(I/O) voltage will not leak to USB pins (VBUS, DP and DM) and the VCC pin. All the digital pins powered by VCC(I/O) are configured as high-impedance inputs. These pins must be driven to their defined states, or terminated by using pull-up or pull-down resistors to avoid floating input condition. Other pins are not powered.
9.1.1 Normal mode
In normal mode, both VCC and VCC(I/O) are powered. The CHIP_SEL pin is asserted. The ISP1512A is fully functional.
9.1.2 Power-down mode
When VCC(I/O) is not present or when the CHIP_SEL pin is deasserted, the ISP1512A is put into power-down mode. In this mode, internal regulators are powered down to keep the VCC current to a minimum. The voltage on the VCC pin will not leak to the VCC(I/O) and/or VBUS pins. In this mode, the ISP1512A pin states are given in Table 6.
Table 6. Pin name VCC VCC(I/O) CHIP_SEL TEST, CLOCK, STP, NXT, DIR, DATA[7:0] REG3V3, REG1V8, DP, DM, XTAL1, XTAL2, RREF
[1]
Pin states in power-down mode Pin state when VCC(I/O) is not present 3.0 V to 4.5 V not not not powered[1] powered[1] powered[1] not powered Pin state when CHIP_SEL is deasserted 3.0 V to 4.5 V 1.65 V to 1.95 V HIGH high-Z (inputs are ignored) not powered[1]
These pins must not be externally driven to HIGH. Otherwise, the ISP1512A behavior is undefined and leakage current will occur.
When VCC(I/O) is not present, all pins are not powered.
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ULPI HS USB transceiver
When the ISP1512A is put into power-down mode by disabling the CHIP_SEL pin, all the digital pins that are powered by VCC(I/O) are configured as high-impedance inputs. These pins must be driven to their defined states or terminated by using pull-up or pull-down resistors to avoid floating input condition. Other pins are not powered. In this mode, minimum current will be drawn by VCC(I/O) to detect the CHIP_SEL pin status.
9.2 ULPI modes
The ISP1512A ULPI interface can be programmed to operate in three modes. In each mode, the signals on the data bus are reconfigured as described in the following subsections. Setting more than one mode will lead to undefined behavior.
9.2.1 Synchronous mode
This is default mode. On power-up, and when CLOCK is stable, the ISP1512A will enter synchronous mode. In synchronous mode, the link must synchronize all ULPI signals to CLOCK, meeting the set-up and hold times as defined in Section 14. This mode is used by the link to perform the following tasks:
* * * *
Table 7. Signal name CLOCK
High-speed detection handshake (chirp) Transmit and receive USB packets Read and write to registers Receive USB status updates (RXCMDs) from the ISP1512A
ULPI signal description Direction on Signal description the ISP1512A[1] O 60 MHz interface clock: If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1512A will drive a 60 MHz output clock. During low-power and serial modes, the clock can be turned off to save power. 4-bit or 8-bit data bus: In synchronous mode, the link drives DATA[7:0] to LOW by default. The link initiates transfers by sending a nonzero data pattern called a TXCMD (transmit command). In synchronous mode, the direction of DATA[7:0] is controlled by DIR. Contents of DATA[7:0] lines must be ignored for exactly one clock cycle whenever DIR changes value. This is called a turnaround cycle. Data lines have fixed directions and different meanings in low-power and 3-pin serial modes.
DATA[7:0]
I/O
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ISP1512A
ULPI HS USB transceiver
Table 7. Signal name DIR
ULPI signal description ...continued Direction on Signal description the ISP1512A[1] O Direction: Controls the direction of data bus DATA[7:0]. In synchronous mode, the ISP1512A drives DIR to LOW by default, making the data bus an input so the ISP1512A can listen for TXCMD from the link. The ISP1512A drives DIR to HIGH only when it has data for the link. When DIR and NXT are HIGH, the byte on the data bus contains decoded USB data. When DIR is HIGH and NXT is LOW, the byte contains status information called an RXCMD (receive command). The only exception to this rule is when the PHY returns register read data, where NXT is also LOW, replacing the usual RXCMD byte. Every change in DIR causes a turnaround cycle on the data bus, during which DATA[7:0] are not valid and must be ignored by the link. DIR is always asserted during low-power and serial modes.
STP
I
Stop: In synchronous mode, the link drives STP to HIGH for one cycle after the last byte of data is sent to the ISP1512A. The link can optionally assert STP to force DIR to be deasserted. In low-power and serial modes, the link holds STP at HIGH to wake up the ISP1512A, causing the ULPI bus to return to synchronous mode.
NXT
O
Next: In synchronous mode, the ISP1512A drives NXT to HIGH to throttle data. If DIR is LOW, the ISP1512A asserts NXT to notify the link to place the next data byte on DATA[7:0] in the following clock cycle. If DIR is HIGH, the ISP1512A asserts NXT to notify the link that a valid USB data byte is on DATA[7:0] in the current cycle. The ISP1512A always drives an RXCMD when DIR is HIGH and NXT is LOW, unless register read data is to be returned to the link in the current cycle. NXT is not used in low-power and serial modes.
[1]
I = input; O = output; I/O = digital input/output.
9.2.2 Low-power mode
When the USB bus is idle, the link can place the ISP1512A into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that shown in Table 8. To enter low-power mode, the link sets the SUSPENDM bit in the FUNC_CTRL register to logic 0. To exit low-power mode, the link asserts the STP signal. After exiting low-power mode, the ISP1512A will send an RXCMD to the link if a change was detected in any interrupt source, and the change still exists. An RXCMD may not be sent if the interrupt condition is removed before exiting. The ISP1512A will draw only suspend current from the VCC supply; see Table 41. During low-power mode, the clock on XTAL1 may be stopped. The clock must be started again before asserting STP to exit low-power mode. For more information on low-power mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
Table 8. Signal LINESTATE0 LINESTATE1 Signal mapping during low-power mode Maps to DATA0 DATA1 Direction[1] Description O O combinatorial LINESTATE0 directly driven by the analog receiver combinatorial LINESTATE1 directly driven by the analog receiver
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ULPI HS USB transceiver
Table 8. Signal Reserved INT Reserved
[1]
Signal mapping during low-power mode ...continued Maps to DATA2 DATA3 DATA[7:0] Direction[1] Description O reserved; the ISP1512A will drive this pin to LOW active-HIGH interrupt indication; will be asserted whenever any unmasked interrupt occurs reserved; the ISP1512A will drive this pin to LOW
O = output.
9.2.3 6-pin full-speed or low-speed serial mode
If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1512A to 6-pin serial mode. In 6-pin serial mode, the data bus definition changes to that shown in Table 9. To enter 6-pin serial mode, the link sets the 6PIN_FSLS_SERIAL bit in the INTF_CTRL register to logic 1. To exit 6-pin serial mode, the link asserts the STP signal. This is provided primarily for links that contain legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path to high-speed functionality. An interrupt pin is also provided to inform the link of USB events. If the link requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM register bit must be set to logic 1 before entering 6-pin serial mode. For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
Table 9. Signal TX_ENABLE TX_DAT TX_SE0 INT RX_DP RX_DM RX_RCV Reserved
[1]
Signal mapping for 6-pin serial mode Maps to DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 Direction[1] Description I I I O O O O active-HIGH transmit enable transmit differential data on DP and DM transmit single-ended zero on DP and DM active-HIGH interrupt indication; will be asserted and latched whenever any unmasked interrupt occurs single-ended receive data from DP single-ended receive data from DM differential receive data from DP and DM reserved; the ISP1512A will drive this pin to LOW
I = input; O = output.
9.2.4 3-pin full-speed or low-speed serial mode
If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1512A to 3-pin serial mode. In 3-pin serial mode, the data bus definition changes to that shown in Table 10. To enter 3-pin serial mode, the link sets the 3PIN_FSLS_SERIAL bit in the INTF_CTRL register to logic 1. To exit 3-pin serial mode, the link asserts STP. This is provided primarily for links that contain legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path to high-speed functionality. An interrupt pin is also provided to inform the link of USB events. If the link requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM register bit must be set to logic 1 before entering 3-pin serial mode. For more information on the 3-pin serial mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
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ULPI HS USB transceiver
Table 10. Signal
Signal mapping for 3-pin serial mode Maps to DATA0 DATA1 DATA2 DATA3 DATA[7:4] Direction[1] Description I I/O I/O O active-HIGH transmit enable transmit differential data on DP and DM when TX_ENABLE is HIGH receive differential data from DP and DM when TX_ENABLE is LOW transmit single-ended zero on DP and DM when TX_ENABLE is HIGH receive single-ended zero from DP and DM when TX_ENABLE is LOW active-HIGH interrupt indication; will be asserted and latched whenever any unmasked interrupt occurs reserved; the ISP1512A will drive these pins to LOW
TX_ENABLE DAT SE0 INT Reserved
[1]
I = input; O = output; I/O = digital input/output.
9.2.5 Transparent UART mode
In transparent UART mode, the ISP1512A functions as a voltage level shifter between following pins:
* From pin DATA0 (VCC(I/O) level) to pin DM (2.7 V level) * From pin DP (2.7 V level) to pin DATA1 (VCC(I/O) level)
The USB transceiver is used to drive the UART transmitting signal on the DM line. The rise time and the fall time of the transmitting signal is determined by whether a full-speed or low-speed transceiver is in use. It is recommended to use a full-speed transceiver if the UART bit rate is equal to or above 921 kbit/s. If the UART bit rate is below 921 kbit/s, a low-speed transceiver may be selected for better EMI performance. In transparent UART mode, data bus definitions change to that shown in Table 11.
Table 11. Signal TXD RXD Reserved INT Reserved
[1]
UART signal mapping Maps to DATA0 DATA1 DATA2 DATA3 DATA[7:4] Direction[1] Description I O O UART TXD signal that is routed to the DM pin UART RXD signal that is routed from the DP pin reserved active-HIGH interrupt indication; must be asserted and latched whenever any unmasked interrupt occurs reserved; the ISP1512A will drive these pins to LOW
I = input; O = output.
Transparent UART mode is entered by setting some register bits in ULPI registers. The recommended sequence is: 1. Set the XCVRSELECT[1:0] bits in the FUNC_CTRL register (see Section 10.5) to 10b (low-speed) or 01b (full-speed). This setting affects the rise time and the fall time of the UART transmitting signal on the DM line. 2. Set the DP_PULLDOWN and DM_PULLDOWN bits in the OTG_CTRL register (see Section 10.7) to logic 0. 3. Set the TERMSELECT bit in the FUNC_CTRL register (see Section 10.5) to logic 0 (power-on default value).
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Remark: Mandatory when a full-speed driver is used and optional for a low-speed driver. 4. Set the TXD_EN and RXD_EN bits in the CARKIT_CTRL register (see Section 10.14) to logic 1. These two bits must be set together in one TXCMD. 5. Set the CARKIT_MODE bit in the INTF_CTRL register (see Section 10.6) to logic 1. Remark: The CARKIT_MODE, TXD_EN and RXD_EN bits must be set to logic 1. The sequence of setting these register bits is ignored. After the register configuration is complete: 1. A weak pull-up resistor will be enabled on the DP and DATA0 pins. This is to avoid the possible floating condition on these input pins when UART mode is enabled. 2. The 39 serial termination resistors on the DP and DM pins will be enabled. 3. One clock cycle after DIR goes from LOW to HIGH, the ISP1512A will drive the data bus for five clock cycles. This is to charge the DATA0 pin to a HIGH level for a slow link. However, the link can start driving DATA0 to HIGH immediately after the turnaround cycle. 4. UART buffers between DATA0 or DATA1 and DM or DP are enabled. Transparent UART mode is entered. Remark: The DP pin will be slowly charged up to HIGH by the weak pull-up resistor. The time needed depends on the capacitive loading on DP. By default, the clock is powered down when the ISP1512A enters UART mode. If the link requires CLOCK to be running in UART mode, it can set the CLOCK_SUSPENDM bit in the INTF_CTRL register to logic 1 before entering UART mode. Transparent UART mode is exited by asserting the STP pin to HIGH or by toggling the CHIP_SEL pin. The INT pin is asserted and latched whenever an unmasked interrupt event occurs. When the link detects INT as HIGH, it must wake up the clock (if powered down) by asserting STP. If the clock is already running, the link asserts STP for one or more clock cycles to switch the interface to synchronous mode. When the PHY is in synchronous mode, the link can read the USB_INTR_L register to determine the source of the interrupt. Note that ISP1512A does not implement optional Carkit Interrupt registers. An alternative way to exit UART mode is to set the CHIP_SEL pin to deassert for more than tPWRDN and then set it to assert. A power-on reset will be generated and the ULPI bus will be put in default synchronous mode.
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ISP1512A
ULPI HS USB transceiver
CLOCK
CLOCK
turnaround
DATA[7:0]
TXCMD (REGW)
DATA
0001 0001
UART mode signals
DIR
STP
NXT
UART mode
004aab160
Fig 5.
Interface behavior when entering UART mode and the clock is powered down
CLOCK
TXCMD (REGW)
DATA
turnaround
UART mode signals
DATA[7:0]
DIR
STP
NXT
UART MODE
004aaa866
Fig 6.
Interface behavior when entering UART mode and the clock remains powered
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CLOCK
CLOCK
turnaround
DATA[7:0]
UART mode signals
0000 0000
synchronous mode signals
DIR
STP NXT
UART mode
004aab161
Fig 7.
Interface behavior when exiting UART mode and the clock is not running
CLOCK
UART mode signals turnaround synchronous mode signals
DATA[7:0]
DIR
one or more clocks
STP NXT UART MODE
004aaa868
Fig 8.
Interface behavior when exiting UART mode and the clock is running
9.3 USB state transitions
A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3. The ISP1512A accommodates various states through register settings of the XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN bits. Table 12 summarizes operating states. The values of register settings in Table 12 will force resistor settings as also given in Table 12. Resistor setting signals are defined as follows.
* RPU_DP_EN enables the 1.5 k pull-up resistor on DP
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* RPD_DP_EN enables the 15 k pull-down resistor on DP * RPD_DM_EN enables the 15 k pull-down resistor on DM * HSTERM_EN enables the 45 termination resistors on DP and DM
It is up to the link to set the desired register settings.
Table 12. Operating states and their corresponding resistor settings Register settings XCVR SELECT [1:0] General settings 3-state drivers Power-up or VBUS < VB_SESS_END Host settings Host chirp Host high-speed Host full-speed Host high-speed or full-speed suspend Host high-speed or full-speed resume Host low-speed Host low-speed suspend Host low-speed resume Peripheral settings Peripheral chirp Peripheral high-speed Peripheral high-speed or full-speed suspend Peripheral high-speed or full-speed resume Peripheral Test J or Test K OTG settings OTG device peripheral chirp OTG device peripheral high-speed
ISP1512A_1
Signaling mode
Internal resistor settings OPMODE [1:0] DP_ DM_ PULL PULL DOWN DOWN Xb 1b Xb 1b RPU_DP RPD_DP RPD_ HSTERM_ _EN _EN DM_EN EN
TERM SELECT
XXb 01b
Xb 0b
01b 00b
0b 0b
0b 1b
0b 1b
0b 0b
00b 00b X1b 01b 01b 10b 10b 10b
0b 0b 1b 1b 1b 1b 1b 1b 0b 1b 0b 1b 1b
10b 00b 00b 00b 10b 00b 00b 10b 10b 10b 00b 00b 00b
1b 1b 1b 1b 1b 1b 1b 1b 1b 0b 0b 0b 0b
1b 1b 1b 1b 1b 1b 1b 1b 1b 0b 0b 0b 0b
0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 0b 1b 1b
1b 1b 1b 1b 1b 1b 1b 1b 1b 0b 0b 0b 0b
1b 1b 1b 1b 1b 1b 1b 1b 1b 0b 0b 0b 0b
1b 1b 0b 0b 0b 0b 0b 0b 1b 0b 1b 0b 0b
Host Test J or Test K 00b 00b 00b
Peripheral full-speed 01b 01b
01b
1b
10b
0b
0b
1b
0b
0b
0b
00b
0b
10b
0b
0b
0b
0b
0b
1b
00b 00b
1b 0b
10b 00b
0b 0b
1b 1b
1b 0b
0b 0b
1b 1b
0b 1b
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Table 12.
Operating states and their corresponding resistor settings ...continued Register settings XCVR SELECT [1:0] TERM SELECT 1b 1b OPMODE [1:0] 00b 00b DP_ DM_ PULL PULL DOWN DOWN 0b 0b 1b 1b Internal resistor settings RPU_DP RPD_DP RPD_ HSTERM_ _EN _EN DM_EN EN 1b 1b 0b 0b 1b 1b 0b 0b
Signaling mode
OTG device 01b peripheral full-speed OTG device peripheral high-speed and full-speed suspend OTG device peripheral high-speed and full-speed resume OTG device peripheral Test J or Test K 01b
01b
1b
10b
0b
1b
1b
0b
1b
0b
00b
0b
10b
0b
1b
0b
0b
1b
1b
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10. Register map
Table 13. Register map Size (bit) 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3Dh to 3Fh Address (6 bit) R[1] 00h 01h 02h 03h 04h to 06h 07h to 09h 0Ah to 0Ch 0Dh to 0Fh 10h to 12h 13h 14h 15h 16h to 18h 19h to 1Bh W[2] 04h 07h 0Ah 0Dh 10h 16h 19h 3Dh S[3] 05h 08h 0Bh 0Eh 11h 17h 1Ah 3Eh C[4] 06h 09h 0Ch 0Fh 12h 18h 1Bh 3Fh Section 10.1 on page 23 Section 10.2 on page 23 Section 10.3 on page 24 Section 10.4 on page 24 Section 10.5 on page 24 Section 10.6 on page 25 Section 10.7 on page 26 Section 10.8 on page 27 Section 10.9 on page 28 Section 10.10 on page 28 Section 10.11 on page 29 Section 10.12 on page 29 Section 10.13 on page 30 Section 10.14 on page 30 Section 10.15 on page 30 References Field name VENDOR_ID_LOW VENDOR_ID_HIGH PRODUCT_ID_LOW PRODUCT_ID_HIGH FUNC_CTRL INTF_CTRL OTG_CTRL USB_INTR_EN_R USB_INTR_EN_F USB_INTR_STAT USB_INTR_L DEBUG SCRATCH CARKIT_CTRL Reserved PWR_CTRL
[1] [2] [3] [4]
1Ch to 3Ch
Read (R): A register can be read. Read-only if this is the only mode given. Write (W): The pattern on the data bus will be written over all bits of a register. Set (S): The pattern on the data bus is OR-ed with and written to a register. Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero (cleared).
10.1 VENDOR_ID_LOW register
Table 14 shows the bit description of the register.
Table 14. VENDOR_ID_LOW - Vendor ID Low register (address R = 00h) bit description Legend: * reset value Bit 7 to 0 Symbol VENDOR_ ID_LOW[7:0] Access R Value CCh* Description Vendor ID Low: Lower byte of the NXP vendor ID supplied by USB-IF; fixed value of CCh
10.2 VENDOR_ID_HIGH register
Table 15 shows the bit description of the register.
Table 15. VENDOR_ID_HIGH - Vendor ID High register (address R = 01h) bit description Legend: * reset value Bit 7 to 0 Symbol VENDOR_ ID_HIGH[7:0] Access R Value 04h* Description Vendor ID High: Upper byte of the NXP vendor ID supplied by USB-IF; fixed value of 04h
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10.3 PRODUCT_ID_LOW register
The bit description of the PRODUCT_ID_LOW register is given in Table 16.
Table 16. PRODUCT_ID_LOW - Product ID Low register (address R = 02h) bit description Legend: * reset value Bit 7 to 0 Symbol PRODUCT_ID_ LOW[7:0] Access R Value 12h* Description Product ID Low: Lower byte of the NXP product ID number; fixed value of 12h
10.4 PRODUCT_ID_HIGH register
The bit description of the register is given in Table 17.
Table 17. PRODUCT_ID_HIGH - Product ID High register (address R = 03h) bit description Legend: * reset value Bit 7 to 0 Symbol PRODUCT_ID_ HIGH[7:0] Access R Value 15h* Description Product ID High: Upper byte of the NXP product ID number; fixed value of 15h
10.5 FUNC_CTRL register
This register controls UTMI function settings of the PHY. The bit allocation of the register is given in Table 18.
Table 18. Bit Symbol Reset Access FUNC_CTRL - Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation 7 reserved 0 R/W/S/C 6 SUSPENDM 1 R/W/S/C 5 RESET 0 R/W/S/C 4 3 2 TERM SELECT 0 R/W/S/C 1 0 OPMODE[1:0] 0 R/W/S/C 0 R/W/S/C XCVRSELECT[1:0] 0 R/W/S/C 1 R/W/S/C
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Table 19. Bit 7 6
FUNC_CTRL - Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description Symbol SUSPENDM Description reserved Suspend LOW: Active-LOW PHY suspend. Places the PHY into low-power mode. The PHY will power down all blocks, except the full-speed receiver, OTG comparators and ULPI interface pins. To come out of low-power mode, the link must assert STP. The PHY will automatically clear this bit when it exits low-power mode. 0b -- Low-power mode 1b -- Powered
5
RESET
Reset: Active-HIGH transceiver reset. After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not reset the ULPI interface or the ULPI register set. When the reset is completed, the PHY will deassert DIR and automatically clear this bit, followed by an RXCMD update to the link. The link must wait for DIR to be deasserted before using the ULPI bus. 0b -- Do not reset 1b -- Reset
4 to 3
OPMODE[1:0]
Operation Mode: Selects the required bit-encoding style during transmit. 00b -- Normal operation 01b -- Non-driving 10b -- Disable bit-stuffing and NRZI encoding 11b -- Do not automatically add SYNC and EOP when transmitting; must be used only for high-speed packets
2
TERMSELECT
Termination Select: Controls the internal 1.5 k full-speed pull-up resistor and 45 high-speed terminations. Control over bus resistors changes, depending on XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in Table 12. Transceiver Select: Selects the required transceiver speed. 00b -- Enable the high-speed transceiver 01b -- Enable the full-speed transceiver 10b -- Enable the low-speed transceiver 11b -- Enable the full-speed transceiver for low-speed packets (full-speed preamble is automatically prefixed)
1 to 0
XCVRSELECT [1:0]
10.6 INTF_CTRL register
The INTF_CTRL register enables alternative interfaces. All of these modes are optional features provided for legacy link cores. Setting more than one of these fields results in undefined behavior. Table 20 provides bit allocation of the register.
Table 20. Bit Symbol INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation 7 6 reserved 5 4 3 CLOCK_ SUSPENDM 0 R/W/S/C 0 R/W/S/C 0 R/W/S/C 2 CARKIT_ MODE 0 R/W/S/C 1 3PIN_ FSLS_ SERIAL 0 R/W/S/C 0 6PIN_ FSLS_ SERIAL 0 R/W/S/C
Reset Access
ISP1512A_1
0 R/W/S/C
0 R/W/S/C
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Table 21. Bit 3
INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description Description reserved Clock Suspend: active-LOW clock suspend. Powers down the internal clock circuitry only. By default, the clock will not be powered in 6-pin serial mode or 3-pin serial mode. Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set to logic 1, otherwise this bit is ignored. 0b -- Clock will not be powered in 3-pin or 6-pin serial mode or UART mode 1b -- Clock will be powered in 3-pin and 6-pin serial mode or UART mode
Symbol CLOCK_SUSPENDM
7 to 4 -
2
CARKIT_MODE
Carkit Mode: Changes the ULPI interface to the carkit interface (UART mode). Bits TXD_EN and RXD_EN in the CARKIT_CTRL register must change as well. The PHY must automatically clear this bit when carkit mode is exited. 0b -- Disable carkit mode 1b -- Enable carkit mode
1
3PIN_FSLS_SERIAL
3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial interface. The ISP1512A will automatically clear this bit when 3-pin serial mode is exited. 0b -- Full-speed or low-speed packets are sent using the parallel interface 1b -- Full-speed or low-speed packets are sent using the 3-pin serial interface
0
6PIN_FSLS_SERIAL
6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 6-bit serial interface. The ISP1512A will automatically clear this bit when 6-pin serial mode is exited. 0b -- Full-speed or low-speed packets are sent using the parallel interface 1b -- Full-speed or low-speed packets are sent using the 6-pin serial interface
10.7 OTG_CTRL register
This register controls various OTG functions of the ISP1512A. The bit allocation of the OTG_CTRL register is given in Table 22.
Table 22. Bit Symbol Reset Access 0 R/W/S/C OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation 7 6 reserved 0 R/W/S/C 0 R/W/S/C 5 4 CHRG_ VBUS 0 R/W/S/C 3 DISCHRG_ VBUS 0 R/W/S/C 2 DM_PULL DOWN 1 R/W/S/C 1 DP_PULL DOWN 1 R/W/S/C 0 reserved 0 R/W/S/C
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Table 23. Bit 4 7 to 5 -
OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description Description reserved Charge VBUS: Charges VBUS through a resistor. Used for the VBUS pulsing of SRP. The link must first check that VBUS is discharged (see bit DISCHRG_VBUS), and that both the DP and DM data lines have been LOW (SE0) for 2 ms. 0b -- Do not charge VBUS 1b -- Charge VBUS
Symbol CHRG_VBUS
3
DISCHRG_VBUS
Discharge VBUS: Discharges VBUS through a resistor. If the link sets this bit to logic 1, it waits for an RXCMD indicating that SESS_END has changed from logic 0 to logic 1, and then resets this bit to logic 0 to stop the discharge. 0b -- Do not discharge VBUS 1b -- Discharge VBUS
2
DM_PULLDOWN
DM Pull Down: Enables the 15 k pull-down resistor on DM. 0b -- Pull-down resistor is not connected to DM 1b -- Pull-down resistor is connected to DM
1
DP_PULLDOWN
DP Pull Down: Enables the 15 k pull-down resistor on DP. 0b -- Pull-down resistor is not connected to DP 1b -- Pull-down resistor is connected to DP
0
-
reserved
10.8 USB_INTR_EN_R register
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding bits in the USB_INTR_STAT register change from logic 0 to logic 1. By default, all transitions are enabled. Table 24 shows the bit allocation of the register.
Table 24. Bit Symbol Reset Access Table 25. Bit 7 to 4 3 2 1 0 0 R/W/S/C 0 R/W/S/C USB_INTR_EN_R - USB Interrupt Enable Rising register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit allocation 7 6 reserved 0 R/W/S/C 1 R/W/S/C 5 4 3 SESS_ END_R 1 R/W/S/C 2 SESS_ VALID_R 1 R/W/S/C 1 VBUS_ VALID_R 1 R/W/S/C 0 HOST_ DISCON_R 1 R/W/S/C
USB_INTR_EN_R - USB Interrupt Enable Rising register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit description Description reserved Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on SESS_END. Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on SESS_VLD. VBUS Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on A_VBUS_VLD.
Symbol SESS_END_R SESS_VALID_R VBUS_VALID_R
HOST_DISCON_R Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on HOST_DISCON.
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10.9 USB_INTR_EN_F register
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding bits in the USB_INTR_STAT register change from logic 1 to logic 0. By default, all transitions are enabled. See Table 26.
Table 26. Bit Symbol Reset Access Table 27. Bit 7 to 4 3 2 1 0 0 R/W/S/C 0 R/W/S/C USB_INTR_EN_F - USB Interrupt Enable Falling register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit allocation 7 6 reserved 0 R/W/S/C 1 R/W/S/C 5 4 3 SESS_ END_F 1 R/W/S/C 2 SESS_ VALID_F 1 R/W/S/C 1 VBUS_ VALID_F 1 R/W/S/C 0 HOST_ DISCON_F 1 R/W/S/C
USB_INTR_EN_F - USB Interrupt Enable Falling register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit description Symbol SESS_END_F SESS_VALID_F VBUS_VALID_F HOST_DISCON_F Description reserved Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on SESS_END. Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on SESS_VLD. VBUS Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on A_VBUS_VLD. Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on HOST_DISCON.
10.10 USB_INTR_STAT register
This register (see Table 28) indicates the current value of the interrupt source signal.
Table 28. Bit Symbol Reset Access Table 29. Bit 7 to 4 3 2 1 0 SESS_END SESS_VALID VBUS_VALID HOST_DISCON X R X R USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation 7 6 reserved X R 0 R 5 4 3 SESS_ END 0 R 2 SESS_ VALID 0 R 1 VBUS_ VALID 0 R 0 HOST_ DISCON 0 R
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit description Symbol Description reserved Session End: Reflects the current value of the session end voltage comparator. Session Valid: Reflects the current value of the session valid voltage comparator. VBUS Valid: Reflects the current value of the VBUS valid voltage comparator. Host Disconnect: Reflects the current value of the host disconnect detector.
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ULPI HS USB transceiver
10.11 USB_INTR_L register
The bits of the USB_INTR_L register are automatically set by the ISP1512A when an unmasked change occurs on the corresponding interrupt source signal. The ISP1512A will automatically clear all bits when the link reads this register, or when the PHY enters low-power mode. Remark: It is optional for the link to read this register when the clock is running because all signal information will automatically be sent to the link through the RXCMD byte. The bit allocation of this register is given in Table 30.
Table 30. Bit Symbol Reset Access Table 31. Bit 7 to 4 3 2 1 0 0 R 0 R USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit allocation 7 6 reserved 0 R 0 R 5 4 3 SESS_ END_L 0 R 2 SESS_ VALID_L 0 R 1 VBUS_ VALID_L 0 R 0 HOST_ DISCON_L 0 R
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description Symbol SESS_END_L SESS_VALID_L VBUS_VALID_L HOST_DISCON_L Description reserved Session End Latch: Automatically set when an unmasked event occurs on SESS_END. Cleared when this register is read. Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD. Cleared when this register is read. VBUS Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD. Cleared when this register is read. Host Disconnect Latch: Automatically set when an unmasked event occurs on HOST_DISCON. Cleared when this register is read.
10.12 DEBUG register
The bit allocation of the DEBUG register is given in Table 32. This register indicates the current value of signals useful for debugging.
Table 32. Bit Symbol Reset Access Table 33. Bit 7 to 2 1 0 0 R 0 R 0 R DEBUG - Debug register (address R = 15h) bit allocation 7 6 5 reserved 0 R 0 R 0 R 4 3 2 1 LINE STATE1 0 R 0 LINE STATE0 0 R
DEBUG - Debug register (address R = 15h) bit description Symbol LINESTATE1 LINESTATE0 Description reserved Line State 1: Contains the current value of LINESTATE 1 Line State 0: Contains the current value of LINESTATE 0
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10.13 SCRATCH register
This is a 1-byte empty register for testing purposes, see Table 34.
Table 34. Bit 7 to 0 SCRATCH - Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description Symbol SCRATCH[7:0] Access R/W/S/C Value 00h Description Scratch: This is an empty register byte for testing purposes. Software can read, write, set and clear this register. The functionality of the PHY will not be affected.
10.14 CARKIT_CTRL register
This register controls transparent UART mode. This register is only valid when the CARKIT_MODE register bit in the INTF_CTRL register is set. When entering UART mode set the CARKIT_MODE bit, and then set the TXD_EN and RXD_EN bits. After entering UART mode, the ULPI interface is not available. When exiting UART mode, assert the STP pin or perform a hardware reset using the CHIP_SEL pin. For bit allocation, see Table 35.
Table 35. Bit Symbol Reset Access Table 36. Bit 7 to 4 3 2 1 to 0 0 R/W/S/C 0 R/W/S/C CARKIT_CTRL - Carkit Control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit allocation 7 6 reserved 0 R/W/S/C 0 R/W/S/C 5 4 3 RXD_EN 0 R/W/S/C 2 TXD_EN 0 R/W/S/C 0 R/W/S/C 1 reserved 0 R/W/S/C 0
CARKIT_CTRL - Carkit Control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit description Symbol RXD_EN TXD_EN Description reserved; the link must never write logic 1 to these bits RXD Enable: Routes the UART RXD signal from the DP pin to the DATA1 pin. This bit will automatically be cleared when UART mode is exited. TXD Enable: Routes the UART TXD signal from the DATA0 pin to the DM pin. This bit will automatically be cleared when UART mode is exited. reserved; the link must never write logic 1 to these bits
10.15 PWR_CTRL register
This vendor-specific register controls the power feature of the ISP1512A. The bit allocation of the register is given in Table 37.
Table 37. Bit Symbol Reset Access 0 R/W/S/C PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation 7 6 reserved 0 R/W/S/C 0 R/W/S/C 5 4 DP_WKPU _EN 0 R/W/S/C 3 BVALID_ FALL 0 R/W/S/C 2 BVALID_ RISE 0 R/W/S/C 0 R/W/S/C 1 reserved 0 R/W/S/C 0
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Table 38. Bit 7 to 5 4 -
PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description Description reserved; the link must never write logic 1 to these bits
Symbol
DP_WKPU_EN DP Weak Pull-Up Enable: Enables the weak pull-up resistor on the DP pin (RweakUP(DP)) in synchronous mode when VBUS is above the VA_SESS_VLD threshold. Note that when the ISP1512A is in UART mode, the DP weak pull-up will be enabled, regardless of the value of this register bit. 0b -- DP weak pull-up is disabled 1b -- DP weak pull-up is enabled when VBUS > VA_SESS_VLD
3
BVALID_FALL
BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID changes from HIGH to LOW, the ISP1512A will send an RXCMD to the link with the ALT_INT bit set to logic 1. This bit is optional and is not necessary for OTG devices. This bit is provided for debugging purposes. Disabled by default.
2
BVALID_RISE
BVALID Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID changes from LOW to HIGH, the ISP1512A will send an RXCMD to the link with the ALT_INT bit set to logic 1. This bit is optional and is not necessary for OTG devices. This bit is provided for debugging purposes. Disabled by default.
1 to 0
-
reserved; the link must never write logic 1 to these bits
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11. Limiting values
Table 39. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VCC(I/O) VI Parameter supply voltage input/output supply voltage input voltage on pin VBUS on pins CLOCK, STP, DATA[7:0] and CHIP_SEL on pins DP and DM on pin XTAL1 VESD electrostatic discharge voltage human body model (JESD22-A114D) machine model (JESD22-A115-A) charge device model (JESD22-C101-A) IEC 61000-4-2 contact on pins DP and DM Ilu Tstg
[1]
[3] [2] [1]
Conditions
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -2000 -200 -500 -8 -60
Max +5.5 +2.5 +5.5 +2.5 +4.6 +2.5 +2000 +200 +500 +8 100 +125
Unit V V V V V V V V V kV mA C
latch-up current storage temperature
When an external series resistor is added to the VBUS pin, it can withstand higher voltages for longer periods of time because the resistor limits the current flowing into the VBUS pin. For example, with an external 1 k resistor, VBUS can tolerate 10 V for at least 5 seconds. Actual performance may vary depending on the resistor used and whether other components are connected to VBUS. The ISP1512A has been tested according to the additional requirements listed in Universal Serial Bus Specification Rev. 2.0, Section 7.1.1. The AC stress test was performed for 24 hours, and the ISP1512A was found to be fully operational after the test completed. The ISP1512A was found to be fully functional after shorting the high-speed DP and DM pins to ground for 24 hours. Transmit and receive were occurring 50 % of the time. The ISP1512A has been tested in-house according to the IEC 61000-4-2 standard on the DP and DM pins. It is recommended that customers perform their own ESD tests, depending on application requirements.
[2]
[3]
12. Recommended operating conditions
Table 40. Symbol VCC VCC(I/O) VI Recommended operating conditions Parameter supply voltage input/output supply voltage input voltage on pin VBUS on pins CLOCK, STP, DATA[7:0] and CHIP_SEL on pins DP and DM on pin XTAL1 Tamb Tj ambient temperature junction temperature Conditions Min 3.0 1.65 0 0 0 0 -40 -40 Typ 3.6 1.8 +25 Max 4.5 1.95 5.25 VCC(I/O) 3.6 1.95 +85 +125 Unit V V V V V V C C
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13. Static characteristics
Table 41. Static characteristics: supply pins VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol VPOR(trip) ICC Parameter power-on reset trip voltage supply current Conditions on pin REG1V8 power-down mode (VCC(I/O) is lost or chip select is deasserted) full-speed transceiver; bus idle; no USB activity full-speed transceiver; 100 % transmission; no inter-packet delay high-speed transceiver; 100 % transmission; no inter-packet delay low-power mode (SUSPENDM = 0); VBUS valid detector disabled (bits VBUS_VALID_R and VBUS_VALID_F are cleared) for host for peripheral UART mode; low-speed transceiver; idle UART mode; full-speed transceiver; idle ICC(I/O) supply current on pin VCC(I/O) power-down mode (chip select is deasserted) ULPI bus idle; 15 pF load on pin CLOCK
[1]
[1]
Min 0.95 -
Typ 0.5 14 26 55
Max 1.5 10 -
Unit V A mA mA mA
-
70 240 750 600 2
100 330 10 -
A A A A A mA
The actual value of ICC(I/O) varies depending on the capacitance loading, interface voltage and bus activity. Use the value provided here only for reference.
Table 42. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL) VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Input levels VIL VIH ILI VOL VOH IOH IOL ZL
ISP1512A_1
Conditions
Min 0.7VCC(I/O) -1
Typ 50
Max
Unit
LOW-level input voltage HIGH-level input voltage input leakage current LOW-level output voltage HIGH-level output voltage HIGH-level output current LOW-level output current load impedance IOL = -2 mA IOH = +2 mA VOH = VCC(I/O) - 0.4 V VOL = 0.4 V
0.3VCC(I/O) V +1 0.4 V A V V mA mA
Output levels VCC(I/O) - 0.4 -4.8 4.2 -
Impedance
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Table 42. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL) ...continued VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Pull up and pull down Ipd Ipu pull-down current pull-up current interface protect enabled; DATA[7:0] pins only; VI = VCC(I/O) interface protect enabled; STP pin only; VI = 0 V UART mode; DATA0 pin only Capacitance Cin input capacitance 1.0 3.0 3.3 pF 18 -17 -17 55 -55 -55 93 -82 -82 A A A Conditions Min Typ Max Unit
Table 43. Static characteristics: analog pins (DP, DM) VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Original USB transceiver (full-speed and low-speed) Input levels (differential data receiver) VDI VCM VIL VIH Output levels VOL VOH LOW-level output voltage HIGH-level output voltage pull-up on pin DP; RL = 1.5 k to 3.6 V pull-down on pins DP and DM; RL = 15 k to GND excluding the first transition from the idle state for 1.5 k pull-up resistor 0.0 2.8 0.3 3.6 V V differential input sensitivity voltage differential common mode voltage range LOW-level input voltage HIGH-level input voltage |VDP - VDM| includes VDI range 0.2 0.8 2.0 2.5 0.8 V V V V
Input levels (single-ended receivers)
VCRS
output signal crossover voltage
1.3
-
2.0
V
Termination VTERM Resistance RUP(DP) RweakUP(DP) pull-up resistance on pin DP weak pull-up resistance on pin DP bit DP_WKPU_EN = 1 and VBUS > VA_SESS_VLD 1425 104 1500 130 1575 156 k termination voltage for upstream facing port pull-up 3.0 3.6 V
High-speed USB transceiver (HS) Input levels VHSSQ VHSDSC VHSDI
ISP1512A_1
high-speed squelch detection threshold voltage (differential signal amplitude) high-speed disconnect detection threshold voltage (differential signal amplitude) high-speed differential input sensitivity |VDP - VDM|
100 525 300
-
150 625 -
mV mV mV
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Table 43. Static characteristics: analog pins (DP, DM) ...continued VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol VHSCM Output levels VHSOI VHSOL VHSOH VCHIRPJ VCHIRPK ILZ Capacitance Cin Resistance RDN(DP) RDN(DM) Termination ZO(drv)(DP) ZO(drv)(DM) ZINP UART mode Input levels VIL VIH Output levels VOL VOH LOW-level output voltage HIGH-level output voltage pin DM; IOL = -4 mA pin DM; IOH = 4 mA 2.4 0.3 V V LOW-level input voltage HIGH-level input voltage pin DP pin DP 2.35 0.8 V V driver output impedance on pin DP driver output impedance on pin DM input impedance exclusive of pull-up/pull-down (for low-/full-speed) steady-state drive steady-state drive 40.5 40.5 1 45 45 49.5 49.5 M pull-down resistance on pin DP pull-down resistance on pin DM 14.25 14.25 15 15 24.8 24.8 k k input capacitance pin to GND 5 pF high-speed idle level voltage high-speed data signaling LOW-level voltage high-speed data signaling HIGH-level voltage Chirp J level (differential voltage) Chirp K level (differential voltage) off-state leakage current -10 -10 360 700 -900 -1.0 +10 +10 440 1100 -500 +1.0 mV mV mV mV mV A Parameter high-speed data signaling common mode voltage range (guideline for receiver) Conditions includes VDI range Min -50 Typ Max +500 Unit mV
Leakage current
Table 44. Static characteristics: analog pin VBUS VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol Comparators VA_VBUS_VLD VA_SESS_VLD Vhys(A_SESS_VLD) VB_SESS_END A-device VBUS valid voltage A-device session valid voltage for A-device and B-device A-device session valid hysteresis for A-device and B-device voltage B-device session end voltage 4.4 0.8 0.2 1.6 100 4.75 2.0 0.8 V V mV V Parameter Conditions Min Typ Max Unit
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Table 44. Static characteristics: analog pin VBUS ...continued VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol Resistance RUP(VBUS) RDN(VBUS) RI(idle)(VBUS) pull-up resistance on pin VBUS connect to REG3V3 when CHRG_VBUS = 1 281 656 75 40 140 680 1200 90 100 100 220 k k k Parameter Conditions Min Typ Max Unit
pull-down resistance on pin VBUS connect to GND when DISCHRG_VBUS = 1 idle input resistance on pin VBUS not in power-down mode chip deasserted (power-down mode) VCC(I/O) lost (power-down mode)
Table 45. Static characteristics: resistor reference VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol VO(RREF) Parameter output voltage on pin RREF Conditions SUSPENDM = 1 Min Typ 1.22 Max Unit V
Table 46. Static characteristics: pin XTAL1 VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIL VIH Parameter LOW-level input voltage HIGH-level input voltage Conditions Min 1.32 Typ Max 0.37 Unit V V
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14. Dynamic characteristics
Table 47. Dynamic characteristics: reset and power VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tW(POR) tw(REG1V8_H) tw(REG1V8_L) tstartup(PLL) td(det)clk(osc) tPWRUP tPWRDN Parameter internal power-on reset pulse width REG1V8 HIGH pulse width REG1V8 LOW pulse width PLL start-up time oscillator clock detector delay regulator start-up time regulator power-down time measured after td(det)clk(osc) measured from regulator start-up time 4.7 F 20 % capacitor each on the REG1V8 and REG3V3 pins 4.7 F 20 % capacitor each on the REG1V8 and REG3V3 pins Conditions Min 0.2 Typ Max 2 11 640 640 1 100 Unit s s s s s ms ms
Table 48. Dynamic characteristics: clock applied to XTAL1 VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol fi(XTAL1) tjit(i)(XTAL1)RMS fi(XTAL1) i(XTAL1) tr(XTAL1) tf(XTAL1)
[1]
Parameter input frequency on pin XTAL1 RMS input jitter on pin XTAL1 input frequency tolerance on pin XTAL1 input duty cycle on pin XTAL1 rise time on pin XTAL1 fall time on pin XTAL1
Conditions
Min [1]
Typ 19.200 50 -
Max 200 200 5 5
Unit MHz ps ppm % ns ns
-
The internal PLL is triggered only on the positive edge from the crystal oscillator. Therefore, the duty cycle is not critical.
Table 49. Dynamic characteristics: CLOCK output VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol fo(CLOCK) o(CLOCK) Parameter output frequency on pin CLOCK output clock duty cycle on pin CLOCK Conditions Min 59.970 40 Typ 60.000 50 Max 60.030 500 60 Unit MHz ps %
tjit(o)(CLOCK)RMS RMS output jitter on pin CLOCK
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Table 50. Dynamic characteristics: digital I/O pins VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tsu Parameter set-up time Conditions set-up time with respect to the positive edge of CLOCK; input-only pin (STP) and bidirectional pins (DATA[7:0]) as inputs hold time with respect to the positive edge of CLOCK; input-only pin (STP) and bidirectional pins (DATA[7:0]) as inputs output delay with respect to the positive edge of CLOCK; output-only pins (DIR, NXT) output delay with respect to the positive edge of CLOCK; bidirectional pins as output (DATA[7:0]) CL load capacitance DATA[7:0], CLOCK, DIR, NXT, STP
[1]
Min -
Typ -
Max 6.0
Unit ns
th
hold time
0.0
-
-
ns
td(o)
output delay time
-
-
9.0 9.0 20
ns ns pF
[1]
Load capacitance on each ULPI pin.
Table 51. Dynamic characteristics: analog I/O pins (DP, DM) in USB mode VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tHSR tHSF tFR tFF tFRFM Parameter rise time (10 % to 90 %) fall time (10 % to 90 %) rise time fall time differential rise and fall time matching transition time: rise time transition time: fall time Conditions drive 45 to GND on pins DP and DM drive 45 to GND on pins DP and DM CL = 50 pF; 10 % to 90 % of |VOH - VOL| CL = 50 pF; 10 % to 90 % of |VOH - VOL| tFR/tFF; excluding the first transition from the idle state CL = 200 pF to 600 pF; 1.5 k pull up on pin DM enabled; 10 % to 90 % of |VOH - VOL| CL = 200 pF to 600 pF; 1.5 k pull up on pin DM enabled; 10 % to 90 % of |VOH - VOL| Min 500 500 4 4 90 Typ Max 20 20 111.1 Unit ps ps ns ns % High-speed driver characteristics
Full-speed driver characteristics
Low-speed driver characteristics tLR tLF tLRFM 75 75 80 300 300 125 ns ns %
rise and fall time matching tLR/tLF; excluding the first transition from the idle state
Table 52. Dynamic characteristics: analog I/O pins (DP, DM) in transparent UART mode VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol tr(UART) tf(UART) tPLH(drv) tPHL(drv) Parameter rise time for UART TXD fall time for UART TXD driver propagation delay (LOW to HIGH) driver propagation delay (HIGH to LOW) Conditions CL = 185 pF; 0.37 V to 2.16 V CL = 185 pF; 2.16 V to 0.37 V CL = 185 pF; DATA0 to DM CL = 185 pF; DATA0 to DM Min 25 25 Typ Max 75 75 39 34 Unit ns ns ns ns Full-speed driver characteristics (DM only)
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ULPI HS USB transceiver
Table 52. Dynamic characteristics: analog I/O pins (DP, DM) in transparent UART mode ...continued VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol tr(UART) tf(UART) tPLH(drv) tPHL(drv) Parameter rise time for UART TXD fall time for UART TXD driver propagation delay (LOW to HIGH) driver propagation delay (HIGH to LOW) receiver propagation delay (LOW to HIGH) receiver propagation delay (HIGH to LOW) receiver propagation delay (LOW to HIGH) receiver propagation delay (HIGH to LOW) Conditions CL = 185 pF; 0.37 V to 2.16 V CL = 185 pF; 2.16 V to 0.37 V CL = 185 pF; DATA0 to DM CL = 185 pF; DATA0 to DM Min 100 100 Typ Max 400 400 614 614 Unit ns ns ns ns Low-speed driver characteristics (DM only)
Full-speed receiver characteristics (DP only) tPLH(rcv) tPHL(rcv) DP to DATA1 DP to DATA1 7 7 ns ns
Low-speed receiver characteristics (DP only) tPLH(rcv) tPHL(rcv) DP to DATA1 DP to DATA1 7 7 ns ns
Table 53. Dynamic characteristics: analog I/O pins (DP, DM) in serial mode VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol tPLH(drv) tPHL(drv) tPHZ tPLZ tPZH tPZL Parameter Conditions Min Typ Max 20 20 12 12 20 20 Unit ns ns ns ns ns ns Driver timing driver propagation delay (LOW to TX_DAT, TX_SE0 to DP, DM; HIGH) see Figure 10 driver propagation delay (HIGH to TX_DAT, TX_SE0 to DP, DM; LOW) see Figure 10 driver disable delay from HIGH level driver disable delay from LOW level driver enable delay to HIGH level driver enable delay to LOW level TX_ENABLE to DP, DM; see Figure 11 TX_ENABLE to DP, DM; see Figure 11 TX_ENABLE to DP, DM; see Figure 11 TX_ENABLE to DP, DM; see Figure 11
Receiver timing Differential receiver tPLH(rcv) tPHL(rcv) receiver propagation delay (LOW to HIGH) DP, DM to RX_RCV, RX_DP and RX_DM; see Figure 12 20 20 ns ns
receiver propagation delay (HIGH DP, DM to RX_RCV, RX_DP and to LOW) RX_DM; see Figure 12
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Table 53. Dynamic characteristics: analog I/O pins (DP, DM) in serial mode ...continued VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Symbol tPLH(se) tPHL(se) Parameter single-ended propagation delay (LOW to HIGH) single-ended propagation delay (HIGH to LOW) Conditions DP, DM to RX_RCV, RX_DP and RX_DM; see Figure 12 DP, DM to RX_RCV, RX_DP and RX_DM; see Figure 12 Min Typ Max 20 20 Unit ns ns Single-ended receiver
1.8 V logic input 0.9 V tHSR, tFR, tLR VOH tHSF, tFF, tLF 0V 90 % 90 % tPLH(drv) VOH differential data lines
004aaa861
0.9 V
tPHL(drv)
VCRS
VCRS
004aaa573
VOL
10 %
10 % VOL
Fig 9.
Rise time and fall time
Fig 10. Timing of TX_DAT and TX_SE0 to DP and DM
2.0 V 0.9 V differential data lines 0.8 V VCRS tPLH(rcv) tPLH(se) VOH logic output
004aaa574
1.8 V logic 0.9 V input 0V VOH differential data lines VOL tPZH tPZL VCRS VOL + 0.3 V
VCRS tPHL(rcv) tPHL(se)
tPHZ tPLZ VOH - 0.3 V
0.9 V
0.9 V
004aaa575
VOL
Fig 11. Timing of TX_ENABLE to DP and DM
Fig 12. Timing of DP and DM to RX_RCV, RX_DP and RX_DM
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CLOCK tsu Control IN (STP) tsu th th
DATA IN (8-bit)
td(o) Control OUT (DIR, NXT) td(o) DATA OUT (8-bit)
004aaa993
td(o)
Fig 13. ULPI timing interface
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15. Application information
Table 54. RRREF Rs(VBUS) CXTAL CVBUS Recommended bill of materials Application mandatory in all applications optional; for peripheral or external 5 V applications mandatory in output clock mode only mandatory for peripherals mandatory for host mandatory for OTG Cbypass Cfilter DESD highly recommended for all applications highly recommended for all applications recommended to prevent damages from ESD Part type 12 k 1 % 1 k 5 % 18 pF 20 % 1 F to 10 F 96 F (min) 1 F to 6.5 F 0.1 F 20 % 4.7 F 20 % Remark use a low ESR capacitor (0.2 to 2 ) for best performance IP4359CX4/LF; Wafer-Level Chip-Scale Package (WLCSP); ESD IEC 61000-4-2 level 4; 15 kV contact; 15 kV air discharge compliant protection ISP1512A and IP4359CX4/LF together have an IEC 61000-4-2 contact discharge tolerance of 20 kV XTAL mandatory; alternatively pin XTAL1 can be driven by a square wave of the same frequency 19.2 MHz CL = 10 pF; RS < 220 ; CXTAL = 18 pF Designator
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Preliminary data sheet Rev. 01 -- 31 July 2008
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VCC VCC(I/O)
Cbypass Cbypass
E1 A4 VCC(I/O) RREF XTAL2 TEST DM DP VCC CHIP_SEL CLOCK DATA0 DATA1 DATA2 DATA3 DATA4 A2 A3 A1 B1 B2 B3 B4 A5 DATA5 B5 C5 C4 D4 D5 E3 DATA6 DATA7 NXT STP DIR CLKOUT CHIP_SEL CLOCK DATA0 DATA1 DATA2 DATA3 DATA4 USB PERIPHERAL CONTROLLER
RRREF
C2 E4
VBUS
1
D3 C1 D1
D-
2
D+
3
USB STANDARD-B RECEPTACLE
GND
4
A1
A2
IP4359CX4/LF
SHIELD 5 B1 B2
DESD
ISP1512A
DATA5 DATA6
RS(VBUS)
SHIELD
6 E2 VBUS
SHIELD
7
CVBUS
DATA7 NXT STP
D2
Cbypass Cfilter
SHIELD
8
REG3V3
E5
Cbypass Cfilter
REG1V8
DIR XTAL1 GND C3
ULPI HS USB transceiver
ISP1512A
004aab142
43 of 55
Fig 14. Using the ISP1512A with a standard USB peripheral controller
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Preliminary data sheet Rev. 01 -- 31 July 2008
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NXP Semiconductors
5V
IN VBUS POWER SWITCH
EN
EN FAULT VCC VCC(I/O) USB HOST CONTROLLER E1 A4
RRREF
OUT
FAULT
Cbypass
Cbypass
VCC(I/O) RREF TEST DM DP
VCC
CHIP_SEL CLOCK DATA0 DATA1 DATA2 DATA3
A2 A3 A1 B1 B2 B3 B4 A5 B5 C5 C4 D4 D5
CHIP_SEL CLOCK DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 NXT STP
C2 D3 C1 D1
VBUS D- D+ USB STANDARD-A GND RECEPTACLE SHIELD SHIELD SHIELD SHIELD
1 2 3 4 5 6 7 8
CXTAL Cfilter CVBUS Cbypass XTAL CXTAL
A1
A2
IP4359CX4/LF
B1 B2
DESD
ISP1512A
DATA4 DATA5
RS(VBUS)
E2 E3 E4 D2 E5
VBUS XTAL1 XTAL2 REG3V3 REG1V8
DATA6 DATA7 NXT STP GND C3 DIR
ULPI HS USB transceiver
DIR
004aab141
Cbypass
Cfilter Cbypass Cfilter
ISP1512A
44 of 55
Fig 15. Using the ISP1512A with a standard USB host controller
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3.3 V
IN VBUS POWER SWITCH
EN
EN ID VCC VCC(I/O) USB OTG CONTROLLER E1 A4
RRREF
OUT
Cbypass
Cbypass
VCC(I/O) RREF VBUS DM DP TEST
VCC
CHIP_SEL CLOCK DATA0 DATA1 DATA2 DATA3
A2 A3 A1 B1 B2 B3 B4 A5 B5 C5 C4 D4 D5
CHIP_SEL CLOCK DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 NXT STP
C2 E2 C1 D1
VBUS D- D+ MICRO-AB CONNECTOR ID GND SHIELD SHIELD SHIELD SHIELD
1 2 3 4 5 6 7 8 9
CXTAL CXTAL XTAL CVBUS Cbypass
A1
A2
D3
IP4359CX4/LF
B1 B2
DESD
ISP1512A
DATA4 DATA5 DATA6
E3 E4 D2 E5
XTAL1 XTAL2 REG3V3 REG1V8
DATA7 NXT STP GND C3 DIR
ULPI HS USB transceiver
DIR
004aab158
Cbypass
Cfilter Cbypass Cfilter
ISP1512A
45 of 55
Fig 16. Using the ISP1512A with a standard USB OTG controller
NXP Semiconductors
ISP1512A
ULPI HS USB transceiver
16. Package outline
WLCSP25: wafer level chip-size package; 25 bumps; 2.24 x 2.21 x 0.6 mm ISP1512xUK
D
B
A
bump A1 index area A2 E A A1
detail X
e1 e3 e b v w
M M
CAB C
C y
E D C B
e4 e2
e
A
1
2
3
4
5
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A 0.6 A1 0.22 0.18 A2 0.38 0.34 b 0.30 0.26 D 2.27 2.21 E 2.24 0.4 2.18 1.6 1.6 0.105 0.09 0.01 0.04 0.03 e e1 e2 e3 e4 v w y
OUTLINE VERSION ISP1512xUK
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 08-07-03 08-07-08
Fig 17. Package outline ISP1512xUK (WLCSP25)
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ULPI HS USB transceiver
17. Soldering of WLCSP packages
17.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note AN10439 "Wafer Level Chip Scale Package" and in application note AN10365 "Surface mount reflow soldering description". Wave soldering is not suitable for this package. All NXP WLCSP packages are lead-free.
17.2 Board mounting
Board mounting of a WLCSP requires several steps: 1. Solder paste printing on the PCB 2. Component placement with a pick and place machine 3. The reflow soldering itself
17.3 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a PbSn process, thus reducing the process window
* Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 55
Table 55. Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 18.
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ULPI HS USB transceiver
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365 "Surface mount reflow soldering description".
17.3.1 Stand off
The stand off between the substrate and the chip is determined by:
* The amount of printed solder on the substrate * The size of the solder land on the substrate * The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal Expansion Coefficient) differences between substrate and chip.
17.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. The surface of the joint should be smooth and the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps after reflow can occur during the reflow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. No failures have been found to be related to these voids. Solder joint inspection after reflow can be done with X-ray to monitor defects such as bridging, open circuits and voids.
17.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip. If a chip is removed from the substrate, most solder balls of the chip will be damaged. In that case it is recommended not to re-use the chip again.
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Device removal can be done when the substrate is heated until it is certain that all solder joints are molten. The chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. Removing the device must be done using plastic tweezers, because metal tweezers can damage the silicon. The surface of the substrate should be carefully cleaned and all solder and flux residues and/or underfill removed. When a new chip is placed on the substrate, use the flux process instead of solder on the solder lands. Apply flux on the bumps at the chip side as well as on the solder pads on the substrate. Place and align the new chip while viewing with a microscope. To reflow the solder, use the solder profile shown in application note AN10365 "Surface mount reflow soldering description".
17.3.4 Cleaning
Cleaning can be done after reflow soldering.
18. Abbreviations
Table 56. Acronym ASIC ATX CDM EMI ESD ESR FPGA HBM IEC MM NRZI OTG PDA PHY PID PLL POR RoHS RXCMD RXD SDR SE0 SOC SRP SYNC TTL TXCMD
ISP1512A_1
Abbreviations Description Application-Specific Integrated Circuit Analog USB Transceiver Charge Device Model ElectroMagnetic Interference ElectroStatic Discharge Effective Series Resistance Field Programmable Gate-Array Human Body Model International Electrotechnical Commission Machine Model Non-Return-to-Zero Inverted On-The-Go Personal Digital Assistant Physical Packet Identifier Phase-Locked Loop Power-On Reset Restriction of Hazardous Substances Receive Command Receive Data Single Data Rate Single-Ended Zero System-On-Chip Session Request Protocol Synchronous Transistor-Transistor Logic Transmit Command
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Abbreviations ...continued Description Transmit Data Universal Asynchronous Receiver-Transmitter UTMI+ Low Pin Interface Universal Serial Bus USB Implementers Forum USB Transceiver Macrocell Interface USB Transceiver Macrocell Interface Plus Wafer-Level Chip-Scale Package
Table 56. Acronym TXD UART ULPI USB USB-IF UTMI UTMI+ WLCSP
19. Glossary
A-device -- An OTG device with an attached micro-A plug. B-device -- An OTG device with an attached micro-B plug. Link -- ASIC, SOC or FPGA that contains the USB host or peripheral core. PHY -- Physical layer containing USB transceiver.
20. References
[1] [2] [3] [4] [5] [6] [7] [8] Universal Serial Bus Specification Rev. 2.0 On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 UTMI+ Specification Rev. 1.0 USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) (JESD22-A114D) Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) (JESD22-A115-A) Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components (JESD22-C101-C) Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test (IEC 61000-4-2)
[9]
21. Revision history
Table 57. Revision history Release date 20080731 Data sheet status Preliminary data sheet Change notice Supersedes Document ID ISP1512A_1
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22. Legal information
22.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
22.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
23. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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ULPI HS USB transceiver
24. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Recommended VBUS capacitor value . . . . . . .11 External capacitor values for 19.2 MHz clock frequency . . . . . . . . . . . . . . . . . . . . . . . .12 Pin states in power-down mode . . . . . . . . . . . .13 ULPI signal description . . . . . . . . . . . . . . . . . .14 Signal mapping during low-power mode . . . . .15 Signal mapping for 6-pin serial mode . . . . . . .16 Signal mapping for 3-pin serial mode . . . . . . .17 UART signal mapping . . . . . . . . . . . . . . . . . . .17 Operating states and their corresponding resistor settings . . . . . . . . . . . . . . . . . . . . . . . .21 Register map . . . . . . . . . . . . . . . . . . . . . . . . . .23 VENDOR_ID_LOW - Vendor ID Low register (address R = 00h) bit description . . . .23 VENDOR_ID_HIGH - Vendor ID High register (address R = 01h) bit description . . . .23 PRODUCT_ID_LOW - Product ID Low register (address R = 02h) bit description . . . .24 PRODUCT_ID_HIGH - Product ID High register (address R = 03h) bit description . . . .24 FUNC_CTRL - Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation . . . . . . . . . . . . . . . . . . .24 FUNC_CTRL - Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description . . . . . . . . . . . . . . . . . .25 INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation . . . . . . . . . . . . . . . . . . .25 INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description . . . . . . . . . . . . . . . . . .26 OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation . . . . . . . . . . . . . . . . . . .26 OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description . . . . . . . . . . . . . . . . . .27 USB_INTR_EN_R - USB Interrupt Enable Rising register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit allocation . . . .27 USB_INTR_EN_R - USB Interrupt Enable Rising register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit description . .27 USB_INTR_EN_F - USB Interrupt Enable Falling register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit allocation . . . .28 USB_INTR_EN_F - USB Interrupt Enable Falling register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit description . . .28 USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation . . . . .28 USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit description . . . . 28 Table 30. USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit allocation . . . . . 29 Table 31. USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description . . . . 29 Table 32. DEBUG - Debug register (address R = 15h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 33. DEBUG - Debug register (address R = 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 34. SCRATCH - Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 35. CARKIT_CTRL - Carkit Control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit allocation . . . . . . . . . . . . . . . . . . . 30 Table 36. CARKIT_CTRL - Carkit Control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit description . . . . . . . . . . . . . . . . . . 30 Table 37. PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation . . . . . . . . . . . . . . . . . . . 30 Table 38. PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description . . . . . . . . . . . . . . . . . . 31 Table 39. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 40. Recommended operating conditions . . . . . . . . 32 Table 41. Static characteristics: supply pins . . . . . . . . . . 33 Table 42. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL) . . . . . . 33 Table 43. Static characteristics: analog pins (DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 44. Static characteristics: analog pin VBUS . . . . . . 35 Table 45. Static characteristics: resistor reference . . . . . 36 Table 46. Static characteristics: pin XTAL1 . . . . . . . . . . . 36 Table 47. Dynamic characteristics: reset and power . . . . 37 Table 48. Dynamic characteristics: clock applied to XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 49. Dynamic characteristics: CLOCK output . . . . . 37 Table 50. Dynamic characteristics: digital I/O pins . . . . . 38 Table 51. Dynamic characteristics: analog I/O pins (DP, DM) in USB mode . . . . . . . . . . . . . . . . . . 38 Table 52. Dynamic characteristics: analog I/O pins (DP, DM) in transparent UART mode . . . . . . . 38 Table 53. Dynamic characteristics: analog I/O pins (DP, DM) in serial mode . . . . . . . . . . . . . . . . . 39 Table 54. Recommended bill of materials . . . . . . . . . . . . 42 Table 55. Lead-free process (from J-STD-020C) . . . . . . 47 Table 56. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 57. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28. Table 29.
ISP1512A_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 31 July 2008
52 of 55
NXP Semiconductors
ISP1512A
ULPI HS USB transceiver
25. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .5 Internal power-on reset timing . . . . . . . . . . . . . . .10 Internal circuit of the VBUS pin . . . . . . . . . . . . . . .11 Interface behavior when entering UART mode and the clock is powered down . . . . . . . . .19 Interface behavior when entering UART mode and the clock remains powered . . . . . . . . .19 Interface behavior when exiting UART mode and the clock is not running . . . . . . . . . . . .20 Interface behavior when exiting UART mode and the clock is running . . . . . . . . . . . . . . .20 Rise time and fall time . . . . . . . . . . . . . . . . . . . . .40 Timing of TX_DAT and TX_SE0 to DP and DM . .40 Timing of TX_ENABLE to DP and DM. . . . . . . . .40 Timing of DP and DM to RX_RCV, RX_DP and RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 ULPI timing interface . . . . . . . . . . . . . . . . . . . . . .41 Using the ISP1512A with a standard USB peripheral controller . . . . . . . . . . . . . . . . . . . . . . .43 Using the ISP1512A with a standard USB host controller . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Using the ISP1512A with a standard USB OTG controller . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Package outline ISP1512xUK (WLCSP25) . . . . .46 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
ISP1512A_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 31 July 2008
53 of 55
NXP Semiconductors
ISP1512A
ULPI HS USB transceiver
26. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.7.1 8.7.1.1 8.7.1.2 8.7.1.3 8.7.2 8.8 8.9 8.10 8.10.1 8.10.2 8.10.3 8.10.4 8.10.5 8.10.6 8.10.7 8.10.8 8.10.9 8.10.10 8.10.11 8.10.12 8.10.13 8.10.14 9 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 ULPI interface controller . . . . . . . . . . . . . . . . . . 7 USB serializer and deserializer. . . . . . . . . . . . . 7 Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 7 Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . 8 Crystal oscillator and PLL. . . . . . . . . . . . . . . . . 8 UART buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VBUS comparators. . . . . . . . . . . . . . . . . . . . . . . 9 VBUS valid comparator . . . . . . . . . . . . . . . . . . . 9 Session valid comparator . . . . . . . . . . . . . . . . . 9 Session end comparator. . . . . . . . . . . . . . . . . . 9 SRP charge and discharge resistors . . . . . . . . 9 Band gap reference voltage . . . . . . . . . . . . . . . 9 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 9 Detailed description of pins . . . . . . . . . . . . . . 10 DATA[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VCC(I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 RREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 REG3V3 and REG1V8 . . . . . . . . . . . . . . . . . . 11 XTAL1 and XTAL2. . . . . . . . . . . . . . . . . . . . . . 11 CHIP_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 NXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Modes of operation . . . . . . . . . . . . . . . . . . . . . 13 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-down mode . . . . . . . . . . . . . . . . . . . . . 13 ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Synchronous mode. . . . . . . . . . . . . . . . . . . . . 14 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 15 9.2.3 9.2.4 9.2.5 9.3 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 11 12 13 14 15 16 17 17.1 17.2 17.3 17.3.1 17.3.2 17.3.3 17.3.4 18 19 20 21 22 22.1 22.2 22.3 22.4 23 24 6-pin full-speed or low-speed serial mode . . . 3-pin full-speed or low-speed serial mode . . . Transparent UART mode . . . . . . . . . . . . . . . . USB state transitions . . . . . . . . . . . . . . . . . . . Register map . . . . . . . . . . . . . . . . . . . . . . . . . . VENDOR_ID_LOW register . . . . . . . . . . . . . . VENDOR_ID_HIGH register . . . . . . . . . . . . . PRODUCT_ID_LOW register. . . . . . . . . . . . . PRODUCT_ID_HIGH register . . . . . . . . . . . . FUNC_CTRL register. . . . . . . . . . . . . . . . . . . INTF_CTRL register. . . . . . . . . . . . . . . . . . . . OTG_CTRL register . . . . . . . . . . . . . . . . . . . . USB_INTR_EN_R register. . . . . . . . . . . . . . . USB_INTR_EN_F register . . . . . . . . . . . . . . . USB_INTR_STAT register . . . . . . . . . . . . . . . USB_INTR_L register . . . . . . . . . . . . . . . . . . DEBUG register . . . . . . . . . . . . . . . . . . . . . . . SCRATCH register . . . . . . . . . . . . . . . . . . . . . CARKIT_CTRL register . . . . . . . . . . . . . . . . . PWR_CTRL register . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering of WLCSP packages . . . . . . . . . . . Introduction to soldering WLCSP packages. . Board mounting . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Stand off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality of solder joint . . . . . . . . . . . . . . . . . . . Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 20 23 23 23 24 24 24 25 26 27 28 28 29 29 30 30 30 32 32 33 37 42 46 47 47 47 47 48 48 48 49 49 50 50 50 51 51 51 51 51 51 52
continued >>
ISP1512A_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 31 July 2008
54 of 55
NXP Semiconductors
ISP1512A
ULPI HS USB transceiver
25 26
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 31 July 2008 Document identifier: ISP1512A_1

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