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RDC (R) R1122 RISC DSP Communication 16-BIT RISC MICROCONTROLLER 16-BIT RISC MICROCONTROLLER R1122 Brief Sheet Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 5 REV 1.0 Jun.05 2006 RDC(R) 1. Features l l l l R1122 RISC DSP Communication 16-BIT RISC MICROCONTROLLER Five-stage pipeline RISC architecture Integrated PLL (*1~*8) Maximum frequency: 80 MHz; the external bus, internal bus and core are operating in the same clock base l Three independent 16-bit timers and one independent watchdog timer l The Interrupt controller with seven maskable external interrupts and one non-maskable external interrupt l Two independent DMA channels l Programmable chip-select logic for memory or I/O bus cycle decoder l Programmable wait-state generators l The I/O pin output is 3.3 volt level and the input 3.3 to 5 volt tolerance. l 3.3V operation voltage l Supports serial port/ DMA transfers l With 8-bit or 16-bit boot ROM bus size l l A green product Package Type - PQFP100 pins & LQFP100 pins l l Static & synthesizable design Bus interface - A multiplexed address and data bus which is compatible with the 80C186 microprocessor - Supports a direct address bus A[19:0] - 1M-byte memory address space - 64K-byte I/O space l l l Software is compatible with the 80C186 microprocessor Supports two asynchronous serial channels with hardware handshaking signals Supports CPU ID l Supports 32 PIO pins Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 5 REV 1.0 Jun.05 2006 RDC(R) R1122 RISC DSP Communication 16-BIT RISC MICROCONTROLLER 2. Block Diagram INT2/INTA0_n INT1/SELECT_n CLKOUTA INT3/INTA1_n/IRQ CLKOUTB INT6~4 INT0 NMI TMROUT0 TMROUT1 TMRIN0 TMRIN1 DRQ0 DRQ1 X1 VCC GND X2 Clock and Power Management Interrupt Control Unit Timer Control Unit DMA Unit RST_n LCS_n/ONCE0_n MCS3_n/RFSH_n MCS[2:0] UCS_n/ONCE1_n PCS3_n~PCS0_n PCS5_n/A1 PCS6_n/A2 Chip Select Unit PSRAM Control Unit Instruction Queue (64bits) Instruction Decoder Control Signal Micro ROM PIO Unit PIO[31:0] ARDY SRDY S2_n~S0_n DT/R_n DEN_n Refresh Control Unit Register File General, Segment, Eflag Register EA / LA Address Asynchronous Serial Port0 RTS0_n/RTR0_n CTS0_n/ENRX0_n TXD0 RXD0 RTS1_n/RTR1_n HOLD HLDA S6/CLKDIV2_n UZI_n Bus Interface Unit ALU (Special, Logic, Adder, BSF) Execution Unit Asynchronous Serial Port1 CTS1_n/ENRX1_n TXD1 RXD1 A[19:0] AD[7:0] RD_n WB_n WR_n ALE AO[15:8] RFSH2_n/ADEN_n Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 5 REV 1.0 Jun.05 2006 RDC(R) 3. R1122 RISC DSP Communication 16-BIT RISC MICROCONTROLLER Package Information PQFP 100 pins D 23.20 0.20 0.10 D1 20.00 "A" 0.10 E1 14.00 SEATING PLANE 0.25 MIN A1 0.25 DETAIL A 0.10 c 0.25~0.38 3.40 Max. "A" 0.65 BSC DETAIL A 1.60 REF L1 A2 2.85 0.12 L 0.88 0.15 15 TYP 7 TYP UNIT:mm Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 5 REV 1.0 Jun.05 2006 E 17.20 0.20 RDC(R) R1122 RISC DSP Communication 16-BIT RISC MICROCONTROLLER LQFP 100 pins 16.00 14.00 0.15 0.10 100 76 1 75 0.10 14.00 25 51 26 50 0.127(TYP) 0.50(TYP) Sealing Plane 0.22 0.05 "A" 0.08(MAX) 1.60(MAX) 0.05 0~7 0.05 0.60 1.00(REF) 0.10 Specifications subject to change without notice, contact your sales representatives for the most update information. Page 5 of 5 REV 1.0 Jun.05 2006 0.2S(TYP) GAUGE PLANE 1.40 0.15 UNIT:mm 16.00 0.15 |
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