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| Product Specification PE42650A Product Description The following specification defines an SP3T (single pole three throw) switch for use in cellular and other wireless applications. It has both a standard and attenuated RX mode. The PE42650A uses Peregrine's UltraCMOSTM process and also features HaRPTM technology enhancements to deliver high linearity and exceptional harmonics performance. HaRPTM technology is an innovative feature of the UltraCMOSTM process providing upgraded linearity performance. The PE42650A is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. SP3T High Power UltraCMOSTM RF Switch 30 MHz - 1000 MHz Features * 50 Watt P1dB compression point * 10 Watts <8:1 VSWR (Normal Operation) * 38 dB TX-RX Isolation * 2fo and 3fo < -81 dBc @10 Watts * ESD rugged to 2.0 kV HBM * No blocking capacitors required * 32-lead 5x5 mm QFN package Figure 1. Functional Diagram Figure 2. Package Type 32-lead 5x5 mm QFN TX1 ESD ANT ESD TX2 RX ESD CMOS Control Driver and ESD CTRL Document No. 70-0267-02 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE42650A Product Specification Table 1: Electrical Specifications @ +25 C, VDD = 3.3 V (ZS = ZL = 50 ) unless otherwise noted Parameter TX Insertion Loss 1 Conditions 30 MHz 1 GHz 30 MHz 1 GHz 800 MHz 800 MHz, 50% duty cycle 800 MHz 800 MHz 800 MHz, +27 dBm 800 MHz, +27 dBm Un-Attenuated State, 800 MHz Min Typ 0.3 0.5 14.5 45.4 Max 0.5 0.9 16 Units dB dB dB dBm dB dB dB dB dB dB dB RX Insertion Loss (Un-Attenuated State)1 RX Insertion Loss (Attenuated State)1 0.1 dB Input Compression Point Isolation (Supply Biased): TX-TX Isolation (Supply Biased): TX-RX Unbiased Isolation: ANT - TX, VDD, V1, V2, V3=0 V Unbiased Isolation: ANT - RX, VDD, V1, V2, V3=0 V RX Port Return Loss1 TX and ANT Port Return Loss1 TX, 2nd Harmonic TX, 3rd Harmonic RX IIP3 Switching Time 13 30 35 6 14 18 12 20 33 38 10 22 22 18 23 -81 -81 -79 -79 Attenuated State, with external matching inductor optimized without attenuator engaged, 800 MHz 800 MHz 800 MHz @ 42.5 dBm 800 MHz @ 42.5 dBm Un-Attenuated State, 800 MHz, 150 kHz tone separation 50% of CTRL to 10/90% of RF dBc dBc dBm 30 0.1 0.5 ms Note: 1. The device was matched with ~4 nH inductance per RF port. RX port may not need matching inductor. Table 2. Operating Ranges Parameter Frequency Range TX Input Power1 (VSWR 8:1) RX Input Power 2 (VSWR 8:1) VDD Power Supply Voltage IDD Power Supply Current Control Voltage High Control Voltage Low TOP Operating temperature range (Case) Tj Operating junction temperature Notes: 1. Supply biased 2. Supply biased or unbiased -40 1.4 0.4 85 3.2 3.3 90 Table 3. Absolute Maximum Ratings Typ Max 1000 40 27 3.4 170 Min 30 Units MHz dBm dBm V uA V V C C Symbol VDD VI TST Parameter/Conditions Power supply voltage Voltage on any DC input Storage temperature range Maximum case temperature Peak maximum junction temperature (10 seconds max) TX Input Power1 (VSWR 20:1, 10 seconds) TX Input Power1 (50 ) RX Input Power at ANT pin2 (VSWR 20:1) RF Input Power on inactive ports or supply unbiased Min Max Units -0.3 -0.3 -65 4 VDD+ 0.3 150 85 200 40 45 27 27 2.8 2000 V V C C C dBm dBm dBm dBm W V TCASE Tj PIN 140 PD VESD Maximum Power Dissipation from RF Insertion Loss ESD Voltage (HBM, MIL_STD 883 Method 3015.7) Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE42650A in the 5x5 QFN package is MSL3. Notes: 1. Supply biased 2. Supply biased or unbiased Absolute Maximum Ratings Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11 Document No. 70-0267-02 UltraCMOSTM RFIC Solutions PE42650A Product Specification Figure 3. Pin Configuration (Top View) 32 GND 31 GND 30 GND 29 GND 27 GND 26 GND 25 GND 28 ANT Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. GND TX1 GND TX1 GND GND GND RX 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9 24 GND 23 TX2 22 GND Exposed Ground Paddle 21 TX2 20 GND 19 GND 18 GND 17 GND Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Table 5. Control Logic Truth Table Path ANT - RX Attenuated Unsupported mode Unsupported mode V3 V2 GND GND Vdd N/C V1 N/C V3 L L L L H H H H V2 L L H H L L H H V1 L H L H L H L H Table 4. Pin Descriptions Pin No. 1 2 3 4 5-7 8 9-10 11 12 13 14 15 16 17-20 21 22 23 24-27 28 29-32 Paddle Pin Name GND TX1 GND TX11 GND RX GND N/C VDD V3 V2 V12 N/C GND TX2 GND TX23 GND ANT GND GND Ground TX1 port Ground TX1 port Ground RX port Ground Description ANT - TX1 ANT - RX Unsupported mode Unsupported mode ANT - TX2 No Connect Nominal 3.3 V supply connection Control Control Control Do not connect Ground TX2 port Ground TX2 port Ground Antenna Port Ground Exposed ground paddle Note: 1. Must be tied to pin 2 2. Must be tied to V2 3. Must be tied to pin 21 Document No. 70-0267-02 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11 PE42650A Product Specification Evaluation Kit The PE42650A Evaluation Kit board was designed to ease customer evaluation of the PE42650A RF switch. DC power is supplied through J10, with VDD on pin 9, and GND on the entire lower row of even numbered pins. To evaluate a switch path, add or remove jumpers on V1 (pin 3), V2 (pin 5), and V3 (pin 7) using Table 5 (adding a jumper pulls the CMOS control pin low and removing it allows the on-board pull-up resistor to set the CMOS control pin high). J10 pins 1, 11, and 13 are N/C. The RF common port (ANT) is connected through a 50 Ohm transmission line via the top SMA connector, J1. RX and TX paths are also connected through 50 Ohm transmission lines via SMA connectors. A 50 Ohm through transmission line is available via SMA connectors J8 and J9. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. An open-ended 50 Ohm transmission line is also provided at J7 for calibration if needed. Narrow trace widths are used near each part to improve impedance matching. Figure 4. Evaluation Board Layout Peregrine Specification 101-0315 Figure 5. Evaluation Board Schematic Peregrine Specification 102-0535 (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11 Document No. 70-0267-02 UltraCMOSTM RFIC Solutions PE42650A Product Specification Performance Plots Figure 6. Isolation, Tx-Tx, VDD=3.3V Figure 8. Isolation, Tx-Tx, +25C Figure 7. Isolation, Tx-Rx, VDD=3.3V Figure 9. Isolation, Tx-Rx, +25C Document No. 70-0267-02 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 11 PE42650A Product Specification Figure 10. Tx Insertion Loss, VDD=3.3V Figure 13. Tx Insertion Loss, +25C Figure 11. Rx Insertion Loss Un-Attenuated, VDD=3.3V Figure 14. Rx Insertion Loss Un-Attenuated, +25C Figure 12. Rx Insertion Loss Attenuated, VDD=3.3V Figure 15. Rx Insertion Loss Attenuated, +25C (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11 Document No. 70-0267-02 UltraCMOSTM RFIC Solutions PE42650A Product Specification Figure 16. Return Loss, VDD=3.3V Figure 18. Return Loss, +25C Figure 17. Tx Return Loss, VDD=3.3V Figure 19. Tx Return Loss, +25C Document No. 70-0267-02 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 11 PE42650A Product Specification Figure 20. Rx Return Loss Attenuated, VDD=3.3V Figure 22. Rx Return Loss Attenuated, +25C Figure 21. Rx Return Loss Un-Attenuated, VDD=3.3V Figure 23. Rx Return Loss Un-Attenuated, +25C (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11 Document No. 70-0267-02 UltraCMOSTM RFIC Solutions PE42650A Product Specification Thermal Data Though the insertion loss for this part is very low, when handling high power RF signals, the part can get quite hot. Power Dissipated (W) Figure 24. Power Dissipation 3.0 1:1 VSWR (50 OhmLoad) Figure 24 shows the estimated power dissipation for a given incident RF power level. Multiple curves are presented to show the effect of poor VSWR conditions. VSWR conditions that present short circuit loads to the part can cause significantly more power dissipation than with proper matching. Figure 25 shows the estimated maximum junction temperature of the part for similar conditions. Note that both of these charts assume that the case (GND slug) temperature is held at 85C. Special consideration needs to be made in the design of the PCB to properly dissipate the heat away from the part and maintain the 85C maximum case temperature. It is recommended to use best design practices for high power QFN packages: multi-layer PCBs with thermal vias in a thermal pad soldered to the slug of the package. Special care also needs to be made to alleviate solder voiding under the part. 2.5 2:1 VSWR (25 OhmLoad) 8:1 VSWR (6.25 OhmLoad) 20:1 VSWR (2.5 OhmLoad) 2.0 INF:1 VSWR (0 OhmLoad) Reliabil ity Limit 1 .5 1 .0 0.5 0.0 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 RF Power (dBm) Figure 25. Maximum Junction Temperature 1 45 Max Junction Temperature (C) 1 40 1 35 1:1 VSWR (50 OhmLoad) Table 6. Theta JC Parameter Theta JC (+85C) 1 30 1 25 1 20 15 1 10 1 1 05 1 00 95 90 85 30 31 2:1 VSWR (25 OhmLoad) 8:1 VSWR (6.25 OhmLoad) 20:1 VSWR (2.5 OhmLoad) INF:1 VSWR (0 OhmLoad) Reliabil ity Limit Min Typ 15 Max Units C/W 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 RF Power (dBm) Document No. 70-0267-02 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 11 PE42650A Product Specification Figure 26. Package Drawing See Note below Note: Not for electrical connection. Corner detail is tied to paddle and should not be isolated on PCB board. Figure 27. Tape and Reel Specs Pin 1 Top of Device Tape Feed Direction Device Orientation in Tape Table 7. Ordering Information Order Code PE42650AMLI-Z PE42650AMLI EK42650A-01 Part Marking 42650A 42650A 42650A Description Parts on Tape and Reel Parts in Tubes or Cut Tape Evaluation Kit Package Green 32-lead 5x5mm QFN Green 32-lead 5x5mm QFN Evaluation Kit Document No. 70-0267-02 Shipping Method 3000 units / T&R 73 units / Tube 1 / Box UltraCMOSTM RFIC Solutions (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11 PE42650A Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Europe Peregrine Semiconductor Europe Batiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 High-Reliability and Defense Products Americas San Diego, CA, USA Phone: 858-731-9475 Fax: 848-731-9499 Europe/Asia-Pacific Aix-En-Provence Cedex 3, France Phone: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 11 Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0267-02 www.psemi.com |
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