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TDA7342EQ2N
Digitally controlled audio processor
Features
Input multiplexer - Two stereo and one mono inputs - One quasi differential input - Selectable input gain for optimal adaptation to different sources Fully programmable loudness function Volume control in 0.3dB steps including gain up to 20dB Zero crossing mute, soft mute and direct mute Bass and treble control Four speaker attenuators - Four independent speakers control in 1.25dB steps for balance and fader facilities - Independent mute function All functions programmable via serial I2C bus Due to a highly linear signal processing, using CMOS-switching techniques instead of standard bipolar multipliers, very low distortion and very low noise are obtained. Several new features like softmute, and zero-crossing mute are implemented. The soft Mute function can be activated in two ways: 1. 2. Via serial bus (Mute byte, bit D0) Directly on pin 21 through an I/O line of the microcontroller
TQFP32

Description
The audioprocessor TDA7342EQ2N is an upgrade of the TDA731X audioprocessor family.
Very low DC stepping is obtained by use of a BICMOS technology.
Order codes
Part number TDA7342EQ2N TDA7342EQ2NTR Package TQFP32 TQFP32 Packing Tray Tape and reel
August 2006
Rev 1
1/21
www.st.com 1
Contents
TDA7342EQ2N
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pns description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 3.3 3.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 4.2 4.3 4.4 4.5 Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Transmission without Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 5.2 5.3 5.4 Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
TDA7342EQ2N
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SUBADDRESS (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/21
List of figures
TDA7342EQ2N
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Validity on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timing Diagram of I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Acknowledge on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TQFP32 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4/21
1
Figure 1.
TDA7342EQ2N
C9 C14 BIN(L) 17 SPKR ATT 24 MUTE ZERO CROSS + MUTE LOUD+ VOL BASS TREBLE L3 22 MUTE OUT LEFT REAR 29 27 SOFT MUTE SERIAL BUS DECODER + LATCHES 26 25 SPKR ATT R3 23 M R2 R1 ZERO CROSS + MUTE LOUD+ VOL MUTE BASS TREBLE ADDR SCL SDA DIGGND 32 TREBLE(L) C15
R2 4.7K 100nF 100nF C17 2.7nF
OUT(L) 16 15 9 18
Block diagram
IN(L)
LOUD(L)
C11 47nF BOUT(L)
Block diagram
C1 L1 L2 M SPKR ATT
L1
13
OUT LEFT FRONT
LEFT INPUTS
L2
12
C2
C6
L3
11
CD
+Vcc
SGND INPUT SELECTOR + GAIN
10
C3
BUS
C7
R3
5
MONO INPUT
M
8
OUT RIGHT FRONT
R2
6
RIGHT INPUTS
C4
R1
7
SPKR ATT 21 MUTE OUT RIGHT REAR 4 LOUD(R) C10 47nF C8 14 CSM CSM 47nF 20 19 BOUT(R) C12 100nF R1 100nF 4.7K 1 BIN(R) C13 TREBLE(R)
D93AU043B
C5
SUPPLY
30 CREF 10F OUT(R) IN(R)
31
28
3
2
VS
Block diagram
C16 2.7nF
5/21
Pns description
TDA7342EQ2N
2
Pns description
Figure 2. Pin connection (Top view)
DIG GND 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 LOUD L CD GND OUT L IN L3 IN L2 IN L1 CSM IN L
ADDR
CREF
GND
TR L
32 31 30 29 28 27 26 25 TR R IN R OUT R LOUD R IN R3 IN R2 IN R1 MONO 1 2 3 4 5 6 7 8 OUT LF OUT RF OUT LR OUT RR BOUT R BIN R BOUT L BIN L
VS
SDA
SCL
D94AU060A
6/21
TDA7342EQ2N
Electrical specifications
3
3.1
Electrical specifications
Absolute maximum ratings
Table 1.
Symbol VS Tamb Tstg
Absolute Maximum Ratings
Parameter Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Value 10.5 -40 to 85 -55 to 150 Unit V C C
3.2
Quick reference data
Table 2.
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation Volume Control 0.3dB step Treble Control 2dB step Bass Control 2dB step Fader and Balance Control 1.25dB step Input Gain 3.75dB step Mute Attenuation -59.7 -14 -10 -38.75 0 100
Quick reference data
Parameter Min. 6 2.1 Typ. 9 2.6 0.01 106 100 20 +14 +18 0 11.25 0.08 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB dB dB
3.3
Thermal data
Table 3.
Symbol Rth j-amb
Thermal data
Parameter Thermal Resistance Junction-pins Value 150 Unit C/W
7/21
Electrical specifications
TDA7342EQ2N
3.4
Table 4.
Electrical characteristics
Electrical characteristics (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Parameter Test Condition Min. Typ. Max. Unit
Symbol INPUT SELECTOR RI VCL SI RL GI MIN GI MAX Gstep eN VDC
Input Resistance Clipping Level Input Separation Output Load Resistance Minimum Input Gain Maximum Input Gain Step Resolution Input Noise DC Steps GIINto GIMAX 20Hz to 20 KHz unweighted Adiacent Gain Steps d 0.3%
70 2.1 80 2 -0.75 10.25 2.75
100 2.6 100
130
K VRMS dB K
0 11.25 3.75 2.3 1.5 3
0.75 12.25 4.75
dB dB dB V
10
mV mV
DIFFERENTIAL INPUT ( IN 3) Input selector BIT D6 = 0 (0dB) RI Input Resistance Input selector BIT D6 = 1(-6dB) Common Mode Rejection Ratio Distortion Input Noise Differential Gain D6 = 1 -7 -6 -5 dB VCM = 1VRMS; f =1KHz f = 10KHz d
eIN
10 14 48 45
15 20 75 70 0.01 5
20 30
K K dB dB
CMRR
VI= 1VRMS 20Hz to 20KHz; Flat; D6 = 0 D6 = 0 -1
0.08
% V
0
1
dB
GDIFF
VOLUME CONTROL RI GMAX AMAX ASTEPC ASTEPF EA Et VDC Input Resistance Maximum Gain Maximum Attenuation Step Resolution Coarse Atten. Step Resolution Fine Attenuation G = 20 to -20dB Attenuation Set Error G = -20 to -58dB Tracking Error Adiacent Attenuation Steps DC Steps From 0dB to AMAX 0.5 5 mV -3 0 -3 2 2 3 dB dB mV 35 18.75 57.7 0.5 0.11 -1.25 50 20 59.7 1.25 0.31 0 21.25 62.7 2.0 0.51 1.25 K dB dB dB dB dB
8/21
TDA7342EQ2N Table 4.
Electrical specifications
Electrical characteristics (continued) (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Parameter Test Condition Min. Typ. Max. Unit
Symbol
LOUDNESS CONTROL RI AMAX Astep Internal Resistor Maximum Attenuation Step Resolution Loud = On 35 17.5 0.5 50 18.75 1.25 65 20.0 2.0 K dB dB
ZERO CROSSING MUTE WIN = 11 VTH Zero Crossing Threshold (1) WIN = 10 WIN = 01 WIN = 00 AMUTE VDC Mute Attenuation DC Step 0dB to Mute 80 20 40 80 160 100 0 3 mV mV mV mV dB mV
SOFT MUTE AMUTE TDON Mute Attenuation ON Delay Time CCSM = 22nF; 0 to -20dB; I = IMAX CCSM = 22nF; 0 to -20dB; I = IMIN OFF Current Soft Mute Threshold (pin 14) VCSM= 0V; I = IMAX VCSM= 0V; I = IMIN 1.5 45 0.7 20 25 60 1 35 50 1 2.5 3.5 1.7 55 75 dB ms ms A A V
IDOFF VTHSM
BASS CONTROL BBOOST BCUT Astep Rg Max Bass Boost Max Bass Cut Step Resolution Internal Feedback Resistance 15 -8.5 1 45 18 -10 2 65 20 -11.5 3 85 dB dB dB K
TREBLE CONTROL CRANGE Control Range Astep Step Resolution 13 1 14 2 15 3 dB dB
SPEAKER ATTENUATORS CRANGE Control Range Astep AMUTE EA VDC Step Resolution Output Mute Attenuation Attenuation Set Error DC Steps Adjacent Attenuation Steps 0 Data Word = XXX11111 35 0.5 80 37.5 1.25 100 1.25 3 40 2.00 dB dB dB dB mV
9/21
Electrical specifications Table 4.
TDA7342EQ2N
Electrical characteristics (continued) (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Parameter Test Condition Min. Typ. Max. Unit
Symbol AUDIO OUTPUT Vclip RL RO VDC
Clipping Level Output Load Resistance Output Impedance DC Voltage Level
d = 0.3%
2.1 2
2.6
Vrms K
30 3.5 3.8
100 4.1
V
GENERAL VCC ICC PSRR Supply Voltage Supply Current f = 1KHz Power Supply Rejection Ratio B = 20 to 20kHz "A" weighted Output Muted (B = 20 to 20kHz flat) eNO Output Noise All Gains 0dB (B = 20 to 20kHz flat) Total Tracking Error Signal to Noise Ratio Channel Separation Distortion VIN =1V AV= 0 to -20dB AV= -20 to -60dB All Gains = 0dB; VO= 1Vrms 80 5 0 0 106 100 0.01 0.08 15 1 2 V dB dB dB dB % 65 2.5 dB V 6 5 60 9 10 80 10.2 15 V mA dB
Et S/N SC d
BUS INPUTS VIL VlN IlN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge VIN = 0.4V IO= 1.6mA 3 -5 0.4 5 0.8 1 V V A V
1. WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold.
10/21
TDA7342EQ2N
I2C bus interface
4
I2C bus interface
Data transmission from microprocessor to the TDA7342EQ2N and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected).
4.1
Data Validity
As shown in Figure 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2
Start and Stop Conditions
As shown in Figure 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition.
4.3
Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
4.4
Acknowledge
The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.
4.5
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
11/21
I2C bus interface Figure 3. Data Validity on the I2C BUS
SDA
TDA7342EQ2N
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 4.
Timing Diagram of I2C BUS
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 5.
Acknowledge on the I2C BUS
SCL
1
2
3
7
8
9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
Patent note:
Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
12/21
TDA7342EQ2N
Software specification
5
5.1
Software specification
Interface Protocol
The interface protocol comprises:

A start condition (s) A chip address byte, (the LSB bit determines read/write transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
CHIP ADDRESS MSB LSB 0 0 0 1 0 A R/W ACK MSB X X X I SUBADDRESS LSB A3 A2 A1 A0 ACK MSB DATA DATA 1 ... DATA n LSB ACK P
S
1
D06AU1650
ACK = Acknowledge S P I X A = Start = Stop = Auto Increment = Not used = I2C address value selectable according to ADDR pin status ADDR = Open/Gnd A = O ADDR = VCC A=I
MAX CLOCK SPEED 500kbits/s
5.2
Auto increment
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled Table 5.
MSB X X X I A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0
SUBADDRESS (receive mode)
LSB A0 0 1 0 1 0 1 0 1 0 Input Selector Loudness Volume Bass, Treble Speaker Attenuator LF Speaker Attenuator LR Speaker Attenuator RF Speaker Attenuator RR Mute Function
13/21
Software specification
TDA7342EQ2N
5.3
Transmitted data
Table 6.
MSB X X X X X SM ZM
Send mode
LSB X
ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chip address.
5.4
Data byte specification
X = not relevant; set to "1" during testing Table 7.
MSB D7 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D6 D5 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1
Input selector
LSB FUNCTION D0 0 1 0 1 0 1 0 1 not used IN 2 IN 1 AM mono not used not used not allowed not allowed 11.25dB gain 7.5dB gain 3.75dB gain 0dB gain 0dB differential input gain (IN3) -6dB differential input gain (IN3)
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
14/21
TDA7342EQ2N Table 8.
MSB D7 X X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X X D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1
Software specification Loudness
LSB FUNCTION D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D0 0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB -10dB -11.25dB -12.5dB -13.75dB -15dB -16.25dB -17.5dB -18.75dB Loudness OFF (1)
1. If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat frequency response. D0 to D3 determine the attenuation level.
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0 Table 9.
MSB D7 D6 D5 D4 D3 D2 D1
Mute
LSB FUNCTION D0 1 0 1 1 0 0 1 0 0 1 0 1 1 Soft Mute On Soft Mute with fast slope (I = IMAX) Soft Mute with slow slope (I = IMIN) Direct Mute Zero Crossing Mute On Zero Crossing Mute Off (delayed until next zerocrossing) Zero Crossing Mute and Pause Detector Reset 160mV ZC Window Threshold (WIN = 00)
15/21
Software specification Table 9.
MSB D7 D6 0 1 1 0 1 D5 1 0 1 D4 D3 D2 D1
TDA7342EQ2N Mute
LSB FUNCTION D0 80mV ZC Window Threshold (WIN = 01) 40mV ZC Window Threshold (WIN = 10) 20mV ZC Window Threshold (WIN = 11) Nonsymmetrical Bass Cut (1) Symmetrical Bass Cut
1. Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain)
An additional direct mute function is included in the Speaker Attenuators. Table 10.
MSB D7 D6 D5 D4 D3 D2 D1
Speaker attenuators
LSB SPEAKER ATTENUATOR LF, LR, RF, RR D0 1.25dB step
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB 10dB step
X X X X X
X X X X X
X X X X X
0 0 1 1 1
0 1 0 1 1 1 1 1
0dB -10dB -20dB -30dB Speaker Mute
For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0 Table 11.
MSB D7 D6 D5 D4 D3 D2 D1
Bass/Treble
LSB FUNCTION D0 Treble step 0 0 0 0 0 0 0 1 -14dB -12dB
16/21
TDA7342EQ2N Table 11.
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 1 1 0 0 1 1 0 0
Software specification Bass/Treble (continued)
LSB FUNCTION D0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB Bass steps 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 -10dB -8dB -6dB -4dB -2dB -0dB -0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 146B 18dB
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1
17/21
Software specification Table 12.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7342EQ2N Volume
LSB FUNCTION D0 0.31dB Fine Attenuation Steps 0 0 1 1 0 1 0 1 0dB -0.31dB -0.62dB -0.94dB 1.25dB Coarse Attenuation Steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB 10dB Gain / Attenuation Steps
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
20dB 10dB 0dB -10dB -20dB -30dB -40dB -50dB
For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1 Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0
18/21
TDA7342EQ2N
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6. TQFP32 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09 9.00 7.00 5.60 0.80 9.00 7.00 5.60 0.60 1.00 0.75 0.018 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.354 0.276 0.220 0.031 0.354 0.276 0.220 0.024 0.039 0.030 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 inch
OUTLINE AND MECHANICAL DATA
Weight: 0.20gr
TQFP32 (7 x 7 x 1.40mm)
0(min.), 3.5(typ.), 7(max.)
D D1 D3 A1
17 16
0.10mm .004 Seating Plane
A A2
24 25
E3
E1
B
E
32 1 8
9
B C L K
0060661 C
e L1
TQFP32
19/21
Revision history
TDA7342EQ2N
7
Revision history
Table 13.
Date 03-Aug-2006
Document revision history
Revision 1 Initial release. Changes
20/21
TDA7342EQ2N
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