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PM6675AS
High efficiency step-down controller with embedded 2 A LDO regulator
Features
Switching section - 4.5 V to 36 V input voltage range - 0.6 V, 1 % voltage reference - Selectable 1.5 V fixed output voltage - Adjustable 0.6 V to 3.3 V output voltage - 1.237 V 1 % reference voltage available - Very fast load transient response using constant-on-time control loop - No RSENSE current sensing using low side MOSFETs' RDS(ON) - Negative current limit - Latched OVP and UVP - Soft-start internally fixed at 3 ms - Selectable pulse skipping at light load - Selectable No-audible (33 kHz) pulse skip mode - Ceramic output capacitors supported - Output voltage ripple compensation - Output soft-end LDO regulator section - Adjustable 0.6 V to 3.3 V output voltage - Selectable 1 Apk or 2 Apk current limit - Dedicated power-good signal - Ceramic output capacitors supported - Output soft-end
VFQFPN-24 4x4
Description
The PM6675AS device consists of a single high efficiency step-down controller and an independent low drop-out (LDO) linear regulator. The constant on-time (COT) architecture assures fast transient response supporting both electrolytic and ceramic output capacitors. An embedded integrator control loop compensates the DC voltage error due to the output ripple. Selectable low-consumption mode allows the highest efficiency over a wide range of load conditions. The low-noise mode sets the minimum switching frequency to 33 kHz for audio-sensitive applications. The LDO linear regulator can sink and source up to 2 Apk. Two fixed current limit (1 A- 2 A) can be chosen. An active soft-end is independently performed on both the switching and the linear regulators outputs when disabled.
Applications

Industrial application on 24 V Graphic cards
Embedded computer systems Table 1. Device summary
Order codes PM6675AS VFQFPN-24 4x4 (exposed pad) PM6675ASTR Tape and reel Package Packaging Tube
February 2008
Rev 1
1/48
www.st.com
Contents
PM6675AS
Contents
1 2 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 3.2 3.3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 5 6 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 Switching section - constant on-time pwm controller . . . . . . . . . . . . . . . . 16
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 Constant-on-time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 19 Pulse-skip and no-audible pulse-skip modes . . . . . . . . . . . . . . . . . . . . . 24 Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 POR, UVLO and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Switching section power-good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Switching section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Switching section OV and UV protections . . . . . . . . . . . . . . . . . . . . . . . 30
2/48
PM6675AS 7.1.12
Contents Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2
LDO linear regulator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2.1 7.2.2 7.2.3 7.2.4 LDO section current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 LDO section soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 LDO section power-good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 LDO section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 VOUT current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3/48
Typical application circuit
PM6675AS
1
Figure 1.
Typical application circuit
Application circuit
R LP
+5V VIN
C IN3
C IN2
R1 C IN R2
3 NOSKIP
12 LILIM
6 AVCC
18 VCC
8 VOSC
22 B O O HGATE 21 T PHASE 20
VLDOIN
C IN4 LDO PG
C BOOT L
10 VSEL 23 LIN
VSMPS
C OUT R LIM
4 LPG 24 LOUT
PM6675AS PM6675A
LGATE 17 CSNS PGND VSNS 19 16 9
VLDO
2 LFB 1 LGND
SWEN
SGND
COMP
VREF
SPG
LEN
C INT
5
15
14
13
7
11
C OUT2 SMPS PG C BYP
4/48
PM6675AS
Pin settings
2
2.1
Pin settings
Connections
Figure 2. Pin connection (through top view)
HGATE
BOOT
PHASE
LOUT
24 1 LGND LFB NOSKIP LPG SGND AVCC 6 7 COMP VOSC VSNS VSEL VREF
CSNS 19 18 VCC LGATE
LIN
PM6675AS PM6675A
PGND SPG LEN 13 12 LILIM SWEN
5/48
Pin settings
PM6675AS
2.2
Pin description
Table 2.
N 1 2 3 4
Pin functions
Pin LGND LFB NOSKIP LPG Function LDO power ground. Connect to negative terminal of VTT output capacitor. LDO remote sensing. Connect as close as possible to the load via a low noise PCB trace. Pulse-skip/no-audible pulse-skip modes selector. See Section 7.1.4: Mode-of-operation selection LDO section power-good signal (open drain output). High when LDO output voltage is within 10 % of nominal value. Ground Reference for analog circuitry, control logic and VTTREF buffer. Connect together with the thermal pad and VTTGND to a low impedance ground plane. See the Application Note for details. +5 V supply for internal logic. Connect to +5 V rail through a simple RC filtering network. High accuracy output voltage reference (1.237 V) for multilevel pins setting. It can deliver up to 50 uA. Connect a 100 nF capacitor between VREF and SGND in order to enhance noise rejection. Frequency Selection. Connect to the central tap of a resistor divider to set the desired switching frequency. The pin cannot be left floating. See Section 7: Device description for details. Switching section output remote sensing and discharge path during output soft-end. Connect as close as possible to the load via a low noise PCB trace. Fixed output selector and feedback input for the switching controller. If VSEL pin voltage is higher than 4 V, the fixed 1.5 V output is selected. If VSEL pin voltage is lower than 4 V, it is used as negative input of the error amplifier. See Section 7.1.4: Mode-of-operation selection for details. DC voltage error compensation input pin for the switching section. Refer to Mode of Operation Selection section for more details. Current limit selector for the LDO. Connect to SGND for 1 A current limit or to +5 V for 2 A current limit. Switching Controller Enable. When tied to ground, the switching output is turned off and a soft-end is performed. Linear Regulator Enable. When tied to ground, the LDO output is turned off and a soft-end is performed. Switching Section power-good signal (open drain output). High when the switching regulator output voltage is within 10 % of nominal value. Power ground for the switching section. Low-side gate driver output. +5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND.
5
SGND
6
AVCC
7
VREF
8
VOSC
9
VSNS
10
VSEL
11 12 13 14 15 16 17 18
COMP LILIM SWEN LEN SPG PGND LGATE VCC
6/48
PM6675AS Table 2.
N 19 20 21 22 23 24
Pin settings Pin functions (continued)
Pin CSNS PHASE HGATE BOOT LIN LOUT Function Current sense input for the switching section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSon sensing) to set the current limit threshold. Switch node connection and return path for the high side gate driver. High-Side Gate Driver Output Bootstrap capacitor connection. Input for the supply voltage of the high-side gate driver. Linear Regulator Input. Bypass to LGND by a 10 F ceramic capacitor for noise rejection enhancement. LDO linear regulator output. Bypass with a 20 F (2x10 F MLCC) filter capacitor.
7/48
Electrical data
PM6675AS
3
3.1
Electrical data
Maximum rating
Table 3.
Symbol VAVCC VVCC AVCC to SGND VCC to SGND PGND, LGND to SGND HGATE and BOOT to PHASE HGATE and BOOT to PGND VPHASE PHASE to SGND LGATE to PGND CSNS, SPG, LEN, SWEN, LILIM, COMP, VSEL, VSNS, VOSC, VREF, NOSKIP to SGND LPG,VREF, LOUT, LFB to SGND LIN, LOUT, LPG, LIN to LGND PTOT Power dissipation @TA = 25C
Absolute maximum ratings (1)
Parameter Value -0.3 to 6 -0.3 to 6 -0.3 to 0.3 -0.3 to 6 -0.3 to 44 -0.3 to 38 -0.3 to VVCC +0.3 -0.3 to VAVCC + 0.3 -0.3 to VAVCC + 0.3 -0.3 to VAVCC + 0.3 2.3 W V Unit
1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
3.2
Thermal data
Table 4.
Symbol RthJA TSTG TA TJ
Thermal data
Parameter Thermal resistance junction to ambient Storage temperature range Operating ambient temperature range Junction operating temperature range Value 42 -50 to 150 -40 to 85 -40 to 125 C Unit C/W
3.3
Recommended operating conditions
Table 5.
Symbol
Recommended operating conditions
Parameter Input voltage range IC supply voltage IC supply voltage Min 4.5 4.5 4.5 Typ Max 36 5.5 5.5 V Unit
VIN VAVCC VVCC
8/48
PM6675AS
Electrical characteristics
4
Table 6.
Electrical characteristics
Electrical characteristics TA = - 25 C to 85 C , VCC = AVCC = +5 V, LIN = 1.5 V and LOUT= 0.6 V if not otherwise specified (1).
Parameter Test condition Min Typ Max Unit
Symbol Supply section
IIN
Operating current (Switching + LDO)
SWEN, LEN, VSEL and NOSKIP connected to AVCC, No load on LOUT output. SWEN, VSEL and NOSKIP connected to AVCC, LEN coneected to SGND. SWEN and LEN tied to SGND. 4.1 3.85 70 4.25 4.0
2 mA 1 10 4.4 V 4.1 mV A
ISW ISHDN
Operating current (switching) Shutdown operating current AVCC Under Voltage Lockout upper threshold
UVLO
AVCC Under Voltage Lockout lower threshold UVLO hysteresis
On-time (SMPS) VSEL low, NOSKIP low, VOSC = 300 mV VOSC = 500 mV 530 320 630 380 730 ns 440
tON
On-time duration
VVSNS = 2 V
OFF-TIME (SMPS) tOFFMIN Minimum Off-Time
300
350
ns
Voltage reference Voltage accuracy Load regulation Undervoltage Lockout Fault Threshold SMPS output VOUT SMPS fixed output voltage Feedback output voltage accuracy VSEL connected to AVCC, NOSKIP tied to SGND, No Load -1.5 1.5 1.5 V % 4.5 V< VIN < 36 V -50 A < IVREF < 50 A 1.224 -4 800 1.237 1.249 4 mV V
9/48
Electrical characteristics
PM6675AS
Table 6.
Electrical characteristics (continued) TA = -25 C to 85 C , VCC = AVCC = +5 V, LIN = 1.5 V and LOUT= 0.6 V if not otherwise specified. (1)
Parameter Test condition Min Typ Max Unit
Symbol
Current limit and zero crossing comparator ICSNS CSNS input bias current Comparator offset Positive current limit threshold fixed negative current limit threshold VZC,OFFS Zero crossing comparator offset -11 VPGND - VCSNS 90 -6 100 mV 110 -5 1 100 110 6 A
High and low side gate drivers HGATE high state (pullup) HGATE driver on-resistance HGATE low state (pulldown) LGATE high state (pullup) LGATE driver on-resistance LGATE low state (pulldown) UVP/OVP protections and PGOOD signals OVP UVP Over voltage threshold Under voltage threshold SMPS upper threshold SMPS lower threshold PGOOD LDO upper threshold LDO lower threshold IPG,LEAK VPG,LOW SPG and LPG leakeage current SPG and LPG low level voltage SPG and LPG forced to 5.5 V ILPG,SINK = ISPG,SINK = 4 mA 150 107 86 110 90 113 93 1 250 A mV 112 67 107 86 115 70 110 90 118 73 113 % 93 0.6 0.9 1.8 1.4 2.7 2.1 2.0 3
Soft-start section (SMPS) Soft-start ramp time (4 steps current limit) Soft-start current limit step Soft end section Switching section discharge resistance LDO section discharge resistance LDO section LDO reference voltage VLREF LDO output accuracy respect to VREF -1 mA < ILDO < 1 mA -1 A < ILDO < 1 A -20 -25 600 20 25 mV 15 15 25 25 35 35 2 3 25 4 ms A
10/48
PM6675AS Table 6.
Electrical characteristics Electrical characteristics (continued) TA = -25 C to 85 C , VCC = AVCC = +5 V, LIN = 1.5 V and LOUT= 0.6 V if not otherwise specified. (1)
Parameter LDO sink current limit Test condition VLFB > VLREF , LILIM = 5 V VLFB > VLREF, LILIM = 0 V 0.9 VLREF < VLFB < VLREF, LILIM=5V Min -3 -1.6 2 1 1 0.5 Typ -2.3 -1.3 2.4 1.3 1.3 0.8 1 Max -2 -1 3 A 1.6 1.6 1.1 10 1 A -1 -1 1 1 Unit
Symbol
ILDO,CL LDO source current limit
0.9 VLREF < VLFB < VLREF, LILIM = 0 V VLFB < 0.9 VLREF, LILIM = 5 V VLFB < 0.9 VLREF, LILIM = 0 V
ILIN,BIAS
LDO input bias current, on LDO input bias current, off
LEN connected to AVCC, no load LEN = 0 V, no load LEN connected to AVCC
ILFB,BIAS ILFB,LEAK
LFB input bias current LFB leakage current
VLFB = 0.6 V
LEN=0V, VLFB = 0.6V
Power management section Fixed mode VVTHVSEL VSEL pin thresholds Adjustable mode Forced-PWM mode VVTHNOSKIP NOSKIP pin thresholds No-audible mode Pulse-skip mode VVTHLEN, VVTHSWEN LEN, SWEN turn off level LEN, SWEN turn on level 2A LDO current limit VVTHLILIM IIN,LEAK IIN3,LEAK IOSC,LEAK LILIM pin thresholds 1A LDO current limit Logic input leakage current Multilevel input leakage current VOSC pin leakage current LEN, SWEN and LILIM = 5 V VSEL and NOSKIP = 5 V VOSC = 1 V 0.4 1.6 VAVCC -0.8 1.0 VAVCC -1.5 0.5 V VAVCC -1.3 VAVCC -0.7
VAVCC -0.8
0.5 10 10 1 A
Thermal shutdown TSHDN Shutdown temperature (2) 150 C
1. Specifications referred to TJ = TA. All the parameters at operating temperatures extremes are guaranteed by design and statistical correlation (not production tested). 2. Guaranteed by design. Not production tested.
11/48
Block diagram
PM6675AS
5
Figure 3.
Block diagram
Functional and block diagram
VREF VOSC
Vr = 0.6V 1.236V Bandgap Level shifter
BOOT
Ton 1-shot Ton min 1-shot
LFB LIN
_
HGATE PHASE
Anti Cross Conduction
LOUT
+ LDS LEN
LILIM
Toff min 1-shot
VCC LGATE PGND
0.6V
LGND
Vr +10% _ + + Vr -10% _ gm + Vr + SWEN VREF
Zero Crossing & Current Limit
CSNS
LPG
COMP
Vr +10% + + Vr -10%
SPG
SGND
UVP/OVP
Vr
AVCC
UVLO
SWEN
LDS
LDS
LEN
VSNS LILIM NOSKIP CONTROL LOGIC
Thermal Shutdown SDS
adj
fix
LEN
SWEN
VSEL
Table 7.
SWEN LEN LDS SDS LILIM
Legend
Switching controller enable LDO regulator enable LDO output discharge enable Switching output discharge enable LDO regulator current limit
12/48
PM6675AS
Typical operating characteristics
6
Figure 4.
Typical operating characteristics
Efficiency vs output load FSW = 330 kHz VOUT=1.5 V, VIN = 24 V
VOUT - Efficiency
100 90 80 Forced PWM Pulse Skip Non Audible PS
Figure 5.
Switching frequency vs output current, VOUT = 1.5 V, VIN = 24 V
SW Frequency VS VOUT Load
500
400 Frequency [kHz]
Efficiency [%]
70 60 50 40 30 20 10 0 0.001 0.010 0.100 1.000 10.000
300 Forced PWM 200 Pulse Skip Non Audible PS 100
Current [A]
0 0.010
0.100
1.000
10.000
Current [A]
Figure 6.
Switching frequency vs input Figure 7. voltage, VOUT = 1.5 V, IVOUT = 2 A, forced PWM mode
SW Frequency VS Input Voltage
1.540 1.535 1.530
VOUT load regulation, VIN = 24 V
VOUT - Load Regulation
550
Forced PWM Pulse Skip Non Audible PS
Frequency [kHz]
Voltage [V]
450
1.525 1.520 1.515 1.510 1.505
350
250 4 14 Voltage [V] 24 34
1.500 0.001
0.010
0.100
1.000
10.000
Current [A]
Figure 8.
LOUT load regulation LDOIN = VOUT, VOUT in forced PWM mode
LOUT - Load Regulation
Figure 9.
VOUT = 1.5 V, VIN = 24 V, IVOUT = 0 A, pulse-skip mode
1.090 1.080 1.070
Voltage [V]
1.060 1.050 1.040 1.030 1.020 -1.500
-1.000
-0.500
0.000
0.500
1.000
1.500
Current [A]
13/48
Typical operating characteristics
PM6675AS
Figure 10. VOUT = 1.5V , VIN = 24V, IVOUT = 0 A, forced-PWM mode
Figure 11. VOUT = 1.5 V, VIN = 24 V, no load, Non-audible pulse-skip mode (33 kHz)
Figure 12. VOUT Soft-start @150m load, pulse-skip mode
Figure 13. LOUT turn on, VOUT in pulse-skip mode
Figure 14. VOUT Load Transient (VIN = 24 V, LOAD = 0 A -> 7 A @2.5 A/s). pulse-skip mode
Figure 15. LOUT load transient (VIN = 24 V, LOAD = -1.5 A -> 1.5 A @2.5 A/s). pulse-skip mode
14/48
PM6675AS Figure 16. VOUT and LOUT output voltages. VOUT soft-end. LOUT powered by an auxiliary rail
Typical operating characteristics Figure 17. VOUT and LOUT output voltages LOUT soft-end
Figure 18. UV protection, pulse-skip mode LOUT powered by an auxiliary rail
Figure 19. OV protection, pulse-skip mode
Figure 20. VOUT current limit protection during a load transient (0 A to 9 A @2.5A/s)
Figure 21. LOUT current limit during an output short
15/48
Device description
PM6675AS
7
Device description
The PM6675AS combines a single high efficiency step-down controller and an independent Low Drop-Out (LDO) linear regulator in the same package. The switching controller section is a high-performance, pseudo-fixed frequency, ConstantOn-Time (COT) based regulator specifically designed for handling fast load transient over a wide range of input voltage. The switching section output can be easily set to a fixed 1.5 V voltage without additional components or adjusted in the 0.6 V to 3.3 V range using an external resistor divider. The Switching Mode Power Supply (SMPS) can handle different modes of operation in order to minimize noise or power consumption, depending on the application needs. Selectable lowconsumption and low-noise modes allow the highest efficiency and a 33 kHz minimum switching frequency respectively at light loads. The current sensing is lossless, based on the Low-Side MOSFET turn-on resistance. The input of the LDO can be either the switching section output or a lower voltage rail in order to reduce the total power dissipation. Linear regulator stability is achieved by filtering its output with a ceramic capacitor (20 F or greater). The LDO linear regulator can sink and source up to 2 Apk. Two fixed current limit (1A-2A) can be chosen. An active soft-end is independently performed on both the switching and the linear regulators outputs when disabled.
7.1
Switching section - constant on-time pwm controller
The PM6675AS employes a pseudo-fixed frequency, Constant On-Time (COT) controller as the core of the switching section. As well known, the COT controller concerns of a relatively simple algorithm and uses the ripple voltage derived across the output capacitor ESR to trigger the On-Time one-shot generator. In this way, the output capacitor ESR acts as a current sense resistor providing the appropriate ramp signal to the PWM comparator. Nearly constant switching frequency is achieved by the system loop in steady-state operating conditions by varying the On-Time duration, avoiding thus the need for a clock generator. The On-Time one shot duration is directly proportional to the output voltage, sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC pin, as follows: Equation 1
TON = K OSC
VSNS + VOSC
where KOSC is a constant value (130 ns typ.) and is the internal propagation delay (40ns typ.). The one-shot generator directly drives the high-side MOSFET at the beginning of each switching cycle allowing the inductor current to increase; after the On-Time has expired, an Off-Time phase, in which the low-side MOSFET is turned on, follows.
16/48
PM6675AS
Device description
The Off-Time duration is solely determined by the output voltage: when lower than the set value (i.e. the voltage at VSNS pin is lower than the internal reference = 0.6 V), the synchronous rectifier is turned off and a new cycle begins (Figure 22).
Figure 22. Inductor current and output voltage in steady state conditions
Inductor current
Output voltage
Vreg
Ton
Toff
t
The duty-cycle of the buck converter is, in steady-state conditions, given by
Equation 2
D=
VOUT VIN
The switching frequency is thus calculated as
Equation 3
fSW
D = = TON
VOUT VIN 1 = OSC V OUT K OSC K OSC SNS VOSC
where
Equation 4 a
OSC =
VOSC VIN
Equation 4 b
OUT =
VSNS VOUT
17/48
Device description
PM6675AS
Referring to the typical application schematic (fig. 1 and 23), the final expression is then:
Figure 23. Switching frequency selection and VOSC pin
VIN
PM6675AS
R1
VOSC
R2
Equation 5
fSW =
OSC R2 1 = K OSC R1 + R 2 K OSC
Even if the switching frequency is theoretically independent from input and output voltages, parasitic parameters involved in power path (like MOSFET on-resistance and inductor DCR) introduce voltage drops responsible of a slight dependence on load current. In addition, the internal delay is cause of a light dependence from input voltage. The PM6675AS switching frequency can be set by an external divider connected to the VOSC pin. The voltage seen at this pin must be greater than 0.8 V and lower than 2 V in order to ensure system's linearity.
7.1.1
Constant-on-time architecture
Figure 24 shows the simplified block diagram of the Constant-On-Time controller.
The switching regulator of the PM6675AS owns a one-shot generator that turns on the highside MOSFET when the following conditions are simultaneously satisfied: the PWM comparator is high (i.e. output voltage is lower than Vr = 0.6 V), the synchronous rectifier current is below the current limit threshold and the minimum off-time has expired. A minimum off-time constrain (300 ns typ.) is introduced to assure the boot capacitor charge and allow inductor valley current sensing on low-side MOSFET. A minimum On-Time is also introduced to assure the start-up switching sequence. Once the on-time has timed out, the high side switch is turned off, while the synchronous rectifier is ignited according to the anti-cross conduction management circuitry. When the output voltage reaches the valley limit (determined by internal reference Vr=0.6 V), the low-side MOSFET is turned off according to the anti-cross conduction logic once again, and a new cycle begins.
18/48
PM6675AS Figure 24. Switching section simplified block diagram
VOSC
Device description
Positive Current Limit comparator
CSNS
100uA VBG
+ + PWM Comparator Integrator gm
Toff-min
VOSC Level shifter HS
BOOT HGATE PHASE
1-Shot generator
S R
Q Q
Anti crossconduction circuitry + + 2.5V
COMP +
0.6V
Ton-min VSEL<4V T on + 2.5V
500mV
VCC
VSEL
VSNS S
Min fsw counter
S Q Q
VOSC VSNS
Q
LS
LGATE PGND
R R + _
0.6V VBG bandgap 1.236V PULSE - SKIP
Zero-crossing Comparator
SGND
VREF
7.1.2
Output ripple compensation and loop stability
The loop is closed connecting the center tap of the output divider (internally, when the fixed output voltage is chosen, or externally, using the VSEL pin in the adjustable output voltage mode). The feedback node is the negative input of the error comparator, while the positive input is internally connected to the reference voltage (Vr = 0.6 V). When the feedback voltage becomes lower than the reference voltage, the PWM comparator goes high and sets the control logic, turning on the high-side MOSFET. After the On-Time (calculated as previously described) the system releases the high-side MOSFET and turns-on the synchronous rectifier. The voltage drop along ground and supply PCB paths, used to connect the output capacitor to the load, is a source of DC error. Further the system regulates the output voltage valley, not the average, as shown in Figure 22. Thus, the voltage ripple on the output capacitor is an additional source of DC error. To compensate this error, an integrative network is introduced in the control loop, by connecting the output voltage to the COMP pin through a capacitor (CINT) as shown in Figure 25.
19/48
Device description Figure 25. Circuitry for output ripple compensation
COMP PIN VOLTAGE Vr t OUTPUT VOLTAGE V V VREF
PM6675AS
COMP
I=gm(V1-Vr)
+
PWM Comparator
CFILT CINT RINT VCINT
Vr gm
-
+
RFb1
V1 RFb2
t
ESR
VSNS
COUT
The additional capacitor is used to reduce the voltage on the COMP pin when higher than 300 mVpp and is unnecessary for most of applications. The transconductance amplifier (gm) generates a current, proportional to the DC error, used to charge the CINT capacitor. The voltage across the CINT capacitor feeds the negative input of the PWM comparator, forcing the loop to compensate the total static error. An internal voltage clamp forces the COMP pin voltage range to 150 mV respect to VREF. This is useful to avoid or smooth output voltage overshoot during a load transient. When the Pulse-Skip Mode is entered, the clamping range is automatically reduced to 60 mV in order to enhance the recovering capability. In case the ripple amplitude is larger than 150 mV, an additional capacitor CFILT can be connected between the COMP pin and ground to reduce ripple amplitude, otherwise the integrator will operate out of its linearity range. This capacitor is unnecessary for most of applications and can be omitted. The design of the external feedback network depends on the output voltage ripple. If the ripple is higher than approximately 20 mV, the correct CINT capacitor is usually enough to keep the loop stable. The stability of the system depends firstly on the output capacitor zero frequency. The following condition must be satisfied:
Equation 6
fSW > k x fZout =
k 2 x C out x ESR
20/48
PM6675AS
Device description
where k is a fixed design parameter (k > 3). It determinates the minimum integrator capacitor value:
Equation 7
CINT >
Vr f Vout 2 SW - fZout k
gm
where gm = 50 s is the integrator transconductance. If the ripple on the COMP pin is greater than the integrator 150 mV, the auxiliary capacitor CFILT can be added. If q is the desired attenuation factor of the output ripple, CFILT is given by:
Equation 8
CFILT =
CINT (1 - q) q
In order to reduce the noise on the COMP pin, it is possible to add a resistor RINT that, together with CINT and CFILT, realizes a low pass filter. The cutoff frequency fCUT must be greater (10 or more times) than the switching frequency:
Equation 9
RINT =
2 fCUT
1 CINT CFILT CINT + CFILT
If the ripple is very small (lower than approximately 20 mV), a different compensation network, called "Virtual-ESR" Network, is needed. This additional circuit generates a triangular ripple that is added to the output voltage ripple at the input of the integrator. The complete control scheme is shown in Figure 26.
21/48
Device description Figure 26. "Virtual-ESR" network
T NODE VOLTAGE V1 t COMP PIN VOLTAGE VREF t
PM6675AS
V2
COMP
I=gm(V1-Vr)
VREF
+
PWM Comparator
RINT CINT
T
-
CFILT
Vr
gm
R1 R
OUTPUT VOLTAGE V
+
RFb1
V1 RFb2
C
VSNS
ESR COUT
t
The ripple on the COMP pin is the sum of the output voltage ripple and the triangular ripple generated by the Virtual-ESR Network. In fact the Virtual-ESR Network behaves like a further equivalent series resistor RVESR. A good trade-off is to design the network in order to achieve an RVESR given by:
Equation 10
R VESR =
VRIPPLE - ESR IL
where IL is the inductor current ripple and VRIPPLE is the total ripple at the T node, chosen greater than approximately 20 mV. The new closed-loop gain depends on CINT. In order to ensure stability it must be verified that:
Equation 11
CINT > where:
Equation 12
gm Vr 2 fZ Vout
fZ =
1 2 C out R TOT
22/48
PM6675AS
Device description
and
Equation 13
R TOT = ESR + R VERS
Moreover, the CINT capacitor must meet the following condition:
Equation 14
fSW > k fZ =
k 2 C out R TOT
where RTOT is the sum of the ESR of the output capacitor and the equivalent ESR given by the Virtual-ESR Network (RVESR). The k parameter must be greater than unity (k > 3) and determines the minimum integrator capacitor value CINT:
Equation 15
CINT >
gm Vr fSW Vout 2 - fZ k
The capacitor of the Virtual-ESR Network, C, is chosen as follow
Equation 16
C > 5 CINT and R is calculated to provide the desired triangular ripple voltage:
Equation 17
R=
L R VESR C
Finally, the R1 resistor can be selected according to expression 18:
Equation 18
1 R f C Z R1 = 1 R- fZ C
23/48
Device description
PM6675AS
7.1.3
Pulse-skip and no-audible pulse-skip modes
High efficiency at light load conditions is achieved by PM6675AS entering the Pulse-Skip Mode (if enabled). At light load conditions the zero-crossing comparator truncates the lowside switch On-Time as soon as the inductor current becomes negative; in this way the comparator determines the On-Time duration instead of the output ripple (see Figure 27).
Figure 27. Inductor current and output voltage at light load with Pulse-Skip
Inductor current
Output voltage
Vreg
TON TOFF
As a consequence, the output capacitor is left floating and its discharge depends solely on the current drained from the load. When the output ripple on the pin COMP falls under the reference, a new shot is triggered and the next cycle begins. The Pulse-Skip mode is naturally obtained enabling the zero-crossing comparator and automatically takes part in the COT algorithm when the inductor current is about half the ripple current amount, i.e. migrating from continuous conduction mode (C.C.M.) to discontinuous conduction mode (D.C.M.). The output current threshold related to the transition between PWM Mode and Pulse-Skip Mode can be approximately calculated as:
Equation 19
ILOAD (PWM2Skip) =
VIN - VOUT TON 2 L
At higher loads, the inductor current never crosses the zero and the device works in pure PWM mode with a switching frequency around the nominal value. A physiological consequence of Pulse-Skip Mode is a more noisy and asynchronous (than normal conditions) output, mainly due to very low load. If the Pulse-Skip is not compatible with the application, the PM6675AS allows the user to choose also between forced-PWM and No-Audible Pulse-Skip alternative modes (see Chapter 7.1.4 for details).
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PM6675AS
Device description
No-audible pulse-skip mode
Some audio-noise sensitive applications cannot accept the switching frequency to enter the audible range as is possible in Pulse-Skip mode with very light loads. For this reason, the PM6675AS implements an additional feature to maintain a minimum switching frequency of 33 kHz despite of a slight efficiency loss. At very light load conditions, if any switching cycle has taken place within 30 s (typ.) since the last one (because of the output voltage is still higher than the reference), a No-audible pulse-skip cycle begins. The low-side MOSFET is turned on and the output is driven to fall until the reference has been crossed. Then, the high-side switch is turned on for a Ton period and, once it has expired, the synchronous rectifier is enabled until the inductor current reaches the zero-crossing threshold (see Figure 28).
Figure 28. Inductor current and output voltage at light load with non-audible pulse-skip
Inductor current
Output voltage
Vreg TMAX TON TOFF TIDLE t
For frequencies higher than 33 kHz (due to heavier loads) the device works in the same way as in Pulse-Skip mode. It is important to notice that in both pulse-skip and no-audible PulseSkip modes the switching frequency changes not only with the load but also with the input voltage.
25/48
Device description
PM6675AS
7.1.4
Mode-of-operation selection
Figure 29. VSEL and NOSKIP multifunction pin configurations
VOUT
+5V PM6675AS
R9 R8
VSEL
VREF
NOSKIP
The PM6675AS has been designed to satisfy the widest range of applications. The device is provided of some multilevel pins which allow the user to choose the appropriate configuration. The VSEL pin is used to firstly decide between fixed preset or adjustable (user defined) output voltages. When the VSEL pin is connected to +5 V, the PM6675AS set the switching section output voltage to 1.5 V without the need of an external divider. Applications requiring different output voltages can be managed by PM6675AS simply setting the adjustable mode. If the VSEL pin voltage is higher than 4 V, the fixed output mode is selected. Connecting an external divider to the VSEL pin, it is used as negative input of the error amplifier and the output voltage is given by expression (20).
Equation 20
VOUTADJ = 0.6
R8 + R9 R8
The output voltage can be set in the range from 0.6 V to 3.3 V. The NOSKIP is the power saving algorithm selector: if tied to +5 V, the forced-PWM (fixed frequency) control is performed. If grounded or connected to VREF pin (1.237 V reference voltage), the Pulse-Skip or Non-Audible Pulse-Skip Modes are respectively selected.
Table 8. Mode-of-operation settings summary
NOSKIP VNOSKI P > 4.2 V VVSEL > 4.3V 1V < VNOSKIP < 3.5 V < 0.5 V VNOSKIP > 4.2 V VVSEL < 3.7V 1 V < VNOSKIP < 3.5 V VNOSKIP < 0.5 V ADJ 1.5 V VOUT Operating mode Forced-PWM Non-Audible Pulse-skip Pulse-Skip Forced-PWM Non-Audible Pulse-skip Pulse-Skip
VSEL
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PM6675AS
Device description
7.1.5
Current sensing and current limit
The PM6675AS switching controller employes a valley current sensing algorithm to properly handle the current limit protection and the inductor current zero-crossing information. The current is sensed during the conduction time of the low-side MOSFET. The current sensing element is the low-side MOSFET on-resistance. The sensing scheme is visible in Figure 30.
Figure 30. Current sensing scheme
HGATE PHASE
RILIM
CSNS LGATE PGND
An internal 100 A current source is connected to CSNS pin that is also the non-inverting input of the positive current limit comparator. When the voltage drop developed across the sensing parameter equals the voltage drop across the programming resistor RILIM, the controller skips subsequent cycles until the overcurrent is detected or the output UV protection latches off the device (see par. Chapter 7.1.4 UV and OV Protections). Referring to Figure 30, the RDSon sensing technique is tailored to all low cost, high efficiency applications. It must be taken into account that the current limit circuit actually regulates the inductor valley current. This means that RILIM must be calculated to set a limit threshold given by the maximum DC output current plus half of the inductor ripple current:
Equation 21
ICL = 100A where RSENSE is the sensing device (RDSon).
RILIM R SENSE
The PM6675AS provides also a fixed negative current limit to prevent excessive reverse inductor current when the switching section sinks current from the load in forced-PWM (3rd quadrant working conditions). This negative current limit threshold is measured between PHASE and PGND pins, comparing the drop magnitude on PHASE pin with an internal 110mV fixed voltage.
27/48
Device description
PM6675AS
7.1.6
POR, UVLO and soft-start
The PM6675AS automatically performs an internal startup sequence during the rising phase of the analog supply of the device (AVCC). The switching controller remains in a stand-by state until AVCC crosses the upper UVLO threshold (4.25 V typ.), keeping active the internal discharge MOSFETs (only if AVCC > 1 V). The soft-start allows a gradual increase of the internal current limit threshold during startup reducing the input/output surge currents. At the beginning of start-up, the PM6675AS current limit is set to 25 % of nominal value and the under voltage protection is disabled. Then, the current limit threshold is sequentially brought to 100 % in four steps of approximately 750 s (figure 13).
Figure 31. Soft-start waveforms
Switching output
Current limit threshold
SWEN
Time
After a fixed 3 ms total time, the soft-start finishes and UVP is released: if the output voltage doesn't reach the under voltage lower threshold within soft-start duration, the UVP condition is detected; the device performs a soft end and latches off. Depending on the load conditions, the inductor current may or may not reach the nominal value of the current limit (Figure 32 on page 29 shows two examples).
28/48
PM6675AS
Device description
Figure 32. Soft-start at heavy load (a) and short-circuit (b) condition, pulse-skip enabled
(a)
(b)
7.1.7
Switching section power-good signal
The SPG pin is an open drain output used to monitor output voltage through VSNS (in fixed output voltage mode) or VSEL (in adjustable output voltage mode) pins and is enabled after the soft-start timer has expired. The SPG signal is held low if the output voltage drops 10 % below or rises 10 % above the nominal regulated value. The SPG output can sink current up to 4 mA.
7.1.8
Switching section output discharge
Active soft-end of the output occurs when the SWEN (SWitching ENable) is forced low. When the switching section is turned off, an internal 25 resistor discharges the output through the VSNS pin.
Figure 33. Switching section soft-end
VOUT Resistive Discharge
SWEN
29/48
Device description
PM6675AS
7.1.9
Gate drivers
The integrated high-current gate drivers allow using different power MOSFETs. The highside driver employes a bootstrap circuit which is supplied by the +5 V rail. The BOOT and PHASE pins work respectively as supply and return path for the high-side driver, while the low-side driver is directly feed through VCC and PGND pins. An important feature of the PM6675AS gate drivers is the Adaptive Anti-Cross-Conduction circuitry, which prevents high-side and low-side MOSFETs from being turned on at the same time. When the high-side MOSFET is turned off, the voltage at the PHASE node begins to fall. The low-side MOSFET is turned on only when the voltage at the PHASE node reaches an internal threshold (2.5 V typ.). Similarly, when the low-side MOSFET is turned off, the high-side one remains off until the LGATE pin voltage is above 1 V. The power dissipation of the drivers is a function of the total gate charge of the external power MOSFETs and the switching frequency, as shown in the following equation:
Equation 22
PD (driver ) = VDRV Q g fSW
The low-side driver has been designed to have a low-resistance pull-down transistor (0.6 typ.) in order to prevent undesired ignition of the low-side MOSFET due to the Miller effect.
7.1.10
Reference voltage and bandgap
The 1.237 V internal bandgap reference has a granted accuracy of 1 % over the -25 C to 85 C temperature range. The VREF pin is a buffered replica of the bandgap voltage. It can supply up to 100 A and is suitable to set the intermediate level of NOSKIP multifunction pin. A 100 nF (min.) bypass capacitor toward SGND is required to enhance noise rejection. If VREF falls below 0.8 V (typ.), the system detects a fault condition and all the circuitry is turned off. An internal divider derives a 0.6 V1 % voltage (Vr) from the bandgap. This voltage is used as reference for both the switching and the linear sections. The Over-Voltage Protection, the Under-Voltage Protection and the power-good signals are also referred to Vr.
7.1.11
Switching section OV and UV protections
When the switching output voltage is about 115 % of its nominal value, a latched OverVoltage Protection (OVP) occurs. In this case the synchronous rectifier immediately turns on while the high-side MOSFET turns off. The output capacitor is rapidly discharged and the load is preserved from being damaged. The OVP is also active during the soft-start. Once an OVP has taken part, a toggle on SWEN pin or a power-on-reset is necessary to exit from the latched state. When the switching output voltage is below 70 % of its nominal value, a latched UnderVoltage Protection occurs. This event causes the switching section to be immediately disabled and both switches to be opened. The controller performs a soft-end and the output is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than 400 mV.
30/48
PM6675AS
Device description
The Under-Voltage Protection circuit is enabled only at the end of the soft-start. Once an UVP has taken part, a toggle on SWEN pin or a Power-On-Reset is necessary to clear the fault state and restart the section.
7.1.12
Device thermal protection
The internal control circuitry of the PM6675AS self-monitors the junction temperature and turns all outputs off when the 150 C limit has been overran. This event causes the switching section to be immediately disabled and both switches to be opened. The controller performs a soft-end and both the outputs are eventually kept to ground, then the low side MOSFET is turned on when the voltage of the switching section is lower than 400 mV. The thermal fault is a latched protection and normal operating condition is restored by a Power-On Reset or toggling SWEN and LEN pins at the same time.
Table 9.
Fault Over voltage
Switching section OV, UV and OT faults management
Conditions VOUT > 115 % of the nominal value Action LGATE pin is forced high and the device latches off. Exit by a Power-On Reset or toggling SWEN
Under voltage
LGATE pin is forced high after the soft-end, then the VOUT < 70 % of the nominal device latches off. Exit by a Power-On Reset or value toggling SWEN. TJ > +150 C LGATE pin is forced high after the soft-end, then the device latches off. Exit by a Power-On Reset or toggling SWEN and LEN after temperature drop.
Junction over temperature
7.2
LDO linear regulator section
The independent Low-Drop-Out (LDO) linear regulator has been designed to sink and source up to 2 A peak current and 1 A continuously. The LDO output voltage can be adjusted in the range 0.6 V to 3.3 V simply connecting a resistor divider as shown in Figure 34 on page 32.
Equation 23
VLDO ADJ = 0.6
R19 + R20 R20
31/48
Device description Figure 34. LDO output voltage selection
PM6675AS
PM6675AS
VLOUT Cc COUT R19 LFB R20 LGND LOUT
A compensation capacitor Cc must be added to adjust the dynamic response of the loop. The value of Cc is calculated according to the desired bandwidth of the LDO regulator and depends on the value of the feedback resistors. In most of applications the pole due to the compensation capacitor is placed at 100-200 kHz (equation 24).
Equation 24
fp =
1 = 200kHz 2(R19 R20) C C
The LIN input can be connected to the switching section output for compact solutions or to a lower supply, if available in the system, in order to reduce the power dissipation of the LDO. A minimum output capacitance of 20 F (2x10 F MLCC capacitors) is enough to assure stability and fast load transient response.
7.2.1
LDO section current limit
The LDO regulator can handle up to 2 Apk, depending on the LDO input voltage and the LILIM pin setting. The output current is limited to 1 A or 2 A if the LILIM pin is connected to SGND or AVCC respectively (Figure 35).
Figure 35. LDO current limit setting
+5V 2A CL 1A CL
PM6675AS
LILIM
The maximum current that the LDO can source depends also on the input and output voltages. Due to the high side MOSFET of the output stage, the LDO cannot source the limit current at high output voltages. Figure 36 shows the maximum current that the LDO can source as function of the input and output voltages. For output voltages higher than 2 V, the maximum output current is limited as reported.
32/48
PM6675AS Figure 36. LDO current limit setting
2.2 2.0 1.8 1.6
VOUT=1.05V VOUT=1.2V VOUT=1.5V VOUT=1.8V VOUT=2.0V VOUT=2.2V VOUT=2.5V VOUT=3.3V
Device description
ILOUT [A]
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VLIN [V]
7.2.2
LDO section soft-start
The LDO section soft-start is performed by clamping the current limit. During startup, the LDO current limit voltage is set to 1 A and the output voltage increases linearly. When the output voltage rises above 90 % of the nominal value, the current limit is released to 2 A according to the LILIM pin setting.
7.2.3
LDO section power-good signal
The LPG pin is an open drain output used to monitor the LDO output voltage through LFB pin. The LPG signal is held low if the output voltage drops 10 % below or rises 10 % above the nominal regulated value. The LPG output can sink current up to 4 mA.
7.2.4
LDO section output discharge
Active soft-end of the LDO output occurs when the LEN (Linear ENable) is forced low. When the LDO section is turned off, an internal 25 resistor, directly connected to the LOUT pin, discharges the output.
Figure 37. LDO section soft-end
VLDO Resistive Discharge
LEN
33/48
Application information
PM6675AS
8
Application information
The purpose of this chapter is to show the design procedure of the switching section. The design starts from three main specifications:

The input voltage range, provided by the battery or the AC adapter. The two extreme values (VINmax and VINmin) are important for the design. The maximum load current, indicated with ILOAD,MAX . The maximum allowed output voltage ripple VRIPPLE,MAX.
It's also possible that specific designs should involve other specifications. The following paragraphs will guide the user into a step-by-step design.
8.1
External components selection
The PM6675AS employes a pseudo-fixed frequency, Constant On-Time (COT) controller as the core of the switching section. The switching frequency can be set by connecting an external divider to the VOSC pin. The voltage seen at this pin must be greater than 0.8 V and lower than 2 V in order to take advantage of the internal block linearity. Nearly constant switching frequency is achieved by the system loop in steady-state operating conditions by varying the On-Time duration, avoiding thus the need for a clock generator. The On-Time one shot duration is directly proportional to the output voltage, sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC pin, as follows:
Equation 25
TON = K OSC
VSNS + VOSC
where KOSC is a constant value (130 ns typ.) and is the internal propagation delay (40 ns typ.). The duty-cycle of the buck converter is, in steady-state conditions, given by
Equation 26
D=
VOUT VIN
The switching frequency is thus calculated as
Equation 27
fSW
VOUT VIN D 1 = = = OSC VSNS TON OUT K OSC K OSC VOSC
34/48
PM6675AS Equation 28 a
Application information
OSC =
VOSC VIN
Equation 28 b
OUT =
VSNS VOUT
Referring to the typical application schematic (figs. 1 and 23), the final expression is then:
Equation 29
fSW =
OSC R2 1 = K OSC R1 + R 2 K OSC
Even if the switching frequency is theoretically independent from battery and output voltages, parasitic parameters involved in power path (like MOSFETs on-resistance and inductor DCR) introduce voltage drops responsible of a slight dependence on load current. In addition, the internal delay is cause of a light dependence from input voltage.
Table 10. Typical values for switching frequency selection
R2 (k) 11 13 15 18 20 22 Approx switching frequency (kHz) 250 300 350 400 450 500
R1 (k) 330 330 330 330 330 330
8.1.1
Inductor selection
Once the switching frequency has been defined, the inductance value depends on the desired inductor ripple current. Low inductance value means great ripple current that brings to poor efficiency and great output noise. On the other hand a great current ripple is desirable for fast transient response when a load step is applied. Otherwise, great inductance brings to good efficiency but the transient response is critical, especially if VINmin - Vout is little. Moreover a minimum output ripple voltage is necessary to assure system stability and jitter-free operations (see Output capacitor selection paragraph). The product of the output capacitor ESR multiplied by the inductor ripple current must be taken into consideration. A good trade-off between the transient response time, the efficiency, the cost and the size is to choose the inductance value in order to maintain the inductor ripple current between 20 % and 50 % (usually 40 %) of the maximum output current. The maximum inductor ripple current, ILMAX, occurs at the maximum input voltage.
35/48
Application information
PM6675AS
With these considerations, the inductance value can be calculated with the following expression:
Equation 30
L=
VIN - VOUT VOUT fsw IL VIN
where fSW is the switching frequency, VIN is the input voltage, VOUT is the output voltage and is the inductor current ripple. Once the inductor value is determined, the inductor current ripple is then recalculated:
Equation 31
IL,MAX =
VIN,MAX - VOUT fsw L
VOUT VIN,MAX
The next step is the calculation of the maximum r.m.s. inductor current:
Equation 32
IL,RMS = (ILOAD,MAX ) 2 +
(IL,MAX ) 2 12
The inductor must have an r.m.s. current greater than IL,RMS in order to assure thermal stability. Then the calculation of the maximum inductor peak current follows:
Equation 33
IL,PEAK = ILOAD,MAX +
IL,MAX 2
ILPEAK is important in inductor selection in term of its saturation current. The saturation current of the inductor should be greater than ILPEAK not only in case of hard saturation core inductors. Using soft-ferrite cores it is possible (but not advisable) to push the inductor working near its saturation current. In Table 11 some inductors suitable for typical working conditions are listed.
Table 11. Evaluated inductors (@ fsw = 400 kHz)
Series MLC1538-102 MVR1261C-112 7443552100 HC8-1R2 Inductance (H) 1 1.1 1 1.2 +40C rms current (A) 13.4 20 16 16.0 -30% saturation current (A) 21.0 20 20 25.4
Manufacturer COILCRAFT COILCRAFT WURTH COILTRONICS
36/48
PM6675AS
Application information
In Pulse-Skip Mode, low inductance values produce a better efficiency versus load curve, while higher values result in higher full-load efficiency because of the smaller current ripple.
8.1.2
Input capacitor selection
In a buck topology converter the current that flows through the input capacitor is pulsed and with zero average value. The RMS input current can be calculated as follows:
Equation 34
ICinRMS = ILOAD D (1 - D) +
2
1 D (IL ) 2 12
Neglecting the second term, the equation 34 is reduced to:
Equation 35
ICinRMS = ILOAD D (1 - D)
The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5:
Equation 36
Ploss = ESR Cin ICinRMS (max) 2 = ESR Cin (0.5 ILOAD (max)) 2
The input capacitor should be selected with a RMS rated current higher than ICinRMS. Tantalum capacitors are good in term of low ESR and small size, but they occasionally can burn out if subjected to very high current during operation. Multi-Layers-Ceramic-Capacitors (MLCC) have usually a higher RMS current rating with smaller size and they remain the best choice. The drawback is their quite high cost. It must be taken in account that MLCC capacitance decreases when the operating voltage is near the rated voltage. In table 12 some MLCC suitable for most of applications are listed.
Table 12. Evaluated MLCC for input filtering
Series UMK325BJ106KM-T GMK316F106ZL-T GMK325F106ZH-T GMK325BJ106KN C3225X5R1E106M Capacitance (F) 10 10 10 10 10 Rated voltage (V) 50 35 35 35 25 Maximum Irms @100 kHz (A) 2 2.2 2.2 2.5
Manufacturer TAIYO YUDEN TAIYO YUDEN TAIYO YUDEN TAIYO YUDEN TDK
37/48
Application information
PM6675AS
8.1.3
Output capacitor selection
Using tantalum or electrolytic capacitors, the selection is made referring to ESR and voltage rating rather than by a specific capacitance value. The output capacitor has to satisfy the output voltage ripple requirements. At a given switching frequency, small inductor values are useful to reduce the size of the choke but increase the inductor current ripple. Thus, to reduce the output voltage ripple a low ESR capacitor is required. To reduce jitter noise between different switching regulators in the system, it is preferable to work with an output voltage ripple greater than 25 mV. As far as it concerns the load transient requirements, the Equivalent Series Resistance (ESR) of the output capacitor must satisfy this relationship:
Equation 37
ESR
VRIPPLE,MAX IL,MAX
where VRIPPLE is the maximum tolerable ripple voltage. In addition, the ESR must be enough high to meet stability requirements. The output capacitor zero must be lower than the switching frequency:
Equation 38
fSW > fZ =
1 2 ESR C out
If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is negligible; then the inductance could be smaller, reducing the size of the choke. In this case it is important that the output capacitor can adsorb the inductor energy without generating an over-voltage condition when the system changes from a full load to a no load condition. The minimum output capacitance can be chosen by the following equation:
Equation 39
C OUT,min =
2 L ILOAD,MAX
Vf 2 - Vi 2
where Vf is the output capacitor voltage after the load transient and Vi is the output capacitor voltage before the load transient.
38/48
PM6675AS
Application information
In Table 13 some tested polymer capacitors are listed.
Table 13. Evaluated output capacitors
Series 4TPE220MF 4TPE150MI 4TPC220M HITACHI TNCB OE227MTRYF Capacitance (F) 220 150 220 220 Rated voltage (V) 4V 4V 4V 2.5 V ESR max @100kHz (m) 15 to 25 18 40 25
Manufacturer SANYO
8.1.4
MOSFETs selection
In SMPS converters, power management efficiency is a high level requirement, so the power dissipation on the power switches becomes an important factor in switches selection. Losses of high-side and low-side MOSFETs depend on their working condition. Considering the high-side MOSFET, the power dissipation is calculated as:
Equation 40
PDHighSide = Pconduction + Pswitching Maximum conduction losses are approximately given by:
Equation 41
Pconduction = R DSon
VOUT 2 ILOAD,MAX VIN. min
where RDSon is the MOSFET drain-source on-resistance. Switching losses are approximately given by:
Equation 42
Pswitching =
VIN (ILOAD (max) - 2
IL I ) t on fsw VIN (ILOAD (max) + L ) t off fsw 2 2 + 2
where tON and tOFF are the turn-on and turn-off times of the MOSFET and depend on the gate-driver current capability and the gate charge Qgate. A greater efficiency is achieved with low RDSon. Unfortunately low RDSon MOSFETs have a great gate charge. As general rule, the RDSon . Qgate product should be minimized to find out the suitable MOSFET. Logic-level MOSFETs are recommended, as long as low-side and high-side gate drivers are powered by VVCC = +5 V. The breakdown voltage of the MOSFETs (VBRDSS) must be greater than the maximum input voltage VINmax. Below some tested high-side MOSFETs are listed.
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Application information
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Table 14.
Evaluated high-side MOSFETs
Type STS12NH3LL STS7NF60L IRF7811 RDSon (m) 10.5 17 9 Gate charge (Nc) 12 25 18 Rated reverse voltage (V) 30 60 30
Manufacturer ST ST IR
In buck converters the power dissipation of the synchronous MOSFET is mainly due to conduction losses:
Equation 43
PDLowSide Pconduction Maximum conduction losses occur at the maximum input voltage:
Equation 44
V Pconduction = R DSon 1 - OUT VIN,MAX
ILOAD,MAX 2
The synchronous rectifier should have the lowest RDSon as possible. When the high-side MOSFET turns on, high dV/dt of the phase node can bring up even the low-side gate through its gate-drain capacitance CRES, causing cross-conduction problem. Once again, the choice of the low-side MOSFET is a trade-off between on resistance and gate charge; a good selection should minimizes the ratio CRSS / CGS where CGS = CISS - CRSS. Below some tested low-side MOSFETs are listed.
Table 15. Evaluated low-side MOSFETs
Type STS12NH3LL STS25NH3LL IRF7811 RDSon (m) 13.5 40 24 C GD C GS 0.069 0.011 0.054 Rated reverse voltage (V) 30 30 30
Manufacturer ST ST IR
Dual N-MOS can be used in applications with low output current.
Figure 16 shows some suitable dual MOSFETs for applications requiring about 3 A. Table 16. Suitable dual MOSFETs
Type STS8DNH3LL IRF7313 RDSon (m) 25 46 Gate charge (nC) 10 33 Rated reverse voltage (V) 30 30
Manufacturer ST IR
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PM6675AS
Application information
8.1.5
Diode selection
A rectifier across the synchronous switch is recommended. The rectifier works as a voltage clamp across the synchronous rectifier and reduces the negative inductor swing during the dead time between turning the high-side MOSFET off and the synchronous rectifier on. Moreover it increases the efficiency of the system. The reverse voltage should be greater than the maximum input voltage VINmax and a minimum recovery reverse charge is preferable. Table 17 shows some evaluated diodes.
Table 17. Evaluated free-wheeling rectifiers
Type STPS1L30M STPS1L30A STPS1L60A Forward voltage (V) 0.34 0.34 0.56 Rated reverse voltage (V) 30 30 60
Manufacturer ST ST ST
8.1.6
VOUT current limit setting
The valley current limit is set by RCSNS and must be chosen to support the maximum load current. The valley of the inductor current ILvalley is:
Equation 45
ILvalley = ILOAD (max) -
IL 2
The output current limit depends on the current ripple as shown in Figure 38:
Figure 38. Valley current limit waveforms
Current Inductor current MAX LOAD 2 MAX LOAD 1 Inductor current
Valley current limit
Time
Being fixed the valley threshold, the more the current ripple is greater, the more the DC output current is greater. If an output current limit greater than over all the input voltage range is required, the minimum current ripple must be considered in the previous formula. Then the resistor RCSNS is:
Equation 46
R CSNS =
R DSon ILvalley 100uA
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Application information
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where RDSon is the drain-source on-resistance low-side switch. Consider the temperature effect and the worst case value in RDSon calculation (typically +0.4 %/C). The accuracy of the valley current also depends on the offset of the internal comparator (6 mV). The negative valley-current limit (if the device works in forced-PWM mode) is given by:
Equation 47
INEG =
110mV RDSon
8.1.7
All ceramic capacitors application
Design of external feedback network depends on the output voltage ripple across the output capacitors ESR. If the ripple is great enough (at least 20 mV), the compensation network simply consist of a CINT capacitor.
Figure 39. Integrative compensation
Ton One-shot generator
VSNS
PWM Comparator VREF
VOUT
+ -
+
COMP
Integrator
gm
-
Vr=0.6
CFILT
RINT
CINT
The stability of the system depends firstly on the output capacitor zero frequency. It must be verified that:
Equation 48
fSW > k fZout =
k 2 R out C out
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PM6675AS
Application information
where k is a free design parameter greater than unity (k > 3) . It determinates the minimum integrator capacitor value CINT:
Equation 49
CINT >
Vref Vo f 2 SW - fZout k
gm
If the ripple on pin COMP is greater than the integrator output dynamic (150 mV), an additional capacitor Cfilt could be added in order to reduce its amplitude. If q is the desired attenuation factor of the output ripple, select:
Equation 50
C filt =
CINT (1 - q) q
In order to reduce noise on pin COMP, it's possible to introduce a resistor RINT that, together with CINT and Cfilt, realizes a low pass filter. The cutoff frequency must be much greater (10 or more times) than the switching frequency of the section:
Equation 51
RINT =
2 fCUT
1 CINT CFILT CINT + CFILT
For most of applications both RINT and Cfilt are unnecessary. If the ripple is very small (e.g. such as with ceramic capacitors), a further compensation network, called "Virtual ESR" network, is needed. This additional part generates a triangular ripple that substitutes the ESR output voltage ripple. The complete compensation scheme is represented in Figure 40.
Figure 40. Virtual ESR network
L R CINT
VOUT
R1
C RINT
PWM Comparator
+
gm VREF
Ton Generation Block
+ CFILT
-
0.6V
Integrator
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Application information
PM6675AS
Select C as shown:
Equation 52
C > 5 CINT Then calculate R in order to have enough ripple voltage on the integrator input:
Equation 53
R=
L R VESR C
Where RVERS is the new virtual output capacitor ESR. A good trade-off is to consider an equivalent ESR of 30-50 m, even though the choice depends on inductor current ripple. Then choose R1 as follows:
Equation 54
1 R Cf Z R1 = 1 R- CfZ
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PM6675AS
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Table 18. VFQFPN-24 4mm x 4mm mechanical data
mm. Dim. Min A A1 A2 D D1 E E1 0.80 Typ 0.90 0.0 0.65 4.00 3.75 4.00 3.75 12 0.24 0.42 0.50 24.00 6.00 6.00 0.30 0.18 1.95 1.95 2.10 2.10 0.40 0.50 0.30 2.25 2.25 0.60 Max 1.00 0.05 0.80
P e N Nd Ne L b D2 E2
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Package mechanical data
PM6675AS
Figure 41. Package dimensions
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PM6675AS
Revision history
10
Revision history
Table 19.
Date 19-Feb-2008
Document revision history
Revision 1 Initial release. Changes
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PM6675AS
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