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L6935
High performance 3 A ULDO linear regulator
Features

Up to 5 V input voltage range 60 m max RDS(on) 35 A shut-down current 3 A maximum output current Split bias and power supplies Adjustable output voltage: 0.5 V to 3.0 V Excellent load and line regulation: 1 % accuracy (over temperature) MLCC supported Programmable soft-start Short-circuit protection 3.5 A overcurrent protection Thermal shut-down VFQFPN20 4 x 4 x 1.0 mm package VFQFPN20 (4.0 x 4.0 x 1.0 mm)
Description
L6935 is an ultra low drop output linear regulator operating up to 5 V input and is able to support output current up to 3 A. Designed with an internal low-RDS(on) N-channel MOSFET, it can be used for on-board DC-DC conversions saving in real estate, list of components and power dissipation. Bias input and power input are split to allow linear conversion from buses lower than 1.2 V minimizing power losses. L6935 provides the application with an adjustable voltage from 0.5 V to 3.0 V with a voltage regulation accuracy of 1 %. soft-start is available to program the output voltage rise-time according to the external capacitor connected. Enable and Power Good functions make L6935 suitable for complex systems and programmable start-up sequencing. The current limit at 3 A protects the system during a short circuit. The current is sensed in the power DMOS in order to limit the power dissipation. Thermal shut down limits the internal temperature at 150 C with a hysteresis of 20 C.
Package VFQFPN20 Tape and reel Packing Tube
Applications

Motherboard Mobile PC Hand-held instruments PCMCIA cards Processors I/O Chipset and RAM supply
Table 1.
Device summary
Order codes
L6935 L6935TR
May 2008
Rev 1
1/20
www.st.com 20
Contents
L6935
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 5
Typical performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 5.2 5.3 5.4 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VIN vs VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4.1 5.4.2 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.1 6.1.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2
VIN, VBIAS and sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 8 9
Demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VFQFPN20 mechanical data and package dimensions . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
Typical application circuit and block diagram
L6935
1
1.1
Typical application circuit and block diagram
Application circuit
Figure 1. Typical application circuit - VIN = VBIAS
VIN
VIN
VBIAS
VOUT = 0.5V to 3.0V
VOUT
EN
CIN
EN SS
L6935
GND PAD
R1
ADJ PGOOD
COUT
R2
CSS PGOOD
L6935 Reference Schematic
Figure 2.
Typical application circuit - VIN VBIAS VBIAS
VIN = 0.75V to VBIAS
VIN
VBIAS
VOUT > 0.5V (*)
VOUT
EN CIN
EN
L6935
GND PAD
R1
ADJ PGOOD
COUT
SS
R2
CSS PGOOD
L6935 Reference Schematic (*) Vin may decrease until the minimum drop is reached. Conversely, Vout can rise untile the minimum drop is reached.
3/20
Typical application circuit and block diagram
L6935
1.2
Block diagram
Figure 3.
VIN VBIAS CHARGE PUMP CURRENT LIMIT
Block diagram
VREF SS REFERENCE 0.500V
+ ERROR AMPLIFIER DRIVER VOUT ADJ
EN
ENABLE
THERMAL SENSOR + 0.9 VREF -
PGOOD
GND
4/20
Pins description and connection diagrams
L6935
2
Pins description and connection diagrams
Figure 4. Pins connection (top view)
N.C. N.C. N.C. N.C. N.C.
10 9 11 12 13 14
15 1 16 17 18 19 20
2.1
Pin descriptions
Table 2.
Pin # 1 2 3, 4 5
Pins descriptions
Name N.C. GND N.C. PGOOD Not internally connected. Ground connection. Connect to PCB ground plane. Not internally connected. Power Good output flag: the pin is open drain and it is forced low if the output voltage is lower than 90 % of the programmed voltage. If not used, it can be left floating. Input bias supply. This pin supplies the internal logic to drive the power N-channel MOSFET that realize the voltage conversion. Connect directly to VIN or to a different supply ranging from VIN to 5 V. The voltage connected to this pin MUST always be higher or equal that VIN. Enables the device if a voltage higher than 1 V is applied. When pulled low, the device is in low-power consumption: everything inside the controller is kept OFF. See Section 6.2 for details about EN signal and power sequencing. Power supply voltage. This pin is connected to the drain of the internal N-channel MOSFET. Filter to GND with capacitor larger than the one used for VOUT. Not internally connected. Regulated output voltage. This pin is connected to the source of the internal N-mos. MLCC capacitor are supported. Filter to GND with capacitor smaller than the one used for VIN. Function
6
VBIAS
7
EN
8 to 10 11 to15 16 to 18
VIN N.C. VOUT
5/20
VOUT VOUT VOUT ADJ SS
VBIAS EN VIN VIN VIN
8 7 6 5 4
L6935
3 2
PGOOD N.C. N.C. GND N.C.
Pins description and connection diagrams Table 2.
Pin # 19
L6935
Pins descriptions (continued)
Name ADJ Function Feedback for the IC regulation. Connecting this pin through a voltage divider to VOUT, it is possible to program the output voltage between 0.5 V and 3.0 V. Soft-start pin. The soft-start time is programmed connecting an external capacitor CSS from this pin to GND. In steady state regulation, the voltage at this pin is 3.3 V. Ground connection. Connect to PCB GND Plane with enough VIAs to improve thermal conductivity.
20
SS
PAD
GND
6/20
Electrical specifications
L6935
3
3.1
Electrical specifications
Absolute maximum ratings
Table 3. Absolute maximum ratings
Parameter to GND to GND to GND to GND Value 5.5 6 -0.3 to 3.3 -0.3 to 1 1000 Unit V V V V V Symbol VIN VBIAS, EN, PGOOD SS, VOUT ADJ
Maximum withstanding voltage range test condition: CDF-AEC-Q100-002 "human body model" acceptance criteria: "normal performance"
3.2
Thermal data
Table 4.
Symbol RthJA TMAX TSTG TJ
Thermal data
Parameter Thermal resistance junction to ambient(1) Maximum junction temperature Storage temperature range Junction temperature range Value 55 150 -50 to 150 -25 to 150 Unit C/W C C C
1. Measured with the component mounted on demonstration board in free air (22 x 28.5 mm - 2 layer 70 m copper).
7/20
Electrical specifications
L6935
3.3
Table 5.
Symbol
Electrical characteristics
Electrical characteristics (VIN = 5 V, VBIAS = 5 V; TA = 25 C unless otherwise specified).
Parameter Test conditions Min Typ Max Unit
Recommended operating conditions VIN VBIAS Operating supply voltage UVLO Quiescent current IIN Shut-down current VIN = VBIAS VBIAS < 5 V VBIAS rising Iout = 0 A VIN = VBIAS = 3.3 V VIN = VBIAS = 5.0 V 2.3 5.0 VBIAS 1.275 3 25 40 V V mA A
Voltage regulation VOUT Output voltage Line regulation ADJ Load regulation Ripple rejection (1) RDS(on) Drain-to-source resistance Io = 0.1 A; VIN = 3.3 V; ADJ = OUT Vin = 3.30 V +/- 10 %; Io = 10 mA Vin = 4.50 V +/- 10 %; Io = 10 mA Vin = 3.3 V; Io = 100 mA to 3 A F = 100...120 Hz; Io = 10 mA Vin = 3 V; Vin = 2 Vpp; Vout = 1 V Io = 3 A 45 30 60 0.496 0.500 0.504 2.5 2.5 7 V mV mV dB m
Enable, SS and protections IOCP Current limiting Power Good threshold PGOOD Hysteresis Voltage low EN SS OT Enable threshold Soft start current Thermal shut-down I = -1 mA EN rising Vss = 0 V Temperature rising Hysteresis (1)
(1)
Vo = 1.8 V VADJ falling, wrt Ref.
3.15 77
3.50
3.85 85
A % %
10 0.4 1.05 1.0 150 20
V V A C C
1. Parameter guaranteed by design, not tested in production
8/20
Typical performances
L6935
4
Typical performances
Figure 5.
1.0 0.8 0.6 Output Voltage [%]
OC Threshold [A] 3.8
Output voltage and OC threshold vs junction temperature
4.0
0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -20 0 20 40 60 80 Temperature [C] 100 120 140
3.6
3.4
3.2
3.0 -40 -20 0 20 40 60 80 Temperature [C] 100 120 140
Figure 6.
4.0
Quiescent and shutdown current vs junction temperature
40 35
Quiescent Current [mA]
3.8
5 VIN Shutdown Current [uA 30 25 20 15 10 5 3 VIN
3.6
3.4
3.2
3.0 -40 -20 0 20 40 60 80 Temperature [C] 100 120 140
0 -40 -20 0 20 40 60 80 Temperature [C] 100 120 140
Figure 7.
0.2%
Line regulation
0.2%
VBIAS = VIN, VOUT = 0.5V
VBIAS = 1.4V, VOUT = 2V Line Regulation [%] 0.1%
Line Regulation [%]
0.1%
0.0%
0.0%
-0.1%
-0.1%
-0.2% 1.0 1.5 2.0 2.5 3.0 VIN [V] 3.5 4.0 4.5 5.0
-0.2% 2.0 2.5 3.0 3.5 VIN [V] 4.0 4.5 5.0
9/20
Typical performances Figure 8.
0.3% VBIAS = 1.4V, VIN = 2.6V, VOUT = 2V 0.2% Load Regulation [%]
Load Regulation [%] 0.2% 0.1% 0.0% -0.1% -0.2% -0.3%
L6935 Load regulation
0.3% VBIAS = VIN = 1.4V, VOUT = 0.5V
0.1% 0.0% -0.1% -0.2% -0.3% 0.0 0.5 1.0 1.5 2.0 2.5 Output Current [A]
0.0
0.5
1.0
1.5
2.0
2.5
Output Current [A]
10/20
Device description
L6935
5
5.1
Device description
Soft-start
L6935 implements a soft-start feature to smoothly charge the output filter avoiding high inrush currents to be required to the input power supply. The soft-start process begins as soon as VBIAS reaches UVLO and ENABLE is asserted. A constant current ISS = 1.0 A is sourced through the SS pin: connecting an external capacitor (CSS) to this pin a voltage ramp is implemented; the voltage ramp internally clamps the E.A. reference, resulting in a controlled slope for the output voltage. As the voltage on CSS reaches the VREF value the internal clamp is released. In this way, the soft-start process lasts for:
V REF 5 T SS = C SS ------------- = 5 10 C SS [ F ] I SS
where CSS is the external capacitor [F] and TSS is the soft-start time [sec.]. If the device is disabled (ENABLE low) and the VBIAS is still present, the SS pin is clamped to GND for a fixed time of about 50 s. in order to discharge the residual charge present on CSS: in this way, the device will be ready for a new SS process as ENABLE is asserted again. Figure 9 describes a typical soft-start process. Figure 9.
Vbias >1.1V
Soft start process diagram (left) and measured (right)
ENABLE >0.7V
ADJ 0.5V
Vout Programmed Vout
Programmed Tss ~50sec
11/20
Device description
L6935
5.2
Power Good
L6935 presents a PGOOD flag, an open drain output that is grounded during all the soft start procedure, and is left free when VOUT reaches 90 % of the programmed value. An hysteresis of 10 % is also provided in order to avoid false triggering due to the noise generated by the application. Figure 10 shows the PGOOD commutations. Figure 10. Power good window
5.3
VIN vs VBIAS
L6935 provides the flexibility to supply the internal logic (VBIAS) with a supply different than the power input (VIN). The aim of this feature is to provide low-drop regulation still having the supply voltage to correctly drive the internal power mosfet so optimizing the conversion. VIN drives only the drain of the power DMOS and it can be kept as low as possible (VIN > VOUT + VDROPmin), while VBIAS drives the control section. VBIAS must be typically higher than VIN.
5.4
Protections
L6935 is equipped with a set of protections in order to protect both the load and the device from electrical overstress. Each protection does not latch the device, that returns to work properly as the perturbation disappear.
5.4.1
Over-current protection
An over current protection is provided: if the current that flows through the power DMOS is greater than 3.5 A, the device adjust the power DMOS driving voltage in order to keep constant the delivered current (IOUT). Anyhow the output may drop also causing the PGOOD to be set low. Figure 11 show the way the OCP intervention: as the threshold value is reached by IOUT, the device forces a lower output current (~3.5 A).
12/20
Device description Figure 11. Over-current protection
L6935
5.4.2
Thermal protection
The device constantly monitors its internal temperature. As the silicon reaches a 150 C, the control circuit turns off the power DMOS, and stays off until a safe temperature of 150 - 20 = 130 C. Figure 12 shows how the over-temperature protection intervention. Figure 12. Over-temperature protection
13/20
Application information
L6935
6
Application information
L6935 is the best choice in smart linear regulator applications, due to its own small size, high power delivered and high regulation accuracy. Furthermore thermal shut-down and OCP guarantee the highest reliability for each application. VIN can be separated by VBIAS: in this way the device can regulate the output voltage even if VIN < VBIAS, resulting in a better performance. In fact, the power dissipated decreases as VIN get lower, according to the relationship PDISS = (VIN - VOUT) x IOUT.
6.1
6.1.1
Components selection
Input capacitor
The choice of the input capacitor value depends on the several factor such as load transient requirements, input source (battery or DC/DC converter) and its distance from the input capacitor. Generally speaking, a capacitor with the lowest ESR possible should be chosen: a value within the range [10 F; 100 F] can be sufficient in many cases.
6.1.2
Output capacitor
The choice of the output capacitor value basically depends on the load transient requirement. Output capacitor must be sized according to the dynamic requests of the load. A too small capacitor may exhibit huge voltage drop after a load transient is applied: a value greater than 10 F should be used. In order to guarantee a good reliability, at least X5R type should be used as I/O capacitors. Different kinds of input/output capacitors can be used: Table 6. shows a few tested examples. Table 6. Input/output capacitor selection guide
Manufacturer Murata - GRM31CR61ExxxK(1) Panasonic - ECJ3YB1AxxxM Panasonic - EEFFD0HxxxR Sanyo - 8TPE100MPC2 TDK - C3216X5R0JxxxMT Type MLCC, SMD1206, X5R MLCC, SMD1206, X5R SPCap - SMD7343 28 m ESR POSCAP, SMD6032 25 m ESR MLCC, SMD1210, X5R I/O cap. value Rated voltage 10...100 F 10...100 F 10...100 F 10...100 F 10...100 F 6.3 - 25 V 10 - 25 V 4-8V 6.3 - 25 V 6.3 V
1. xxx in the part numbers stands for 106 (10 F), 226 (22 F)... 105 (100 F)
14/20
Application information
L6935
6.2
VIN, VBIAS and sequencing
Different configurations for VIN and VBIAS are possibleand the power sequencing must consider the different timings in which the power suppliesbecomes available. In order to properly drive the device internal logic, it is reccomendedto control the sequence between EN signal and the VIN / VBIAS application: the device need to result being disabled when VBIAS crosses the UVLO threshols. Furthermore, in case of VIN <> VBIAS, the EN signal needs to be driven by the last-coming between the two supplies. It is reccomended to drive the EN pin with a resistor divider connected as reported into Figure 13 and Figure 14. Figure 13. Recommended circuit for VBIAS = VIN
VIN
VIN VBIAS
VOUT = 0.5V to 3.0V
VOUT
CIN
REH
EN SS
L6935
R1
PGOOD ADJ
RPG
COUT
GND PAD
PGOOD EN (OpenDrain Toggle **) REL CSS R2
** Drive EN with external Open-Drain Signal.
Figure 14. Reccomended circuit for VBIAS VIN
VBIAS
VIN (< VBIAS)
VIN
VBIAS
VOUT = 0.5V to 3.0V
VOUT
REH*
CIN
L6935
EN SS
R1
PGOOD ADJ
RPG
COUT
GND PAD
PGOOD EN (OpenDrain Toggle **) REL CSS R2
* EN Divider (REH) needs to be connected to the Last-Coming rail between VCC and VIN. ** Drive EN with external Open-Drain Signal.
15/20
Demonstration board description
L6935
7
Demonstration board description
Figure 15 and Figure 16 show the schematic and the layout of the demonstration board designed for L6935. VIN and VBIAS may be different and, in this case, R4 must not be mounted. C3 defines the Soft-Start timer, according to the relationship described in the Section 5.1. The value of the output divider R1 / R2 have to be designed in order to program the desired VOUT value, according to the following equation:
R1 V OUT = 0.5 1 + ------ R 2
Figure 15. Demonstration board schematic
VBIAS PGOOD
R4
C2
R5 6 16,17,18
VOUT
VIN EN
8, 9, 10 VIN 7 EN
SS
VBIAS
VOUT
R3 C6 R1 C5 R2 ADJ GND
L6935 PGOOD 5
GND PAD ADJ 19
C4
C1 C3
20
2
Figure 16. Demonstration board layout
16/20
Demonstration board description
L6935
Different values for R1 are available in order to program the value of VOUT (R2 = 10 k) VOUT = 0.50 VDC @ R1 = 0 VOUT = 0.75 VDC @ R1 = 5 k VOUT = 1.00 VDC @ R1 = 10 k VOUT = 1.25 VDC @ R1 = 15 k VOUT = 1.50 VDC @ R1 = 20 k VOUT = 3.00 VDC @ R1 = 50 k Table 7. L6935 demonstration board bill of material
Description Chip capacitor 100 nF - 6.3 V - X5R Murata chip capacitor (GRM31CR60J226K) 1206, X5R, 6.3-25V, 22 F Murata chip capacitor (GRM31CR61E106K) 1206, X5R, 6.3-25V, 10 F Not mounted Chip resistor 15 k +/-0.1% - 1/16 W Chip resistor 10 k +/-0.1% - 1/16 W Chip resistor 10 k +/-5% - 1/16 W Chip resistor 0
Reference C1, C2, c3 C4 C5 C6 R1 R2 R3, R5 R4
17/20
VFQFPN20 mechanical data and package dimensions
L6935
8
VFQFPN20 mechanical data and package dimensions
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 17. VFQFPN20 mechanical data and package dimensions
DIMENSIONS REF.
A A1 A2 A3 b D D2 E E2 e L ddd 0.18 3.85 2.70 3.85 2.70 0.45 0.3
mm MIN.
0.80
mils TYP. MAX.
TYP. MAX. MIN.
0.90 0.02 0.65 0.25 0.23 4.00 2.80 4.00 2.80 0.50 0.4 0.30 4.15 2.90 4.15 2.90 0.55 0.5 0.08 7.087 1.00 0.05 1.00
PACKAGE AND PACKING INFORMATION
31.496 35.433 39.370 0.787 1.969
25.591 39.370 9.843 9.055 11.811
Very Fine Quad Flat Package No lead
Weight: not available
151.57 157.48 163.39 106.30 110.24 114.17 151.57 157.48 163.39 106.30 110.24 114.17 17.717 19.685 21.654 11.811 15.748 19.685 3.150
VFQFPN20 (4x4x1.00mm)
18/20
Revision history
L6935
9
Revision history
Table 8.
Date 20-May-2008
Document revision history
Revision 1 Initial release Changes
19/20
L6935
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