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Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer Product Features
* * * * * * * * * * * 180MHz Clock Support TM Supports PowerPC , Intel and RISC Processors 9 Clock Outputs: Frequency Configurable Two Reference Clock Inputs for Dynamic Toggling Oscillator or PECL Reference Input Output Disable Control Spread Spectrum Compatible 3.3V Power Supply Pin Compatible with MPC951 Industrial Temp. Range: -40C to +85C 32-Pin TQFP Package
Frequency Table
SEL (A:D) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 QA VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 QB VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8
Table 1
VCO 200480MHz
QC (0,1) VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8
QD (0:4) VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8
Block Diagram
SELA PLL_EN TCLK REF_SEL
PECL_CLK PECL_CLK#
Phase Detector
2/ 4
QA
Pin Configuration
REF_SEL
LPF
4/ 8
QB
PLL_EN
VDDC 27
TCLK
VSS
FB_IN SELB SELC MR/OE#
4/ 8
QC0
32
31
30
29
28
26
Power-On Reset 4/ 8 QD0 QD1
SELD
QD2 QD3 QD4
VDD FB_IN SELA SELB SELC SELD VSS PECL_CLK
1 2 3 4 5 6 7 8 9
25 24 23 22 21 20 19 18 17 16
QC1
VSS
QA
QB
Z9951
10 11 12 13 14 15
QC0 VDDC QC1 VSS QD0 VDDC QD1 VSS
PECL_CLK#
QD4
VSS
QD3
MR/OE#
VDDC
Figure 1
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07084 Rev. *B
VDDC
QD2
12/22/2002 Page 1 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer Pin Description
PIN 8 9 30 28 26 22, 24 12, 14, 16, 18, 20 2 10 NAME PECL_CLK PECL_CLK# TCLK QA QB QC(1,0) QD(4:0) FB_IN MR/OE# PWR I/O I I I O O O O I I TYPE PU Description PECL Input Clock. PECL Input Clock. External Test Clock Input. Clock Output. See Frequency Table. Clock Output. See Frequency Table. Clock Outputs. See Frequency Table. Clock Outputs. See Frequency Table.
Feedback Clock Input. Connect to an output for normal operation.
VDDC VDDC VDDC VDDC
PD
31 32 3, 4, 5, 6
PLL_EN REF_SEL SEL(A:D)
I I I
11, 15, 19, 23, 27 1 7, 13, 17, 21, 25, 29
VDDC VDD VSS
Master Reset/Output Enable Input. When asserted high, resets all of the internal flip-flops and also disables all of the outputs. When pulled low, releases the internal flip-flops from reset and enables all of the outputs. PLL Enable Input. When asserted high, PLL is enabled. And when set low, PLL is bypassed. Reference Select Input. When high, TCLK is the reference clock and when low, PECL clock is selected. Frequency Select Inputs. See Frequency Table. If SEL_ = 1, then QA divider = /4, QB:D divider = /8 If SEL_ = 0, then QA divider = /2, QB:D divider = /4 3.3V Power Supply for Output Clock Buffers. 3.3V Power Supply for PLL Common Ground
PD = Internal Pull-Down, PU = Internal Pull-Up.
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002 Page 2 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS - 0.3V Maximum Input Voltage Relative to VDD: VDD + 0.3V Storage Temperature: Operating Temperature: Maximum ESD protection Maximum Power Supply: Maximum Input Current: -65C to + 150C -40C to +85C 2KV 5.5V 20mA VSS<(Vin or Vout)DC Parameters
Characteristic Input Low Voltage Input High Voltage Input Low Current (@VIL = VSS) Input High Current (@VIL =VDD) Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Output Low Voltage Output High Voltage Quiescent Supply Current PLL Supply Current Input Capacitance Symbol VIL VIH IIL IIH VPP VCMR VOL VOH IDDC IDD Cin 2.4 15 15 20 20 4 Min VSS 2.0 Typ Max 0.8 VDD -120 120 1000 VDD0.6 0.5 Units V V A A mV V V V mA mA pF IOL = 40mA, Note 4 IOH = -40mA, Note 4 All VDDC and VDD VDD only Conditions
Note 2 Note 3
300 VDD2.0 -
VDD = VDDC = 3.3V 5%, TA = -40C to +85C Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Note 2: Inputs have pull-up, pull-down resistors that affect input current. Note 3: The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the VCMR range and the input lies within the VPP specification. Note 4: Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. Output buffers are dual staged to control drive strength in order to reduce over / under shoot.
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Document#: 38-07084 Rev. *B
12/22/2002 Page 3 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer AC Parameters1
SYMBOL
Tr / Tf Fref FrefDC Fvco Tlock Tr / Tf Fout
PARAMETER
TCLK Input Rise / Fall Reference Input Frequency Reference Input Duty Cycle PLL VCO Lock Range Maximum PLL lock Time Output Clocks Rise / Fall Time
4,5
MIN
Note 2 25 200 0.10 -
TYP
MAX
3.0 Note 2 75 480 10 1.0 180 120 60
UNITS
ns MHz % MHz ms ns MHz
CONDITIONS
0.8V to 2.0V QA = (/2) QA/QB = (/4) QB = (/8)
Maximum Output Frequency
FoutDC tpZL, tpZH tpLZ, tpHZ TCCJ Tpd TSKEW0
Output Duty Cycle
4,5
TCYCLE/2 - 1
TCYCLE/2 + 1 6 7
ns ns ns ps ps ps ps Fref = 50MHz, Feedback = VCO/8
Output enable time (all outputs) Output disable time (all outputs) Cycle to Cycle Jitter (peak to peak) TCLK to FB_IN Delay
3 3 4,5 4,5
+/- 100 50 -950 250 -770 200 400 -600 350
PECL_CLK to FB_IN Delay
Any Output to Any Output Skew
VDD = VDDC = 3.3V +/- 5%, TA = -40C to +85C Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. Note 2: Maximum and minimum input reference is limited by the VCO lock range. Note 3: The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the minimum limits with an increase/decrease of the input reference clock period. Note 4: Driving series or parallel terminator 50 (or 50 to VDD/2) transmission lines. Note 5: Outputs loaded with 30pF each
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002 Page 4 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer Description
The Z9951 has an integrated PLL that provides low skew and low jitter clock outputs for high performance microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies from 25MHz to 180MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by SEL(A:D) select inputs, see Table 2. The VCO frequency is then divided down to provide the required output frequencies. The use of even dividers ensures that the output duty cycle remains at 50%.
SELA 0 1
QA /2 /4
SELB 0 1
QB /4 /8
SELC 0 1
QC /4 /8
SELD 0 1
QD /4 /8
Table 2
Zero Delay Buffer
When used as a zero delay buffer the Z9951 will likely be in a nested clock tree application. For these applications the Z9951 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The Z9951 then can lock onto the LVPECL reference and translate with near zero delay to low skew outputs. By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the Z9951 is a function of the configuration used.
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002 Page 5 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Package Drawing and Dimensions 32 Pin TQFP Outline Dimensions
INCHES SYMBOL A D A1 A2 D D1 b D1 12 A1 A L e b e L 0.018 MIN 0.002 0.037 0.012 NOM 0.354 0.276 0.031 BSC 0.030 0.45 MAX 0.047 0.006 0.041 0.018 MIN 0.05 0.95 0.30 MILLIMETERS NOM 9.00 7.00 0.80 BSC 0.75 MAX 1.20 0.15 1.05 0.45
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Document#: 38-07084 Rev. *B
12/22/2002 Page 6 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer Ordering Information
Part Number Package Type Production Flow Z9951AA 32 PIN TQFP Industrial, -40C to +85C Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress Z9951AA Date Code, Lot #
Z9951AA
Package A = TQFP Revision Device Number
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002 Page 7 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Notice
Cypress Semiconductor Corp. reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corp. assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corp. for the use of its products in the life supporting and medical applications.
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002 Page 8 of 9
Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Document Title: Z9951 3.3V, 180 MHz, Multi-Output Zero Delay Buffer Document Number: 38-07084
Rev. ECN No. ** 107120 *A 108063
Issue Date 06/12/01 07/03/01
Orig. of Change IKA NDP
Description of Change Convert from IMI to Cypress Changed Commercial to Industrial (See page 7) Delete Pull down in pin 9,10,30& 32; Delete Pull up in pin 3,4,5,6, & 31 (See page 2) Add power up requirements to maximum ratings information
*B
122769
12/22/02
RBI
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002 Page 9 of 9

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