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| 350 mA, Low VIN, Low Quiescent Current, CMOS Linear Regulator ADP130 FEATURES 350 mA maximum output current Input voltage supply range VBIAS = 2.3 V to 5.5 V VIN = 1.2 V to 3.6 V 2.3 V < VIN < 3.6 V, VIN can be tied to VBIAS Very low dropout voltage: 17 mV @ 100 mA load Low quiescent current: 25 A @ no load Low shutdown current: <1 A 1% accuracy @ 25C Excellent PSRR performance: 70 dB @ 10 kHz Excellent load/line transient response Optimized for small 1 F ceramic capacitors Current limit and thermal overload protection Logic controlled enable 5-lead TSOT package TYPICAL APPLICATION CIRCUITS VIN = 1.8V 1F + 2 1 VIN VOUT 5 VOUT = 1.2V 1F + ADP130 GND 3 EN VBIAS 4 VBIAS = 3.6V 1F 06963-001 + Figure 1. VIN = 2.8V 1F + 1 VIN VOUT 5 VOUT = 1.8V 1F + ADP130 2 GND VBIAS = 5V 1F 06963-002 APPLICATIONS Mobile phones Digital camera and audio devices Portable and battery-powered equipment Post dc-to-dc regulation 3 EN VBIAS 4 + Figure 2. GENERAL DESCRIPTION The ADP130 is a low quiescent current, low dropout linear regulator. It is designed to operate in dual-supply mode with an input voltage as low as 1.2 V to increase efficiency and provide up to 350 mA of output current. The low 17 mV dropout voltage at a 100 mA load improves efficiency and allows operation over a wider input voltage range. A dual-supply power solution typically improves conversion efficiency over a single-supply solution because the higher VBIAS supply powers the part, and the lower VIN supply delivers current to the load. The power dissipated in the device is thereby reduced. The ADP130 is optimized for stable operation with small 1 F ceramic output capacitors. The ADP130 delivers good transient performance with minimal board area. The ADP130 is available in the following 31 fixed output voltage options: * * 0.80 V to 2.00 V in 50 mV steps 1.875 V, 2.25 V, 2.50 V, 2.775 V, 2.80 V, and 3.0 V The ADP130 has a typical internal soft start time of 200 s. Shortcircuit protection and thermal overload protection circuits prevent damage in adverse conditions. The ADP130 is available in a tiny 5-lead TSOT package for the smallest footprint solution to meet a variety of portable power applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved. ADP130 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Typical Application Circuits............................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Input and Output Capacitor, Recommended Specifications.. 4 Absolute Maximum Ratings............................................................ 5 Thermal Data ................................................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ..............................................7 Theory of Operation ...................................................................... 12 Applications Information .............................................................. 13 Capacitor Selection .................................................................... 13 Undervoltage Lockout ............................................................... 14 Enable Feature ............................................................................ 14 Current Limit and Thermal Overload Protection ................. 15 Thermal Considerations............................................................ 15 Junction Temperature Calculations ......................................... 16 Printed Circuit Board Layout Considerations ....................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18 REVISION HISTORY 7/08--Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADP130 SPECIFICATIONS VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 10 mA, CIN = 1 F, COUT = 1 F, CBIAS = 1 F, TA = 25C, unless otherwise noted. Table 1. Parameter INPUT VOLTAGE RANGE BIAS VOLTAGE RANGE OPERATING SUPPLY CURRENT Symbol VIN VBIAS IVIN 1 Conditions TJ = -40C to +125C TJ = -40C to +125C IOUT = 0 A IOUT = 0 A, TJ = -40C to +125C IOUT = 1 mA IOUT = 1 mA, TJ = -40C to +125C IOUT = 100 mA IOUT = 100 mA, TJ = -40C to +125C IOUT = 350 mA IOUT = 350 mA, TJ = -40C to +125C TJ = -40C to +125C EN = GND EN = GND, TJ = -40C to +85C EN = GND, TJ = +85C to +125C EN = GND EN = GND, TJ = -40C to +125C IOUT = 10 mA 1 mA < IOUT < 350 mA, VIN = (VOUT + 0.4 V) to 3.6 V 1 mA < IOUT < 350 mA, VIN = (VOUT + 0.4 V) to 3.6 V, TJ = -40C to +125C VIN = (VOUT + 0.4 V) to 3.6 V, TJ = -40C to +125C IOUT = 10 mA to 350 mA IOUT = 10 mA to 350 mA, TJ = -40C to +125C IOUT = 10 mA, VBIAS = 2.3 V, VOUT = 3 V IOUT = 10 mA, VBIAS = 2.3 V, VOUT = 3 V, TJ = -40C to +125C IOUT = 100 mA, VBIAS = 2.3 V, VOUT = 3 V IOUT = 100 mA, VBIAS = 2.3 V, VOUT = 3 V, TJ = -40C to +125C IOUT = 350 mA, VBIAS = 2.3 V, VOUT = 3 V IOUT = 350 mA, VBIAS = 2.3 V, VOUT = 3 V, TJ = -40C to +125C VOUT = 1.2 V Min 1.2 2.3 Typ Max 3.6 5.5 44 40 58 100 130 160 220 16 28 0.1 1.0 20 0.1 -1 -2 -3 -0.10 0.001 0.005 2 3.5 17 28 70 100 200 550 150 15 1.2 0.4 0.1 1 2.1 1.5 180 1.0 +1 +2 +3 +0.10 Unit V V A A A A A A A A A A A A A A A % % % %/ V %/A %/A mV mV mV mV mV mV s mA C C V V A A V V mV 25 BIAS OPERATING CURRENT SHUTDOWN CURRENT IBIAS ISD-VIN ISD-VBIAS FIXED OUTPUT VOLTAGE ACCURACY VOUT LINE REGULATION LOAD REGULATION 2 DROPOUT VOLTAGE 3 VOUT/VIN VOUT/IOUT VDROPOUT START-UP TIME 4 CURRENT LIMIT THRESHOLD 5 THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis EN INPUT EN Input Logic High EN Input Logic Low EN Input Leakage Current UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling Hysteresis TSTART-UP ILIMIT TSSD TSSD-HYS VIH VIL VI-LEAKAGE UVLO UVLORISE UVLOFALL UVLOHYS 400 TJ rising 1000 2.3 V VBIAS 5.5 V 2.3 V VBIAS 5.5 V EN = BIAS or GND EN = BIAS or GND, TJ = -40C to +125C TJ = -40C to +125C TJ = -40C to +125C Rev. 0 | Page 3 of 20 ADP130 Parameter OUTPUT NOISE Symbol OUTNOISE Conditions 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 0.8 V 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.5 V 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 2.5 V 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 3.0 V Modulated bias, 10 kHz, VOUT = 3.0 V, VIN = 3.6 V, VBIAS = 5 V Modulated bias, 100 kHz, VOUT = 3.0 V, VIN = 3.6 V, VBIAS = 5 V Modulated VIN, 10 kHz, VOUT = 1.2 V, VIN = VOUT + 1 V, VBIAS = 5 V Modulated VIN, 100 kHz, VOUT = 1.2 V, VIN = VOUT + 1 V, VBIAS = 5 V Modulated VIN, 10 kHz, VOUT = 0.8 V, VIN = VOUT + 1 V, VBIAS = 5 V Modulated VIN, 100 kHz, VOUT = 0.8 V, VIN = VOUT + 1 V, VBIAS = 5 V Min Typ 29 38 43 61 77 70 53 70 54 70 55 Max Unit V rms V rms V rms V rms V rms dB dB dB dB dB dB POWER SUPPLY REJECTION RATIO PSRR 1 2 IVIN = IGND - IBIAS, where IGND is the current flowing from the GND pin. Based on an endpoint calculation using 1 mA and 350 mA loads. 3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 1.3 V. 4 Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of its nominal value. 5 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 2.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 2.0 V, or 1.8 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter MINIMUM INPUT AND OUTPUT CAPACITANCE 1 CAPACITOR ESR 1 Symbol CMIN RESR Conditions TJ = -40C to +125C TJ = -40C to +125C Min 0.70 .001 Typ 1 Max Unit F 1 The minimum input and output capacitance should be >0.70 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. 0 | Page 4 of 20 ADP130 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN to GND VBIAS to GND EN to GND VOUT to GND Storage Temperature Range Operating Temperature Range Operating Junction Temperature Lead Temperature (Soldering, 10 sec) Rating -0.3 V to +3.6 V -0.3 V to +6 V -0.3 V to +6 V -0.3 V to VIN -65C to +150C -40C to +125C 125C 300C The junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a four-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a four-layer, 4 in x 3 in circuit board. For details about board construction, refer to JEDEC JESD51-7. JB is the junction-to-board thermal characterization parameter with units of C/W. JB of the package is based on modeling and calculation using a four-layer board. The JEDEC JESD51-12 document, Guidelines for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path, as in thermal resistance (JB). Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make JB more useful in real world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD), using the following formula: TJ = TB + (PD x JB) Refer to the JEDEC JESD51-8 and JESD51-12 documents for more detailed information about JB. Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply only individually, not in combination. The ADP130 may be damaged when junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-toambient thermal resistance of the package (JA). TJ is calculated using the following formula: TJ = TA + (PD x JA) THERMAL RESISTANCE JA and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 5-Lead TSOT JA 170 JB 43 Unit C/W ESD CAUTION Rev. 0 | Page 5 of 20 ADP130 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 1 5 VOUT GND 2 ADP130 TOP VIEW (Not to Scale) 06963-003 EN 3 4 VBIAS Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic VIN GND EN VBIAS VOUT Description Regulator Input Supply. Bypass VIN to GND with a capacitor of 1 F or greater. Ground. Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VBIAS Bias Input Supply. Connect a capacitor of 1 F or greater between VBIAS and GND. Regulated Output Voltage. Bypass VOUT to GND with a capacitor of 1 F or greater. Rev. 0 | Page 6 of 20 ADP130 TYPICAL PERFORMANCE CHARACTERISTICS VBIAS = 5 V, VIN = 2.2 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = CBIAS = 1 F, TA = 25C, unless otherwise noted. 1.805 LOAD = 1mA LOAD = 10mA 200 180 160 LOAD = 100mA LOAD = 200mA LOAD = 350mA 1.800 IVIN CURRENT (A) 1.795 VOUT (V) LOAD = 50mA LOAD = 100mA LOAD = 200mA 140 120 100 80 60 40 20 LOAD = 1mA LOAD = 10mA LOAD = 50mA 06963-007 1.790 LOAD = 350mA 1.785 1.780 -40 -5 +25 +85 +125 06963-004 1.775 0 -40 -5 +25 +85 +125 JUNCTION TEMPERATURE (C) JUNCTION TEMPERATURE (C) Figure 4. Output Voltage vs. Junction Temperature Figure 7. IVIN Current vs. Junction Temperature 1.805 30 1.803 25 BIAS CURRENT (A) LOAD = 350mA LOAD = 200mA LOAD = 100mA LOAD = 50mA LOAD = 10mA LOAD = 1mA 20 VOUT (V) 1.801 15 1.799 10 1.797 5 06963-005 1 10 ILOAD (mA) 100 1000 JUNCTION TEMPERATURE (C) Figure 5. Output Voltage vs. Load Current Figure 8. Bias Current vs. Junction Temperature 1.805 1.804 1.803 1.802 LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA LOAD = 350mA 180 160 140 IVIN CURRENT (A) 120 100 80 60 40 06963-009 VOUT (V) 1.801 1.800 1.799 1.798 1.797 1.796 2.4 2.6 2.8 3.0 3.2 3.4 3.6 06963-006 20 0 1 10 ILOAD (mA) 1.795 2.2 100 1000 VIN (V) Figure 6. Output Voltage vs. Input Voltage Figure 9. IVIN Current vs. Load Current Rev. 0 | Page 7 of 20 06963-008 1.795 0 -40 -5 +25 +85 +125 ADP130 25 60 VOUT = 3V TA = 25C 20 50 DROPOUT VOLTAGE (mV) 06963-010 BIAS CURRENT (A) 40 15 30 10 20 5 10 ILOAD (mA) ILOAD (mA) Figure 10. Bias Current vs. Load Current Figure 13. Dropout Voltage vs. Load Current, VOUT = 3 V 200 180 160 GROUND CURRENT (A) 80 70 TA = 25C 140 120 100 80 60 40 20 LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA 2.4 2.6 2.8 3.0 3.2 3.4 3.6 06963-011 DROPOUT VOLTAGE (mV) LOAD = 350mA LOAD = 200mA 60 VOUT = 1.8V 50 40 30 20 10 0 10 VOUT = 3.0V VIN (V) ILOAD (mA) Figure 11. Ground Current vs. Input Voltage Figure 14. Dropout Voltage vs. Output Voltage and Load Current 25 3.05 3.00 LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA LOAD = 350mA 20 2.95 BIAS CURRENT (A) 10 LOAD = 1mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA LOAD = 350mA VOUT (V) 15 2.90 2.85 2.80 2.75 2.70 5 06963-012 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 VIN (V) VIN (V) Figure 12. Bias Current vs. Input Voltage Figure 15. Output Voltage vs. Input Voltage (in Dropout), VOUT = 3 V Rev. 0 | Page 8 of 20 06963-015 0 2.2 2.65 2.75 06963-014 0 2.2 100 1000 06963-013 0 1 10 100 1000 0 10 100 1000 ADP130 600 0 -10 500 -20 -30 LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA LOAD = 350mA VRIPPLE = 50mV VIN = 2.8V VOUT = 1.8V COUT = 1F GROUND CURRENT (A) 400 PSRR (dB) -40 -50 -60 -70 -80 -90 LOAD = 100A LOAD = 10mA LOAD = 100mA LOAD = 350mA 06963-019 06963-021 06963-020 300 200 100 06963-016 0 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 -100 10 100 1k 10k 100k 1M 10M VIN (V) FREQUENCY (Hz) Figure 16. Ground Current vs. Input Voltage (in Dropout), VOUT = 3 V Figure 19. Power Supply Rejection Ratio vs. Frequency, VIN Input 18 0 -10 17 -20 LOAD = 350mA LOAD = 200mA LOAD = 100mA LOAD = 50mA LOAD = 10mA VRIPPLE = 50mV VIN = 2.2V VOUT = 1.2V COUT = 1F BIAS CURRENT (A) -30 PSRR (dB) 3.00 3.05 3.10 3.15 3.20 06963-017 16 -40 -50 -60 -70 15 14 13 2.75 2.80 2.85 2.90 2.95 LOAD = 100A LOAD = 10mA -90 LOAD = 100mA LOAD = 350mA -100 10 100 -80 1k 10k 100k 1M 10M VIN (V) FREQUENCY (Hz) Figure 17. Bias Current vs. Input Voltage (in Dropout), VOUT = 3 V Figure 20. Power Supply Rejection Ratio vs. Frequency, VIN Input 0 -10 -20 -30 VRIPPLE = 50mV VIN = 3.6V VOUT = 3.0V COUT = 1F 0 -20 VRIPPLE = 50mV VIN = 1.8V VOUT = 0.8V COUT = 1F LOAD = 100A LOAD = 10mA LOAD = 100mA LOAD = 350mA -40 PSRR (dB) -50 -60 -70 -80 -90 -100 10 LOAD = 100A LOAD = 10mA LOAD = 100mA LOAD = 350mA 100 1k 10k 100k 1M 10M 06963-018 PSRR (dB) -40 -60 -80 -100 -120 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 18. Power Supply Rejection Ratio vs. Frequency, VIN Input Figure 21. Power Supply Rejection Ratio vs. Frequency, VIN Input Rev. 0 | Page 9 of 20 ADP130 0 VRIPPLE = 50mV VOUT = 1.8V IOUT = 100mA COUT = 1F 0 -10 -20 -30 1V HEADROOM 0.5V HEADROOM VRIPPLE = 50mV VIN = 2.2V VOUT = 1.2V COUT = 1F LOAD = 350mA LOAD = 100mA LOAD = 10mA LOAD = 100A -20 -40 PSRR (dB) PSRR (dB) -40 -50 -60 -70 -80 -90 -60 -80 -100 100 1k 10k 100k 1M 10M 06963-022 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 22. Power Supply Rejection Ratio vs. Headroom, VIN Input Figure 25. Power Supply Rejection Ratio vs. Frequency, VBIAS Input 0 -10 -20 -30 VRIPPLE = 50mV VIN = 3.6V VOUT = 3.0V COUT = 1F 0 -10 -20 LOAD = 350mA LOAD = 100mA LOAD = 10mA LOAD = 100A -30 VRIPPLE = 50mV VIN = 1.8V VOUT = 0.8V COUT = 1F PSRR (dB) -40 -50 -60 -70 -80 PSRR (dB) -40 -50 -60 -70 -80 LOAD = 350mA LOAD = 100mA LOAD = 10mA LOAD = 100A 06963-023 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Power Supply Rejection Ratio vs. Frequency, VBIAS Input Figure 26. Power Supply Rejection Ratio vs. Frequency, VBIAS Input 0 -10 -20 -30 VRIPPLE = 50mV VIN = 2.8V VOUT = 1.8V COUT = 1F LOAD = 350mA LOAD = 100mA LOAD = 10mA LOAD = 100A 10 3.0V 1 1.5V PSRR (dB) -40 -50 -60 -70 -80 -90 10 100 1k NOISE (V/Hz) 0.8V 0.1 10k 100k 1M 10M 06963-024 100 1k FREQUENCY (Hz) 10k 100k FREQUENCY (Hz) Figure 24. Power Supply Rejection Ratio vs. Frequency, VBIAS Input Figure 27. Noise Spectrum vs. VOUT Rev. 0 | Page 10 of 20 06963-027 -100 0.01 10 06963-026 -90 10 100 1k 10k 100k 1M 10M -90 10 06963-025 -120 10 -100 ADP130 90 80 70 NOISE (V rms) 1.8V 2.5V 3.0V VIN 3V TO 3.5V INPUT VOLTAGE STEP 2V/s 60 50 40 2 30 20 10 0.1 1 10 ILOAD (mA) 100 1000 06963-028 0.8V 1.2V 1.5V 1 VOUT 5mV/DIV 0 0.01 CH1 500mV CH2 5mV M20s T 10.20% A CH1 3.37V Figure 28. Output Noise vs. Load Current and Output Voltage Figure 31. VIN Line Transient Response, VBIAS = 5 V, IOUT = 1 mA 1 ILOAD 1mA TO 350mA LOAD STEP 2.5A/s 200mA/DIV VIN 3V TO 3.5V INPUT VOLTAGE STEP 2V/s 2 2 VOUT 50mV/DIV 06963-029 VOUT 5mV/DIV 1 CH1 200mA CH2 50mV M40s T 10.40% A CH1 92mA CH1 500mV CH2 5mV M20s T 10.20% A CH1 3.27V Figure 29. Load Transient Response Figure 32. VIN Line Transient Response, VBIAS = 5 V, IOUT = 350 mA VIN = 3.6V VBIAS 3V TO 3.5V INPUT VOLTAGE STEP 2V/s 500mV/DIV 1 2 VOUT 2mV/DIV 1 CH1 500mV CH2 2mV M40s T 10.20% A CH1 3.35V Figure 30. VBIAS Line Transient Response, VIN = 3.6 V, IOUT = 350 mA 06963-030 Rev. 0 | Page 11 of 20 06963-032 06963-031 ADP130 THEORY OF OPERATION The ADP130 is a low dropout, linear regulator that uses an advanced proprietary architecture to achieve low quiescent current and high efficiency regulation. It also provides high power supply rejection ratio (PSRR) and excellent line and load transient response using a small 1 F ceramic output capacitor. The device operates from a 2.3 V to 5.5 V bias rail and a 1.2 V to 3.6 V input rail to provide up to 350 mA of output current. Supply current in shutdown mode is typically less than 1 A. Internally, the ADP130 consists of a reference, an error amplifier, a feedback voltage divider, and a pass device. The output current is delivered via the pass device, which is controlled by the error amplifier, forming a negative feedback system that ideally drives the feedback voltage to equal the reference voltage. If the feedback voltage is lower than the reference voltage, the negative feedback drives more current, increasing the output voltage. If the feedback voltage is higher than the reference voltage, the negative feedback drives less current, decreasing the output voltage. The VBIAS pin is the positive supply for all circuitry except the pass device. The ADP130 has an internal soft start that limits the output voltage ramp period to approximately 200 s. All internal devices are controlled by the enable pin, EN. When EN is high, the output is on; when EN is low, the output is off. VIN R1 VOUT GND SHORT-CIRCUIT, UVLO, AND THERMAL PROTECT 0.5V REF VBIAS EN SHUTDOWN R2 06963-033 Figure 33. Internal Block Diagram The ADP130 is available in 31 output voltage options, ranging from 0.8 V to 3.0 V. The ADP130 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on. When EN is low, VOUT turns off. For automatic startup, EN can be tied to VBIAS. Rev. 0 | Page 12 of 20 ADP130 APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor The ADP130 is designed for operation with small, space-saving ceramic capacitors, but it functions with most commonly used capacitors as long as care is taken regarding the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure stability of the ADP130. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP130 to large changes in load current. Figure 34 and Figure 35 show the transient responses for output capacitance values of 1 F and 10 F, respectively. ILOAD 1 Input Bypass Capacitor Connecting a 1 F capacitor from VIN to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance are encountered. If >1 F of output capacitance is required, the input capacitor should be increased to match it. Bias Capacitor Connecting a 1 F capacitor from VBIAS to GND reduces the circuit sensitivity to PCB layout, especially when long input traces or high source impedance are encountered. Input, Bias, and Output Capacitor Properties Any good quality ceramic capacitor can be used with the ADP130, as long as it meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended for use with any LDO, due to their poor temperature and dc bias characteristics. Figure 36 shows the capacitance vs. voltage bias characteristics of the 0402 1F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40 to +85C temperature range and is not a function of the package or voltage rating. 1.2 1mA TO 350mA LOAD STEP 2.5A/s 200mA/DIV 2 VOUT 50mV/DIV -VOUT = 1.8V CIN = COUT = 1F CH1 200mA CH2 50mV M400ns T 14% A CH1 192mA 06963-034 Figure 34. Output Transient Response, COUT = 1 F ILOAD 1mA TO 350mA LOAD STEP 2.5A/s 200mA/DIV 1.0 1 CAPACITANCE (F) 06963-035 0.8 0.6 2 VOUT 50mV/DIV -VOUT = 1.8V CIN = COUT = 10F CH1 200mA CH2 50mV M400ns T 13% A CH1 160mA 0.4 0.2 0 2 4 6 8 10 VOLTAGE (V) Figure 35. Output Transient Response, COUT = 10 F Figure 36. Capacitance vs. Voltage Characteristics Rev. 0 | Page 13 of 20 06963-036 0 ADP130 Use Equation 1 to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = COUT x (1 - TEMPCO) x (1 - TOL) where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT = 0.94 F at 1.8 V, as shown in Figure 36. Substituting these values in Equation 1 yields the following: CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP130, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. (1) As shown in Figure 37, the EN pin has built-in hysteresis. This prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. The EN pin active and inactive thresholds are derived from the VIN voltage. Therefore, these thresholds vary with changing input voltage. Figure 38 shows typical EN active and inactive thresholds when the VBIAS voltage varies from 2.3 V to 5.5 V. 1.10 1.05 1.00 0.95 THRESHOLD (V) 0.90 EN ACTIVE 0.85 0.80 0.75 0.70 0.65 2.7 3.1 3.5 3.9 VBIAS (V) 4.3 4.7 5.1 5.5 06963-038 06963-039 EN INACTIVE 0.60 2.3 Figure 38. Typical EN Pin Thresholds vs. Input UNDERVOLTAGE LOCKOUT The ADP130 has an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 2.1 V. This ensures that the ADP130 inputs and the output behave in a predictable manner during power-up. ENABLE FEATURE The ADP130 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 37, when a rising voltage on EN crosses the active threshold, VOUT turns on. When a falling voltage on EN crosses the inactive threshold, VOUT turns off. -VOUT = 1.8V CIN = COUT = 1F The ADP130 uses an internal soft start to limit the inrush current when the output is enabled. The start-up time for the 0.8 V option is approximately 180 s from the time at which the EN active threshold is crossed to when the output reaches 90% of its final value. The start-up time depends somewhat on the output voltage setting and increases slightly as the output voltage increases. 5.0 4.5 4.0 3.5 ENABLE 3.0V 1.8V 1.2V 0.8V VBIAS = 2.3V VIN = 3.6V ILOAD = 10mA VOLTAGE (V) 3.0 2.5 2.0 1.5 VOUT 500mV/DIV 1.0 0.5 0 0 100 200 300 400 500 600 700 800 900 1000 EN 500mV/DIV TIME (s) Figure 39. Typical Start-Up Time 06963-037 1 2 CH1 500mV CH2 500mV M10ms T 30% A CH2 640mV Figure 37. Typical EN Pin Operation Rev. 0 | Page 14 of 20 ADP130 CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION The ADP130 is protected against damage due to excessive power dissipation by current limit and thermal overload protection circuits. The ADP130 is designed to current limit when the output load reaches 550 mA (typical). When the output load exceeds 550 mA, the output voltage is reduced to maintain a constant current limit. Thermal overload protection limits the junction temperature to a maximum of 150C typical. Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150C, the output is turned off, reducing output current to zero. When the junction temperature drops below 135C, the output is turned on again and output current is restored to its nominal value. Consider the case where a hard short from VOUT to GND occurs. At first, the ADP130 current limits so that only 550 mA is conducted into the short. If self-heating of the junction is great enough to cause its temperature to rise above 150C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 135C, the output turns on and conducts 550 mA into the short, again causing the junction temperature to rise above 150C. This thermal oscillation between 135C and 150C causes a current oscillation between 550 mA and 0 mA that continues as long as the short remains at the output. Current limit and thermal overload protections protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125C. the junction and ambient air (JA). The value of JA is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered on the PCB. Table 6 shows typical JA values of the 5-lead TSOT package for various PCB copper sizes. Table 6. Typical JA Values for Specified PCB Copper Sizes Copper Size (mm2) 01 50 100 300 500 1 JA (C/W) 170 152 146 134 131 Device soldered to minimum size pin traces. The junction temperature of the ADP130 can be calculated from the following equation: TJ = TA + (PD x JA) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) where: VIN and VOUT are the input and output voltages, respectively. ILOAD is the load current. IGND is the ground current. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation can be simplified as follows: TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} (4) As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, a minimum copper size requirement exists for the PCB to ensure that the junction temperature does not rise above 125C. Figure 40 through Figure 46 show junction temperature calculations for different ambient temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper. (3) (2) THERMAL CONSIDERATIONS To guarantee reliable operation, the junction temperature of the ADP130 must not exceed 125C. To ensure that the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between Rev. 0 | Page 15 of 20 ADP130 JUNCTION TEMPERATURE CALCULATIONS 140 140 MAX TJ (DO NOT OPERATE ABOVE THIS POINT) 120 100 80 60 40 20 0 0.4 1mA 10mA 0.8 50mA 100mA 1.2 1.6 VIN - VOUT (V) 150mA 250mA 350mA (LOAD CURRENT) 2.0 2.4 120 100 80 60 40 20 0 0.4 MAX TJ (DO NOT OPERATE ABOVE THIS POINT) TJ (C) TJ (C) 06963-040 1mA 10mA 0.8 50mA 100mA 1.2 1.6 150mA 250mA 2.0 350mA (LOAD CURRENT) 2.4 2.8 2.8 VIN - VOUT (V) Figure 40. 500 mm2 of PCB Copper, TA = 25C, TSOT 140 140 Figure 43. 500 mm2 of PCB Copper, TA = 50C, TSOT MAX TJ (DO NOT OPERATE ABOVE THIS POINT) 120 100 80 60 40 20 0 0.4 1mA 10mA 0.8 50mA 100mA 1.2 1.6 VIN - VOUT (V) 150mA 250mA 2.0 350mA (LOAD CURRENT) 2.4 MAX TJ (DO NOT OPERATE ABOVE THIS POINT) 120 100 80 60 40 20 0 0.4 1mA 10mA 0.8 50mA 100mA 1.2 1.6 VIN - VOUT (V) 150mA 250mA 350mA (LOAD CURRENT) 2.0 2.4 TJ (C) 06963-041 TJ (C) 2.8 2.8 Figure 41. 100 mm2 of PCB Copper, TA = 25C, TSOT 140 140 Figure 44. 100 mm2 of PCB Copper, TA = 50C, TSOT MAX TJ (DO NOT OPERATE ABOVE THIS POINT) 120 100 80 60 40 20 0 0.4 1mA 10mA 0.8 50mA 100mA 1.2 1.6 VIN - VOUT (V) 150mA 250mA 2.0 350mA (LOAD CURRENT) 2.4 120 100 80 60 40 20 0 0.4 MAX TJ (DO NOT OPERATE ABOVE THIS POINT) TJ (C) TJ (C) 06963-042 1mA 10mA 0.8 50mA 100mA 1.2 1.6 150mA 250mA 2.0 350mA (LOAD CURRENT) 2.4 2.8 2.8 VIN - VOUT (V) Figure 42. 0 mm2 of PCB Copper, TA = 25C, TSOT Figure 45. 0 mm2 of PCB Copper, TA = 50C, TSOT Rev. 0 | Page 16 of 20 06963-045 06963-044 06963-043 ADP130 In cases where board temperature is known, use the thermal characterization parameter, JB, to estimate the junction temperature rise. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD), using the following formula: TJ = TB + (PD x JB) (5) PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP130. However, as shown in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. The input capacitor should be placed as close as possible to the VIN and GND pins. The output capacitor should be placed as close as possible to the VOUT and GND pins. Using 0402 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where the area is limited. GND GND The typical value of JB is 42.8C/W for the 5-lead TSOT package. 140 MAX TJ (DO NOT OPERATE ABOVE THIS POINT) 120 100 80 60 TJ (C) ANALOG DEVICES ADP130-xx-EVALZ C1 C2 U1 40 20 0 0.4 1mA 10mA 0.8 50mA 100mA 1.2 1.6 VIN - VOUT (V) 150mA 250mA 2.0 350mA (LOAD CURRENT) 2.4 06963-046 J1 VIN C3 VOUT 2.8 Figure 46. TSOT, TA = 85C GND EN VBIAS GND Figure 47. Example TSOT PCB Layout Rev. 0 | Page 17 of 20 06963-047 ADP130 OUTLINE DIMENSIONS 2.90 BSC 5 4 1.60 BSC 1 2 3 2.80 BSC PIN 1 0.95 BSC *0.90 0.87 0.84 1.90 BSC *1.00 MAX 0.20 0.08 8 4 0 0.60 0.45 0.30 0.10 MAX 0.50 0.30 SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 48. 5-Lead Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions show in millimeters ORDERING GUIDE Model ADP130AUJZ-0.8-R7 1 ADP130AUJZ-1.2-R71 ADP130AUJZ-1.5-R71 ADP130AUJZ-1.8-R71 ADP130AUJZ-2.5-R71 ADP130-0.8-EVALZ1 ADP130-1.2-EVALZ1 ADP130-1.5-EVALZ1 ADP130-1.8-EVALZ1 ADP130-2.5-EVALZ1 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Output Voltage (V) 0.8 1.2 1.5 1.8 2.5 0.8 1.2 1.5 1.8 2.5 Package Description 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Package Option UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 Branding LCH LCJ LCK LCL LCM Z = RoHS Compliant Part. Rev. 0 | Page 18 of 20 ADP130 NOTES Rev. 0 | Page 19 of 20 ADP130 NOTES (c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06963-0-7/08(0) Rev. 0 | Page 20 of 20 |
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