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FSSD06 -- SD/SDIO and MMC Two-Port Multiplexer
September 2008
FSSD06 -- SD/SDIO and MMC Two-Port Multiplexer
Features
On Resistance Typically 4, VDDH=2.7V Ftoggle: > 120MHz Low On Capacitance: 9pF Typical Low Power Consumption: 1A Maximum Conforms to Secure Digital (SD), Secure Digital I/O (SDIO), and Multimedia Card (MMC) Specifications Supports 1-Bit / 4-Bit Host Controllers (VDDH=1.65V to 3.6V) Communicating with High-Voltage (2.7-3.6V) and Dual-Voltage Cards (1.65-1.95V, 2.7-3.6V)
Description
The FSSD06 is a two-port multiplexer that allows Secure Digital (SD), Secure Digital I/O (SDIO), and Multimedia Card (MMC) host controllers to be expanded out to multiple cards or peripherals. This configuration enables the CMD, CLK, and D[3:0] signals to be multiplexed to dual-card peripherals. It is optimized for 1-bit / 4-bit SD / MMC applications. The architecture includes the necessary bi-directional data and command transfer capability for single highvoltage cards or dual-voltage supply cards. The clock path for the FSSD06 is a uni-directional buffer with an integrated pull-up for high-impedance mode. Typical applications involve switching in portables and consumer applications: cell phones, digital cameras, home theater monitors, portable GPS units, and printers.
-
VDDH=1.65 to 3.6V, VDDC1/C2=VDDH to 3.6V
24-Lead MLP (3.5 x 4.5mm) and UMLP Packages
Applications
Cell Phone, PDA, Digital Camera, Portable GPS LCD Monitor, Home Theater PC/TV, All-in-One Printer
IMPORTANT NOTE:
For additional performance information, please contact analogswitch@fairchildsemi.com.
Analog Symbol Diagram
VDDC1 VDDC2 VDDH 5 DAT[0:3], CMD 5 5 2DAT[0:3], 2CMD Control /OE S 1DAT[0:3], 1CMD
V DD C1
V DD C 2
RP U
RPU
CLK
1CLK 2CLK
GND
Figure 1.
Analog Symbol Diagram
Ordering Information
Part Number FSSD06BQX FSSD06UMX Operating Temperature Range -40C to +85C -40C to +85C
Eco Status
Green Green
Package Description 24-Lead Molded Leadless Package (MLP), JEDEC MO-220, 3.5 x 4.5mm 24-Lead Ultrathin Molded Leadless Package (UMLP)
Packing Method Tape & Reel Tape & Reel
For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
(c) 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com
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FSSD06 -- SD/SDIO and MMC Two-Port Multiplexer
Pin Configuration
1DAT[2] 1DAT[3] 1CMD
1DAT[2] 1DAT[3] VDDC1
19 18 17 16 15 14 13 11 1CLK 1DAT[0] 1DAT[1] 2DAT[2] 2DAT[3] 2CMD 12
DAT[2]
2
1
24
23 22 21 20 19 18 17 16 15
24
/OE
23
22
21
DAT[2] DAT[3] CMD VDDH GND CLK DAT[0] DAT[1]
3 4 5 6 7 8 9 10 11 12 13 14
VDDC1 1CLK
DAT[3] CMD
1 2 3 4 5 6
1DAT[0] 1DAT[1] 2DAT[2] 2DAT[3] 2CMD VDDC2
VDDH GND CLK DAT[0]
7
8
9
10
1CMD
20
/OE
DAT[1]
S
2DAT[1]
2DAT[0]
2CLK
VDDC2
Figure 2.
S
2DAT[1]
MLP Pin Assignments
2DAT[0]
2CLK
Figure 3.
UMLP Pin Assignments
Pin Definitions
Name
VDDH VDDC1, VDDC2 /OE S 1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD DAT[3:0], CMD CLK, 1CLK, 2CLK
Description
Power Supply (Host ASIC) Power Supply (SDIO Peripheral Card Ports) Output Enable (Active Low) Select Pin SDIO Card Ports SDIO Common Ports Clock Path Ports
Truth Table
/OE
LOW LOW HIGH
S
LOW HIGH X
Function
CMD, CLK, DAT[3:0] connected to 1CMD, 1CLK, 1DAT[3:0]; 2CLK pulled HIGH via RPU CMD, CLK, DAT[3:0] connected to 2CMD, 2CLK, 2DAT[3:0]; 1CLK pulled HIGH via RPU All Ports High Impedance; 1CLK, 2CLK pulled HIGH via RPU
(c) 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3
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Typical Application Diagram
VDDH
1.65 - 3.60V
VDDC1
FSSD06
RT GND
VDD H to 3.6V
CMD, DAT[3:0] 5
1CMD, 1DAT[3:0] 5 1CLK
Processor Secure Data / Multimedia Card 2:1 Peripheral Expander
WiFi, Bluetooth, MMC or SD Module VDDC2
CLK
RT GND
2CMD, 2DAT[3:0] 5 2CLK
VDD H to 3.6V
Note: External resistors (R T) are recommended if card supplies are allowed to float in the application. The resistors should be >500K to minimize power consumption. GND /OE S
WiFi, , Bluetooth, MMC or SD Module
Figure 4.
Typical Application Diagram
Functional Description
The FSSD06 enables sharing the ASIC/baseband processor SDIO port(s) to two peripheral cards, providing bi-directional support for dual-voltage SD/SDIO or MMC cards available in the marketplace. Each SDIO port of the FSSD06 has its own supply rail, allowing peripheral cards with different supplies to be interfaced to the host. The peripheral card supplies must be equal or greater than the host to minimize power consumption. The independent VDDH, VDDC1, and VDDC2 are defined by the supplies connected from the application Power Management ICs (PMICs) to the FSSD06. The clock path is a uni-directional buffered path rather than a bi-directional switch port.
CLK Bus
The 1CLK and 2CLK outputs are bi-state buffer architectures, rather than a switch I/O, to ensure 52MHz incident wave switching. When there is no communication on the bus (IDLE), the FSSD06 can be disabled with the /OE pin. When this pin is pulled HIGH, the nCLK outputs are also pulled HIGH. Along with nCMD, nDAT[3:0] goes high-impedance to ensure that the CLK path between the FSSD06 and the peripheral does not float.
IDLE State CMD/DAT Bus "Parking"
The SD and MMC card specifications were written for a direct point-to-point communication between host controller and card. The introduction of the FSSD06 in that path, as an expander, requires that the functional operation and system latency not be impacted by the FSSD06 switch characteristics. Since there are various card formats, protocols, and configurable controllers, a /OE pin is available to facilitate a fast IDLE transition for the nCMD/nDAT[3:0] outputs. Some controllers, rather than simply placing CMD/DAT into high-impedance mode, may pull their outputs HIGH for a clock cycle prior to going into high-impedance mode (referred to as "parking" the output). Some legacy controllers pull their outputs HIGH versus high impedance. If the /OE pin is left LOW and the controller places the CMD/DAT[3:0] outputs into high impedance, the nCMD/nDAT[3:0] output rise time is a function of the RC time constant through the switch path. It is recommended that the host controller pull CMD and DAT[3:0] HIGH for one cycle before pulling /OE HIGH. This facilitates parking all nCMD/nDAT[3:0] outputs HIGH before putting the switch I/Os in high impedance.
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CMD, DAT Bus Pull-ups
The 1CMD, 2CMD, 1DAT[3:0], and 2DAT[3:0] ports do not have, internally, the system pull-up resistors as defined in the MMC or SD card system bus specifications. The system bus pull-up must be added external to the FSSD06. The value, within the specific specification limits, is a function of the individual application and type of card or peripheral connected. For SD card applications, the RCMD and RDAT pull-ups should be between 10k and 100k. For MMC applications, the RCMD pull-ups should be between 4.7k and 100k and the RDAT pull-ups between 50k and 100k. The card-side 1CMD, 2CMD, 1DAT[3:0], and 2DAT[3:0] outputs have a circuit that facilitates incident wave switching, so the external pull-up resistors ensure retention of the output high level. The /OE pin can be used to place the 1CMD, 2CMD, 1DAT[3:0] and 2DAT[3:0] into high-impedance mode when the system enters IDLE state (see IDLE State CMD/DAT Bus "Parking").
(c) 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3
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FSSD06 -- SD/SDIO and MMC Two-Port Multiplexer
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDDH VDDC1,VDDC2 VSW
(1)
Parameter
Supply Voltage Supply Voltage Switch I/O Voltage
Conditions
Min.
-0.5 -0.5
Max.
4.6 4.6 VDDx + 0.3V (4.6V maximum) VDDx + 0.3V (4.6V maximum) 4.6 4.6 VDDx + 0.3V (4.6V maximum) -50 50 100
(2) (2) (2)
Unit
V V V V V V V mA mA mA C C C kV kV
1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD Pins DAT[3:0], CMD Pins
-0.5 -0.5 -0.5 -0.5 -0.5
VCNTRL VCLKO
(1)
Control Input Voltage CLK Input Voltage CLK Output Voltage Input Clamp Diode Current Switch I/O Current Peak Switch Current Storage Temperature Range Max Junction Temperature Lead Temperature Human Body Model (JEDEC: JESD22-A114)
S, /OE CLK 1CLK, 2CLK
(1) VCLKI (1)
IINDC ISW ISWPEAK TSTG TJ TL
SDIO Continuous SDIO Pulsed at 1ms Duration, <10% Duty Cycle -65 Soldering, 10 Seconds I/O to GND Supply to GND All Other Pins
+150 +150 +260C 8 9 5 2
ESD
Charged Device Model (JEDEC: JESD22-C101)
Notes: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. 2. VDDx references the specific SDIO port VDD rail (i.e. VDDC1, VDDC2, VDDH).
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VDDH VDDC1, VDDC2 VCNTRL VCLKI VSW C JA
Parameter
Supply Voltage - Host Side Supply Voltage - SDIO Cards Control Input Voltage - VS,V/OE Clock Input Voltage - VCLKI Switch I/O Voltage - CMD, DAT[3:0] Switch I/O Voltage - 1CMD, 1DAT[3:0] Switch I/O Voltage - 2CMD, 2DAT[3:0] Operating Temperature Thermal Resistance (free air), MLP24
Minimum
1.65 VDDH 0 0 0 0 0 -40
Maximum
3.6V 3.6V VDDH VDDH VDDH VDDC1 VDDC2 +85 50
Unit
V V V V V V V C C/W
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DC Electrical Characteristics at 1.8V VDDH
All typical values are for VDDH=1.8V at 25C unless otherwise specified.
Symbol
Common Pins VIK VIH VIL IIN IOZ IPU VOHC VOLC RPU RON RON
Parameter
VDDC1 / VDDC2 (V)
Conditions
TA=- 40C to +85C Min. Typ. Max.
-1.2 1.3
Unit
Clamp Diode Voltage Control Input Voltage High Control Input Voltage Low S, /OE Input High Current Off Leakage, Current of all ports CLK Pull-up Current CLK Output Voltage High CLK Output Voltage Low CLK Pull-up (3) Resistance Switch On Resistance Delta On Resistance Quiescent Supply Current (Host) Quiescent Supply Current (SDIO Cards) Delta ICC(VDDC1, VDDC2) for One Card Powered Off
(4)
2.7 2.7
IIK=-18mA VDDH=1.65V
V 0.5
2.7 3.6 3.6 3.6 2.7 3.6 VDDH=1.95V, VCNTRL=0V to VDDH VDDH=1.95V, VSW =0V to VDDX VCLKI=VDDH VCLKO=0V, /OE=VDDH IOH=-2mA IOL=-2mA 50 2.7 2.7 VCMD, DAT[3:0]=0V, ION=-2mA, See Figure 5 VCMD, DAT[3:0]=0V, ION=- 2mA VDDH=1.95V, VSW=0 or VDDH, IOUT=0 VSW=0 or VDDx, IOUT=0, VCLKI=VDDH, VCLKO=Open, /OE=0V VSW=0 or VDDx, IOUT=0, VCLKI=VDDH, VCLKO=Open, /OE=0V 100 4 0.8
2.4
-1 -1.0 0.5
1 1.0 35
A A A V
90
mV k
6

(4, 5)
Power Supply ICC(VDDH) ICC(VDDC1,
VDDC2)
0 3.6 3.6V / 0V
1 1
A A
ICARD
1
A
Notes: 3. Guaranteed by characterization, not production tested. 4. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch. 5. RON=RON max - RON min measured at identical VCC, temperature, and voltage.
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DC Electrical Characteristics at 2.7V VDDH
All typical values are for VDDH=2.7V at 25C unless otherwise specified.
Symbol
Common Pins VIK VIH VIL IIN IOZ IPU VOHC VOLC RPU RON RON
Parameter
VDDC1 / VDDC2 (V)
Conditions
TA=- 40C to +85C Min. Typ. Max.
-1.2 1.8
Unit
Clamp Diode Voltage Control Input Voltage High Control Input Voltage Low S, /OE Input High Current Off Leakage Current of all ports CLK Pull-up Current CLK Output Voltage High CLK Output Voltage Low CLK Pull-up (6) Resistance Switch On Resistance Delta On Resistance Quiescent Supply Current (Host) Quiescent Supply Current (SDIO Cards) Delta ICC(VDDC1, VDDC2) for One Card Powered Off
(7)
2.7 2.7
IIK=-18mA VDDH=2.7V
V 0.8
2.7 3.6 3.6 3.6 2.7 3.6 VDDH=3.6V, VCNTRL=0V to VDDH VDDH=3.6V, VSW =0V to VDDX VCLKI=VDDH, VCLKO=0V, /OE=VDDH IOH=-2mA IOL=-2mA 50 2.7 2.7 VCMD, DAT[3:0]=0V, ION=-2mA See Figure 5 VCMD, DAT[3:0]=0V, ION=- 2mA VDDH=3.6V, VSW=0 or VDDH, IOUT=0 VSW=0 or VDDx, IOUT=0, VCLKI=VDDH , VCLKO=Open, /OE=0V VSW=0 or VDDx, IOUT=0, VCLKI=VDDH, VCLKO=Open, /OE=0V 100 2.5 0.8
2.4
-1 -1.0 0.5
1 1.0 50
A A A V
90
mV k
6.0

(7,8)
Power Supply ICC(VDDH) ICC(VDDC1,
VDDC2)
0 3.6 3.6V/0V 0V/3.6V
1 1
A A
ICARD
1
A
Notes: 6. Guaranteed by characterization, not production tested. 7. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch. 8. RON=RON max - RON min measured at identical VCC, temperature, and voltage.
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AC Electrical Characteristics at 1.8V VDDH
All typical values are for VDDH=1.8V at 25C unless otherwise specified.
Symbol
Parameter
Turn-On Time, S, /OE to CMD, DAT[3:0] Turn-Off Time, S, /OE to CMD, DAT[3:0] Switch Propagation (9) Delay Switch Skew CMD, DAT[3:0]
(9, 10)
VDDC1 / VDDC2 (V)
2.7 to 3.6
Conditions
TA=- 40C to +85C Min. Typ.
10
Unit
Max.
24 ns
tON1
VSW =0V, RL=1k, CL=30pF See Figure 7, Figure 8 VSW =0V, RL=1k, CL=30pF See Figure 7, Figure 8 See Figure 9 RL=1k, CL=30pF VSW =0V, RL=1k, CL=30pF See Figure 7, Figure 8 VSW =0V, RL=1k, CL=30pF See Figure 7, Figure 8 RL=1k, CL=30pF See Figure 11 f=10MHz, RT=50, CL=30pF, See Figure 12 f=10MHz, RT=50, CL=30pF, See Figure 13 CL=30pF
tOFF1 tPD tSKEW tON2 tOFF2 tPDCLK OIRR Xtalk ftoggle
2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6
7 1 2 17 10 3.0 -60 -60 120
22
ns ns ns
Turn-On Time, S, /OE to 1CLK, 2CLK Turn-Off Time S, /OE to 1CLK, 2CLK Clock Propagation Delay Off Isolation
(9)
35 28 5.5
ns ns ns dB dB MHz
Non-Adjacent Channel (9) Crosstalk Clock Frequency
(9)
Notes: 9. Guaranteed by characterization, not production tested. 10. Skew is determined by |TPLH - TPHL | for worst-case temperature and VDDX.
(c) 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3
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AC Electrical Characteristics at 2.7V VDDH
All typical values are for VDDH=2.7V at 25C unless otherwise specified.
Symbol
tON1 tOFF1 tPD tSKEW tON2 tOFF2 tPDCLK OIRR Xtalk ftoggle
Parameter
Turn-On Time S, /OE to CMD, DAT[3:0] Turn-Off Time S, /OE to CMD, DAT[3:0] Switch Propagation (11) Delay Switch Skew CMD, DAT[3:0]
(12)
VDDC1 / VDDC2 (V)
2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6
TA=- 40C to +85C Conditions Min.
VSW =0V, RL=1k, CL=30pF See Figure 7, Figure 8 VSW =0V, RL=1k, CL=30pF See Figure 7, Figure 8 See Figure 9 RL=1k, CL=30pF VSW =0V, RL=1k, CL=30pF See Figure 7, Figure 8 VSW =0V, RL=1k, CL=30pF See Figure 7, Figure 8 RL=1k, CL=30pF See Figure 11 f=10MHz, RT=50, CL=30pF See Figure 12 f=10MHz, RT=50, CL=30pF See Figure 13 CL=30pF
Unit Typ.
8 6 1 1.5 15 10 1.5 -60 -60 120 25 25 3.0
Max.
17 13 ns ns ns ns ns ns ns dB dB MHz
Turn-On Time S, /OE to 1CLK, 2CLK Turn-Off Time S, /OE to 1CLK, 2CLK Clock Propagation Delay Off Isolation
(11)
Non-Adjacent Channel (11) Crosstalk Clock Frequency
(11)
Notes: 11. Guaranteed by characterization, not production tested. 12. Skew is determined by |TPLH - TPHL | for worst-case temperature and VDDX.
Capacitance
Symbol Parameter
Control and CLK Pin Input Capacitance Common Port On Capacitance (CDAT[3:0], CMD) Input Source Off Capacitance
Conditions
TA=- 40C to +85C Min. Typ.
2.5 9.0
Unit
Max.
CIN (S, /OE, CLK) CON
VDDH=0V VDDH=1.8V,VDDC1=VDDC2=2.7V, V/OE=0V, Vbias=0V, f=1MHz See Figure 15 VDDH=1.8V,VDDC1=VDDLH2=2.7V, V/OE=3.3V, Vbias=0V, f=1MHz See Figure 14
pF
COFF
4.0
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Test Diagrams
V ON
nDAT[3:0],nCMD V IN
GND
DAT[3:0],CMD
NC
I OZ
A
V IN Select VS =
GND
Select
I ON
GND
RON =
VON / ION
VS =
Vddl 0 orVddl
0 orVddl V
Figure 5.
On Resistance
Figure 6.
Off Leakage (Each Switch Port is Tested Separately)
V DDx nDAT[3:0],nCMD DAT[3:0], CMD RL VSW
GND
tRISE = 2.5ns Vddx Input - VCNTRL GND VOH Output - VOUT VOL Vol + 0.15V tON t
OFF
tFALL = 2.5ns
RS
CL
GND
V OUT
90% V ddx /2
90% V ddx /2 10%
10%
VS
GND
50%
RL , RS , and C L are function of application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance
Figure 7.
AC Test Circuit Load
Figure 8.
Turn On/Off Time Waveforms
V DDx
tRISE = 2.5ns Vddx Input - VSW GND VOH Output- VOUT VOL 50% tpLH tpHL 10% 90% Vddx /2 90% V ddx/2
tFALL = 2.5ns
CLK VCLKI 1CLK, 2CLK RL
10%
GND
RS
CL
GND
V OUT
50%
VS
GND
RL , RS , and CL are function of application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance
Figure 9.
Switch Propagation Delay Waveform
Figure 10.
AC Test Circuit Load (CLK)
(c) 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3
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Test Diagrams (Continued)
tRISE = 2.5ns Vddx 90% Input - VCLKI GND VOHC Output - VCLKO VOLC 50% tpLH tpHL 50% 10% V ddx /2 90% V ddx /2
RT
GND
t FALL = 2.5ns
Network Analyzer
RS V IN V S
GND
10%
VS
GND
GND GND
V OUT RT
GND
RS and R T are function of application environment (see AC Tables for specific values)
Off -Isolation = 20 Log (VOUT / VIN )
Figure 11.
CLK Propagation Delay Waveforms
Figure 12.
Channel Off Isolation
NC
Network Analyzer
RS
GND
V IN
VS
GND
VS
GND
RT
GND GND
RS and RT are function of application environment GND (see AC Tables for specific values) CROSSTALK = 20 Log (VOUT / VIN )
RT
VOUT
Figure 13.
Channel-to-Channel Crosstalk
nDAT[3:0], nCMD, nCLK
Capacitance Meter
f = 1MHz,Vbias = 0V
nDAT[3:0], nCMD, nCLK
S VS =
0 orVddh
Capacitance Meter
f = 1MHz, Vbias = 0V
nDAT[3:0], nCMD, nCLK
S VS =
0 or Vddh
Figure 14.
Channel Off Capacitance
Figure 15.
Channel On Capacitance
(c) 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3
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FSSD06 -- SD/SDIO and MMC Two-Port Multiplexer
Tape and Reel Specifications
Package Designator
MPX
Tape Selection
Leader (Start End) Carrier Trailer (Hub End)
Number Cavities
125 (Typical) 3000 75 (Typical)
Cavity Status
Empty Filled Empty
Cover Tape Status
Sealed Sealed Sealed
Tape Dimensions
Dimensions are in millimeters unless otherwise noted.
Reel Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Tape Size
(12.00mm)
A
13.000 (330.00)
B
0.059 (1.50)
C
0.512 (13.00)
D
0.795 (20.00)
N
2.165 (55.00)
W1
0.488 (12.40)
W2
0.724 (18.40)
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Physical Dimensions
Figure 16.
24-Lead Molded Leadless Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
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Physical Dimensions
2.80 2.23 0.10 C 0.66 2.50 0.56
2X
A
B
1
24
19
0.40
PIN #1 IDENT
2.23 3.40
13
3.70
0.10 C
7
TOP VIEW
2X
0.23
RECOMMENDED LAND PATTERN
0.55 MAX. 0.10 C
0.15
SEATING PLANE
0.08 C 0.05 0.00
C
SIDE VIEW
7
23X
0.35 0.45
13
0.40
1
0.45 0.55
24
19
0.15 24X 0.25 0.10 C A B 0.05 C
BOTTOM VIEW
Figure 17.
24-Lead Ultrathin Molded Leadless Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3
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CONFIDENTIAL AND PROPRIETARY -- DO NOT DISTRIBUTE
FSSD06 -- SD/SDIO and MMC Two-Port Multiplexer
(c) 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3
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