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 STL55NH3LL
N-channel 30 V, 0.0079 15 A, PowerFLATTM (6x5) , ultra low gate charge STripFETTM Power MOSFET
Features
Type STL55NH3LL

VDSS 30 V
RDS(on) max < 0.0088
ID 15 A
Improved die-to-footprint ratio Very low profile package (1mm max) Very low thermal resistance Very low gate charge Low threshold device
PowerFLATTM(6x5)
Application
Switching applications Figure 1. Internal schematic diagram
Description
This application specific Power MOSFET is the latest generation of STMicroelectronics unique "STripFETTM" technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The chip-scaled PowerFLATTM package allows a significant board space saving, still boosting the performance.
Table 1.
Device summary
Marking L55NH3LL Package PowerFLATTM (6x5) Packaging Tape and reel
Order code STL55NH3LL
May 2008
Rev 3
1/14
www.st.com 14
Contents
STL55NH3LL
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6
3 4 5
Test circuits
.............................................. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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STL55NH3LL
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS(1) VGS(2) ID(3) ID(3) IDM ID
(4) (5)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Gate-source voltage Drain current (continuous) at TC = 25 C Drain current (continuous) at TC=100 C Drain current (pulsed) Drain current (continuous) at TC = 25 C Drain current (continuous) at TC=100 C Total dissipation at TC = 25 C Total dissipation at TC = 25 C Derating factor Value 30 16 18 55 36 60 15 9.4 4 60 0.03 -55 to 150 Unit V V V A A A A A W W W/C C
ID (5) PTOT PTOT
(5) (3)
TJ Tstg
Operating junction temperature Storage temperature
1. Continuous mode 2. Guaranteed for test time 15 ms 3. The value is rated according Rthj-c 4. Pulse width limited by safe operating area 5. The value is rated according Rthj-pcb
Table 3.
Symbol Rthj-case Rthj-pcb
(1)
Thermal resistance
Parameter Thermal resistance junction-case (drain) Thermal resistance junction-ambient Value 2.08 31.3 Unit C/W C/W
1. When mounted on FR-4 board of 1inch, 2oz Cu, t < 10 sec
Table 4.
Symbol IAV EAS
Avalanche data
Parameter Not-repetitive avalanche current (pulse width limited by Tj Max) Single pulse avalanche energy (starting Tj = 25 C, ID=IAV, VDD = 24 V, L=6 mH) Value 7.5 150 Unit A mJ
3/14
Electrical characteristics
STL55NH3LL
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 5.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS= 0 VDS = max rating, VDS = max rating @125 C VGS = 16 V VDS= VGS, ID = 250 A VGS= 10 V, ID= 7.5 A VGS= 8 V, ID= 7.5 A VGS= 4.5 V, ID= 7.5 A 1 0.0079 0.0079 0.009 Min. 30 1 10 Typ. Max. Unit V A A
IDSS
IGSS VGS(th)
100
nA V
2.5 0.0088 0.0088 0.0115
RDS(on)
Table 6.
Symbol Ciss Coss Crss Qg Qgs Qgd Qgs1 Qgs2
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Pre Vth gate-to-source charge Post Vth gate-to-source charge Gate input resistance Test conditions VDS = 25 V, f=1 MHz, VGS=0 VDD=15 V, ID = 15 A VGS =4.5 V (see Figure 16) VDD=15 V, ID = 15 A VGS =4.5 V f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain Min. Typ. 965 285 38 9 3.7 3 2.5 1.2 12 Max. Unit pF pF pF nC nC nC nC nC
RG
0.5
1.5
2.5
4/14
STL55NH3LL
Electrical characteristics
Table 7.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=15 V, ID= 7.5 A, RG=4.7 , VGS=4.5 V (see Figure 18) Min. Typ. 15 32 18 8.5 Max. Unit ns ns ns ns
Table 8.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD=15 A, VGS=0 ISD=15 A, di/dt = 100 A/s, VDD=20 V, Tj=150 C (see Figure 17) 24 17.4 1.45 Test conditions Min Typ. Max 15 60 1.3 Unit A A V ns nC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300 s, duty cycle 1.5%
5/14
Electrical characteristics
STL55NH3LL
2.1
Figure 2.
Electrical characteristics (curves)
Safe operating area Figure 3. Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Normalized BVDSS vs temperature
Figure 7.
Static drain-source on resistance
6/14
STL55NH3LL Figure 8. Gate charge vs gate-source voltage Figure 9.
Electrical characteristics Capacitance variations
Figure 10. Normalized gate threshold voltage vs temperature
Figure 11. Normalized on resistance vs temperature
Figure 12. Source-drain diode forward characteristics
Figure 13. Avalanche energy vs starting tj
7/14
Electrical characteristics Figure 14. Allowable Iav vs time in avalanche
STL55NH3LL
The previous curve gives the single pulse safe operating area for unclamped inductive loads, under the following conditions: PD(AVE) =0.5*(1.3*BVDSS *IAV) EAS(AR) =PD(AVE) *tAV Where: IAV is the allowable current in avalanche PD(AVE) is the average power dissipation in avalanche (single pulse) tAV is the time in avalanche
8/14
STL55NH3LL
Test circuits
3
Test circuits
Figure 16. Gate charge test circuit
Figure 15. Switching times test circuit for resistive load
Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test switching and diode recovery times circuit
Figure 19. Unclamped inductive waveform
Figure 20. Switching time waveform
9/14
Test circuits Figure 21. Gate charge waveform
Id Vds Vgs
STL55NH3LL
Vgs(th)
Qgs1 Qgs2
Qgd
10/14
STL55NH3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
11/14
Package mechanical data
STL55NH3LL
PowerFLATTM (6x5) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 TYP 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 MAX. 0.93 0.05 MIN. 0.031 TYP. 0.032 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 MAX. 0.036 0.0019 inch
12/14
STL55NH3LL
Revision history
5
Revision history
Table 9.
Date 18-Mar-2008 05-May-2008 07-May-2008
Document revision history
Revision 1 2 3 First release. Corrected Table 1: Device summary Update Figure 6: Normalized BVDSS vs temperature Changes
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STL55NH3LL
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