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STMEC001
Power interface switch for ExpressCardTM
Features

Compliant with PC CardTM standard for ExpressCard 3-channel power interface switch Built-in under-voltage lockout (UVLO) circuit Ultra-low standby-mode current Additional 5 V or 12 V power supply not required High reliability ensured with integrated overcurrent, thermal and undervoltage protection circuitries applied to each voltage rail Soft start function for non-rush current Ultra-low standby-mode current for power saving Ultra-low ON resistance for fast switching
QFN16
TSSOP20

Description
The STMEC001 is an ExpressCard power interface switch which provides the complete power management solution required by the ExpressCard specification. The STMEC001 consists of 3 internal switches distributing 3.3 V, 3.3VAUX, and 1.5 V to the ExpressCard socket without the need of additional charge pump or external switches. The STMEC001 ExpressCard power switch is ideal for notebook computers, desktop computers, personal digital assistants (PDA), or other handheld devices implementing the ExpressCard schematic.
. Table 1. Device summary
Order code STMEC001QTR STMEC001ATTR Package QFN16 TSSOP20 Packing Tape and reel Tape and reel
April 2008
Rev 4
1/19
www.st.com 19
Contents
STMEC001
Contents
1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 3 4
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Power states description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 6 7 8 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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STMEC001
Pin description
1
Pin description
Figure 1. STMEC001 pin configuration (top view)
RCLKEN SYSRST SHDN
/STBY VIN_3.3V VO_3.3V VO_3.3V
16 1 2 3 4 5
/PERST
15
14
/OC
13 12 11 10 9 VIN_3.3AUX VO_3.3AUX VIN_1.5V VO_1.5V
6
GND
7
/CPUSB
8
/CPPE
QFN16
NC /SYSRST /SHDN /STBY VIN_3.3V VIN_3.3V VO_3.3V VO_3.3V /PERST NC GND NC
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
NC /OC RCLKEN VIN_3.3VAUX V0_3.3VAUX VIN_1.5V VIN_1.5V VO_1.5V VO_1.5V /CPPE /CPUSB NC
TSSOP20
3/19
Pin description Table 2.
Pin Name QFN16 15 16 1 2 3 4 5 6 7 8 9 10 11 12 TSSOP20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 NC /SYSRST /SHDN /STBY VIN_3.3V VIN_3.3V VO_3.3V VO_3.3V /PERST NC GND NC NC /CPUSB /CPPE VO_1.5V VO_1.5V VIN_1.5V VIN_1.5V VO_3.3VAUX VIN_3.3VAUX I I I I I O O O I I O O I I O I No connection Type Description
STMEC001 Pin assignments
System Reset input - active low, logic level signal, internal 150 K pull-up Shutdown input - active low, logic level signal, internal 150 K pull-down Standby input - active low, logic level signal, internal 150 K pull-down 3.3 V input for VO_3.3V 3.3 V input for VO_3.3V Switched output that delivers 0 V, 3.3 V or high impedance to card Switched output that delivers 0 V, 3.3 V or high impedance to card A logic level power good to slot (delayed) No connection Ground No connection No connection Card Present input for USB cards, internal 150 K pull-up Card Present input for PCI ExpressCard, internal 150 K pull-up Switched output that delivers 0 V, 1.5 V or high impedance to card Switched output that delivers 0 V, 1.5 V or high impedance to card 1.5 V input for 1.5Vout 1.5 V input for 1.5VOUT Switched output that delivers 0 V, 3.3 V or high impedance to card 3.3 V input for VO_3.3VAUX and chip power Reference Clock Enable signal. As an output, a logic level power good to host for slot (open drain). As an input, if kept inactive by the host, prevents /PERST from being de-asserted, internal 150 K pull-up Over-current status output for slot (open drain) No connection
13
22
RCLKEN
I/O
14 -
23 24
/OC NC
O -
4/19
STMEC001
Pin description
1.1
Pin functional description
Table 3.
Symbol
Pin detailed descriptions
Description A logic low level on this input indicates that the card present supports PCI Express functions. This input pin connects to the 3.3 VAUX input through a 150 k internal pull up. When inserted, the card physically connects this input to ground if the card supports PCI Express functions. A logic low level on this input indicates that the card present supports USB functions. The input pin CPUSB connects to the 3.3 VAUX input through a 150 k internal pull up. When inserted, the card physically connects CPUSB to ground if the card supports USB functions. When asserted (logic low), this input instructs the STMEC001 to turn off all voltage outputs and the discharge FETs at the 3 outputs are activated. When asserted (logic low), this input places the power switch in Standby Mode by turning off the 3.3 V and 1.5 V power switches and keeping the 3.3 VAUX switch on.
CPPE
CPUSB
SHDN STBY
This pin serves as both an input and an output. On power up, the power switch keeps this signal at a low state as long as any of the output power rails are out of their tolerance range. Once all output power rails are within tolerance, the power switch releases RCLKEN RCLKEN allowing it to transition to a high state (internally pulled up to 3.3 VAUX). The transition of RCLKEN from a low to a high state starts an internal timer for the purpose of de-asserting /PERST. As an input, RCLKEN can be kept low to delay the start of the /PERST internal timer. RCLKEN can be used by the host system to enable a clock driver. PERST On power up, this output remains asserted. Once all power rails are within tolerance, RCLKEN is asserted and /PERST is de-asserted after a time delay. On power down, this output is asserted whenever any of the power rails drop below their voltage tolerance. This input is driven by the host system and directly affects /PERST. Asserting /SYSRST (logic level: low) forces /PERST to assert. The OC pin is an open drain output for over-current indication. Output does not turn off during over-current condition. The output voltage decreases as the output current exceeds over-current limit. Only if the temperature increases above the limit the output is turned off completely. Over-current in one output does not affect the other outputs.
SYSRST
OC
5/19
Logic diagram
STMEC001
2
Logic diagram
Figure 2. STMEC001 block diagram
UVLO
Vin_3.3V
SW
V/I sense and discharge switch
VO_3.3V
Vin_1.5V
SW
V/I sense and discharge switch
VO_1.5V
Vin_3.3VAUX
SW
V/I sense and discharge switch
VO_3.3VAUX
150 K
150 K 150 K 150 K
150 K 150 K
#SHDN #STBY #SYSRST #OC Control logic
#PERST #CPUSB #CPPE RCLKEN Thermal sense POR
6/19
STMEC001 Figure 3. STMEC001 typical application
Logic diagram
3.3 V IN Power supply 3.3 V AUX IN 1.5 V IN
3.3 V 3.3 V AUX
STMEC001
ExpressCard Power switch
1.5 V ExpressCard slot Control signals
Control signals ExpressCard host Data links
7/19
Maximum ratings
STMEC001
3
Maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol
Absolute maximum ratings(1)
Parameter Value VI(3.3VIN) - 0.3 to 4.6 Unit V V V
VI
Input voltage
VI(1.5VIN) - 0.3 to 4.6 VI(3.3VAUX) - 0.3 to 4.6 VI(3.3VIN) internally limited
IO
Output current
VI(1.5VIN) internally limited VI(3.3VAUX) internally limited
TOP TSTG
Operating junction temperature, TJ (max to be calc. at worst case PD at 85 C ambient) Storage temperature range
-40 to 120 -55 to 150
C C
1. Absolute maximum ratings are those values above which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referenced to GND.
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STMEC001
Power states
4
Power states
The STMEC001 operates in a number of states, as described in the following table:
Table 5.
Power states
Logic states 1.5 V X X ON ON ON X /SHDN 1 0 1 1 1 X /CPUSB 1 X 0 X X X /CPPE 1 X X 0 X X /STBY X X 1 1 0 X 3.3VAUX GND GND ON ON ON OFF Outputs 3.3 V GND GND ON ON OFF OFF 1.5 V GND GND ON ON OFF OFF No card Shutdown USB enable PE enable Standby OFF Mode
Voltage inputs 3.3VAUX ON ON ON ON ON OFF 3.3 V X X ON ON ON X
4.1
Power states description

No card mode: when no card is inserted, and at least 3.3 VAUX is available, all outputs are grounded Shutdown mode: when /SHDN is asserted, and at least 3.3 VAUX is available all outputs are grounded USB/PW enable mode: when all 3 inputs are available, detection of cartd insertion turns on all 3 outputs. - VIN_3.3 V, VIN_3.3VAUX and VIN_1.5 V are present at the USB/PW enable input of the power switch prior to a card being inserted. Power to the card is based on the state of /CPUSB and /CPPE (see table). The card is present and VIN_1.5 V or/and VIN_3.3 V is removed from the input of the power switch; VIN_3.3VAUX will still be provided to the card, VIN_1.5 and VIN_3.3 V will be disabled (see table). If power to VIN_1.5 V and VIN_3.3 V is restored, output to the card will be restored. Prior to the insertion of a card, VIN_3.3 VAUX is available, VIN_3.3 V and VIN_1.5 V are not available; no power is made available to the card. If VIN_1.5 V and VIN_3.3 V are made available at the input of the power switch after the card is inserted, both VO_3.3 V and VO_1.5 V are made available to the card. Standy mode: when all 3 supplies are available and /STBY is asserted. Only 3.3 VAUX output is on. OFF mode: if VAUX is off, all outpus are off. When VIN_3.3VAUX is not present, VIN_1.5 V or/and VIN_3.3 V must not be present.
-
-
- -
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Electrical characteristics
STMEC001
5
Table 6.
Symbol
Electrical characteristics
Recommended operating conditions
Parameter Input voltage: VI(3.3VIN) is required for its respective functions VI Input voltage: VI(1.5VIN) is required for its respective functions Input voltage: VI(3.3VAUX) is required for all circuit operations Output current: IO(3.3V) at TJ = 100 C IO Output current: IO(1.5V) at TJ = 100 C Output current: IO(AuxV) at TJ = 100 C TOP Operating junction temperature, TJ (max to be calc. at worst case PD at 85 C ambient) Value 3.0 to 3.6 1.35 to 1.65 3.0 to 3.6 1.3 (max.) 650 (max.) 275 (max.) 100 Unit V V V A mA mA C
Table 7.
Symbol
Electrical characteristics TJ = 25 C, VI(VIN 3.3 V) = VI(VIN 3.3VAUX)= 3.3 V, VI(VIN 1.5 V) = 1.5 V
Parameter VIN_3.3 V to VO_3.3 V Test conditions I = 1300 mA, TJ = 25 C I = 1300 mA, TJ = 100 C I = 650 mA, TJ = 25 C I = 650 mA, TJ = 100 C I = 275 mA, TJ = 25 C I = 275 mA, TJ = 100 C I = 1300 mA, TJ = 25 C I = 1300 mA, TJ = 100 C I = 650 mA, TJ = 25 C I = 650 mA, TJ = 100 C I = 275 mA, TJ = 25 C I = 275 mA, TJ = 100 C I discharge = 1 mA I discharge = 1 mA I discharge = 1 mA 0.1 0.1 0.1 170 80 53 140 70 Min Typ 53 Max 64 80 88 m 105 170 210 64 80 92 m 115 192 230 0.5 0.5 0.5 Unit
RSW(1) TSSOP20
VIN_1.5 V to VO_1.5 V
VIN_3.3VAUX to VO_VAUX
VIN_3.3 V to VO_3.3 V RSW(1) QFN16
VIN_1.5 V to VO_1.5 V
VIN_3.3VAUX to VO_VAUX RO(3.3 V) discharge resistance RO RO(1.5 V) discharge resistance RO(1.5 V) discharge resistance
10/19
STMEC001 Table 7.
Symbol
Electrical characteristics Electrical characteristics TJ = 25 C, VI(VIN 3.3 V) = VI(VIN 3.3VAUX)= 3.3 V, VI(VIN 1.5 V) = 1.5 V (continued)
Parameter IO(3.3 V) limit (limit is the steady state value) Test conditions TJ -40 C to100 C Output powered into a short TJ -40 C to100 C Output powered into a short TJ -40 C to 100 C Output powered into a short Min Typ Max Unit
1.3
2.5
A
IOS
IO(1.5 V) limit IO(VAUX) limit
650 275
1300 660
mA
1. Switch resistance (in production - probe testing at 1.3 A. Final test at 1.0 A and apply guard band)
Table 8.
Symbol Tsh
Power switching
Parameter Thermal shutdown, trip point, TJ. Hysteresis VO (3.3VOUT) with100 m short Current limit response time. From short to first threshold within 1.1 times VO (1.5VOUT) with100 m short of the final current limit VO (VAUX) with100 m short Input quiescent current: normal operation VIN_3.3VAUX VO (VAUX) = VI(3.3VAUX) = VI(3.3VIN) VO(1.5V) = VI(1.5VIN) VIN_3.3V TJ -40 C,100 C VIN_1.5V Outputs are ON and unloaded VIN_3.3VAUX VO(VAUX) = VI(3.3VAUX) = VI(3.3VI N) VO(1.5 V) = VI(1.5VIN) VIN_3.3V TJ -40 C,100 C] VIN_1.5V Outputs are ON and unloaded VIN_3.3VAUX T -40 C,100 C J VIN_3.3V discharge FETs are ON VIN_1.5V VIN_3.3VAUX Forward leakage current (current measured at input pins/no card present) VIN_3.3V /SHDN inactive VIN_1.5V VIN_3.3VAUX TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C 150 25 10 150 10 10 50 15 5 5 20 10 30 10 30 Test condition Over-current condition Min 155 10 5 5 5 20 20 20 120 40 10 180 40 25 270 15 15 100 20 10 10 50 15 50 15 50 A A A s Typ Max Unit 165 C C
IOL
IQ
Input quiescient current: normal operation with pull-up
Input quiescient current: /SHDN asserted with pull-up
SHDN
Reverse leakage current ILEAK(1) (current measured from output pins / input grounded)
VIN_1.5V
VIN_3.3V
1. All high side switches are in Hi-Z state, VO (AUX) = VO (3.3 V) = 3.3 V, Vo (1.5 V) = 1.5 V, TJ -40 C,100 C
11/19
Electrical characteristics
STMEC001
Table 9.
Symbol
Undervoltage lockout (UVLO)
Parameter VIN_3.3 UVLO Test condition VIN_3.3 level, below which VIN_3.3 and VIN_1.5 switches are off VIN_1.5 level, below which VIN_3.3 and VIN_1.5 switches are off VIN_3.3VAUX level, below which sets the device into OFF state Min 2.6 Typ Max Unit 2.9 V
UVLO
VIN_1.5 UVLO
1
1.25
V
VIN_3.3 VAUX UVLO UVLO hysteresis
2.6 100
2.9
V mV
12/19
STMEC001
Logic characteristics
6
Table 10.
Logic characteristics
Logic states
Logic transition High level Condition Min 2.0 V Low level 3.3 V output falling 2.7 2.7 1.2 0.8 3.0 3.0 1.35 500 4 10 20 500 100 0.4 1 6 20 ns ms ns s V A s V Typ Max Unit
Logic input voltage
PERST# assertion threshold of output voltage PERST# assertion delay from output voltage invalid PERST# de-assertion from output voltage valid
AUX output falling 1.5 V output falling Output falling below threshold Output rising above threshold
PERST# assertion delay from SYSRST# STSRST asserted or de-asserted RCLKEN assertion delay from output voltage valid OC# output low voltage OC# leakage current OC# deglitch Output rising above threshold IOC = 2 mA VOC = 3.6 V Falling into or out of an over-current condition
Table 11.
ESD protections
Pin Condition Versus GND & supply Versus GND & supply Versus GND Versus supply ESD tolerance 6 2 kV 2 1 Unit
VOUT (3.3 V, 1.5 V, AUX) All other pins (except RCLKEN) RCLKEN RCLKEN
13/19
Switching times
STMEC001
7
Table 12.
Symbol
Switching times
Switching characteristics
Parameter VIN_3.3V to VO_3.3V VIN_3.3VAUX to VO_VAUX VIN_1.5V to VO_1.5V tR Output rise time VIN_3.3V to VO_3.3V VIN_3.3VAUX to VO_VAUX VIN_1.5V to VO_1.5V VIN_3.3V to VO_3.3V VIN_3.3VAUX to VO_VAUX tF Output fall time (/CPUSB and /CPPE inactive) VIN_1.5V to VO_1.5V VIN_3.3V to VO_3.3V VIN_3.3VAUX to VO_VAUX VIN_1.5V to VO_1.5V VIN_3.3V to VO_3.3V VIN_3.3VAUX to VO_VAUX VIN_1.5V to VO_1.5V Condition CL(3.3V) = 0.1 F Io(3.3V) = 0 A CL(AUX) = 0.1 F Io(AUX) = 0A CL(1.5V) = 0.1 F Io(1.5V) = 0 A CL(3.3V) = 100 F RL = VO_3.3V / 1.0 A CL(3.3V) = 100 F RL = VO_VAUX/ 0.25 A CL(3.3V) = 100 F RL = VO_1.5 V / 0.5 A CL(3.3V) = 0.1 F Io(3.3V) = 0 A CL(AUX) = 0.1 F Io(AUX) = 0 A CL(1.5V) = 0.1 F Io(1.5V) = 0 A CL(3.3V) = 20 F, no load CL(AUX) = 20 F, no load CL(1.5V) = 20 F, no load CL(3.3V) = 0.1 F Io(3.3V) = 0 A CL(AUX) = 0.1 F Io(AUX) = 0 A CL(1.5V) = 0.1 F Io(1.5V) = 0 A CL(3.3V) = 100 F RL = VO_3.3V/1.0 A CL(3.3V) = 100 F RL = VO_VAUX/0.25 A CL(3.3V) = 100 F RL = VO_1.5V/0.5 A Min 0.1 0.1 0.1 0.1 0.1 0.1 10 10 10 2.0 2.0 2.0 10 10 10 0.1 0.1 0.1 Typ Max 3 3 3 ms 6 6 6 150 150 150 30.0 30.0 30.0 80 80 80 5.0 5.0 5.0 ms s ms s Unit
tSHDN
Output fall time (/SHDN active) VIN_3.3V to VO_3.3V VIN_3.3VAUX to VO_VAUX VIN_1.5V to VO_1.5V
14/19
STMEC001 Table 12.
Symbol
Switching times Switching characteristics (continued)
Parameter VIN_3.3V to VO_3.3V VIN_3.3VAUX to VO_VAUX VIN_1.5V to VO_1.5V Condition CL(3.3V) = 0.1 F Io(3.3V) = 0 A CL(AUX) = 0.1 F, Io(AUX) = 0 A CL(1.5V) = 0.1 F Io(1.5V) = 0 A CL(3.3V)=100F RL = VO_3.3V/1.0 A CL(3.3V) = 100 F RL = VO_VAUX/0.25 A CL(3.3V) = 100F RL = VO_1.5V/0.5 A Min 0.02 0.02 0.02 0.05 0.05 0.05 Typ Max 1.0 1.0 1.0 ms 1.0 1.0 1.0 Unit
tPD
Propagation delay VIN_3.3V to VO_3.3V VIN_3.3VAUX to VO_VAUX VIN_1.5V to VO_1.5V
15/19
Package mechanical data
STMEC001
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 4. QFN16 (3 x 3 mm) package outline
E
A K A1
E2
e D b K r D2
A3
1. Drawing not to scale.
L
Table 13.
Symbol
QFN16 (3 x 3 mm) mechanical data
millimeters Min Typ 0.90 0.02 0.20 0.18 0.25 3.00 1.55 1.70 3.00 1.55 1.70 0.50 0.20 0.30 0.40 0.09 0.50 0.012 0.006 1.80 0.061 1.80 0.061 0.30 0.007 Max 1.00 0.05 Min 0.032 inches Typ 0.035 0.001 0.008 0.010 0.118 0.067 0.118 0.067 0.020 0.008 0.016 0.020 0.071 0.071 0.012 Max 0.039 0.002
A A1 A3 b D D2 E E2 e K L r
0.80
16/19
STMEC001 Figure 5. TSSOP20 package outline
Package mechanical data
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0087225C
1. Drawing not to scale.
Table 14.
Symbol
TSSOP20 mechanical data
millimeters Min Typ Max 1.2 0.05 0.8 0.19 0.09 6.4 6.2 4.3 6.5 6.4 4.4 0.65 BSC 0 0.45 0.60 8 0.75 0 0.018 0.024 1 0.15 1.05 0.30 0.20 6.6 6.6 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 Min inches Typ Max 0.047 0.006 0.041 0.012 0.0079 0.260 0.260 0.176
A A1 A2 b c D E E1 e K L
17/19
Revision history
STMEC001
9
Revision history
Table 15.
Date 02-Aug-2006 08-Feb-2007
Document revision history
Revision 1 2 First release Replaced TSSOP24 package information with QFN16 Modified title, added RSW values for QFN16 inTable 7 on page 10 , small text changes, layout restructure, content reworked to improve readability in Section 4.1: Power states description on page 9, modified Figure 2: STMEC001 block diagram on page 6 Modified: Figure 2 and Table 2: Pin assignments on page 4 and Table 5: Power states on page 9, minor text changes. Change
18-Oct-2007
3
17-Apr-2008
4
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STMEC001
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