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| NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P5504EVG SOP-8 Lead-Free D PRODUCT SUMMARY V(BR)DSS -40V RDS(ON) 55m ID -5.5A 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -40 20 -5.5 -4.5 -20 2.5 1.3 -55 to 150 275 UNITS V V TC = 25 C TC = 70 C ID IDM A TC = 25 C TC = 70 C PD Tj, Tstg TL W Operating Junction & Storage Temperature Range Lead Temperature ( /16" from case for 10 sec.) THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Ambient 1 2 1 C SYMBOL RJA TYPICAL MAXIMUM 50 UNITS C / W Pulse width limited by maximum junction temperature. Duty cycle 1% ELECTRICAL CHARACTERISTICS (TC = 25 C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current1 Drain-Source On-State Resistance1 Forward Transconductance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) gfs VGS = 0V, ID = -250A VDS = VGS, ID = -250A VDS = 0V, VGS = 20V VDS = -32V, VGS = 0V VDS = -30V, VGS = 0V, TJ = 125 C VDS = -5V, VGS = -10V VGS = -4.5V, ID = -4.5A VGS = -10V, ID = -5.5A VDS = -10V, ID = -5.5A -20 65 38 11 94 55 -40 -1 -1.5 -2.5 250 nA 1 10 A A m S V LIMITS UNIT MIN TYP MAX SEP-30-2004 1 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P5504EVG SOP-8 Lead-Free DYNAMIC Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge 2 2 Ciss Coss Crss Qg Qgs Qgd 2 690 VGS = 0V, VDS = -10V, f = 1MHz 310 75 14 VDS = 0.5V(BR)DSS, VGS = -10V, ID = -5.5A 2.2 1.9 6.7 VDS = -20V, ID -1A, VGS = -10V, RGS = 6 9.7 13.4 19.4 nS nC pF Gate-Source Charge Gate-Drain Charge Rise Time2 Turn-Off Delay Time Fall Time2 2 Turn-On Delay Time td(on) tr 2 td(off) tf 19.8 35.6 12.3 22.2 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 C) Continuous Current Pulsed Current 3 IS ISM VSD trr Qrr IF = IS, VGS = 0V IF = -5 A, dlF/dt = 100A / S 15.5 7.9 -1.3 -2.6 -1 A V nS nC Forward Voltage1 Reverse Recovery Time Reverse Recovery Charge 1 2 Pulse test : Pulse Width 300 sec, Duty Cycle 2 . Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH "P5504EVG", DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. SEP-30-2004 2 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P5504EVG SOP-8 Lead-Free TYPICAL PERFORMANCE CHARACTERISTICS 100 -Is - Reverse Drain Current(A) V GS = 0V 10 T A = 125 C 1 0.1 25 C -55 C 0.01 0.001 0 0.8 1.0 1.2 0.2 0.6 0.4 -VSD - Body Diode Forward Voltage(V) 1.4 SEP-30-2004 3 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P5504EVG SOP-8 Lead-Free SEP-30-2004 4 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P5504EVG SOP-8 Lead-Free SOIC-8(D) MECHANICAL DATA mm Dimension Min. A B C D E F G 1.35 0.1 4.8 3.8 5.8 0.38 mm Dimension Max. 5.0 4.0 6.2 0.51 H I J K L 1.75 0.25 M N 0 Typ. 4.9 3.9 6.0 0.445 1.27 1.55 0.175 Min. 0.5 0.18 Typ. 0.715 0.254 0.22 4 Max. 0.83 0.25 8 SEP-30-2004 5 |
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