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0.35m 20MHZ-170MHZ FSPLL
AL2007LA
GENERAL DESCRIPTION
The AL2007LA is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macrofunctions provide frequency multiplication capabilities. The output clock frequency Fout is related to the reference input clock frequency Fin by the following equation: Fout = ( m*Fin ) / ( p* 2S) Where, Fout is the output clock frequency. Fin is the reference input clock frequency. m,p and s are the values for programmable dividers. AL2007LA consists of a phase/Frequency Detector(PFD), a Charge Pump an External Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as shown in Figure1.
FEATURES
-- 0.35um CMOS device technology -- 3.3 Volt Single power supply -- VCO frequency range: 60~170MHz -- Output frequency range: 20~170MHz -- Jitter 150ps -- Duty ratio 40% to 60% at 170MHz -- Frequency changed by programmable divider -- Power down mode IMPORTANT NOTICE Please contact SEC application engineer to confirm the proper selection of M,P,S value.
FUNCTIONAL BLOCK DIAGRAM
Fin
Pre Divider P
PFD
Charge Pump
Loop Filter (External)
VCO
Post Scaler S
Fout
Main Divider M
Figure 1. Phase Lockd Loop Block Diagram
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AL2007LA
0.35m 20MHZ-170MHZ FSPLL
CORE PIN DESCRIPTION
Name VDD VSS VDDA VSSA VBB FIN FILTER FOUT PWRDN I/O Type DP DG AP AG AB/DB DI AO DO DI I/O Pad vddd vssd vdda vssa vbba picc_bb poar50_bb pot12_bb picc_bb Digital power supply Digital ground Analog power supply Analog ground Analog/Digital sub bias Power PLL clock input - Pump out is connected to Filter - A capacitor is connected between the pin and analog ground 20MHz~170MHz clock output FSPLL clock power down. - PWRDN is High, PLL do not operating under this condition. - If isn't used this pin, tied to VSS. The values for 6bit programmable pre-divider. The values for 8bit programmable main divider. The values for 2bit programmable post scaler. Pin Description
P[5:0] M[7:0] S[1:0] I/O Type Abbr. -- AI: Analog Input -- DI: Digital Input -- AO: Analog Output -- DO: Digital Output
DI DI DI
picc_bb picc_bb picc_bb
-- AB: Analog Bidirectional -- DB: Digital Bidirectional -- AP: Analog Power -- DP: Digital Power -- AG: Analog Ground -- DG: Digital Ground
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0.35m 20MHZ-170MHZ FSPLL
AL2007LA
CORE CONFIGURATION
FIN PWRDN M[7:0] M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7] P[0] P[1] P[2] P[3] P[4] P[5] S[0] S[1]
FOUT
FILTER
AL2007LA
P[5:0]
S[1:0]
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AL2007LA
0.35m 20MHZ-170MHZ FSPLL
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Voltage on Any Digital Pin Storage Temperature Symbol VDD VDDA Vin Tstg Value -0.3 to 3.8 Vss-0.3 to Vdd+0.3 -45 to 125 Unit V V C Applicable pin VDD,VDDA,VSS,VSSA P[5:0],M[7:0],S[1:0] PWRDN -
NOTES: 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5K resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Differential External Loop Filter Capacitance Operating Temperature Symbol VDD - VDDA LF Topr 0 Min -0.1 Typ 0 820 70 Max +0.1 Unit V pF C
NOTE: It is strongly recommended that all the supply pins (VDDA, VDD) be powered from the same source to avoid power latch-up.
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0.35m 20MHZ-170MHZ FSPLL
AL2007LA
DC ELECTRICAL CHARACTERISTICS
Characteristics Operating Voltage Digital Input Voltage High Digital Input Voltage Low Dynamic Current (CORE Level without I/O Cell) Power Down Current Symbol VDD/VDDA Vih Vil Idd Ipd Min 3.15 2.0 0.8 3.5 120 Typ 3.3 Max 3.45 Unit V V V mA uA
AC ELECTRICAL CHARACTERISTICS
Characteristics Input Frequency Output Clock Frequency VCO Output Clock Frequency Input Clock Duty Cycle Output Clock Duty Cycle Locking Time Cycle to Cycle Jitter Symbol FIN FOUT Fvco TID TOD TLT TJCC -150 Min 3 20 20 40 40 Typ 14.318 Max 40 170 170 60 60 150 +150 Unit MHz MHz MHz % % us ps
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AL2007LA
0.35m 20MHZ-170MHZ FSPLL
FUNCTION DESCRIPTION
A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in frequency as well as in phase. In this application, it includes the following basic blocks. -- The voltage-controlled oscillator to generate the output frequency -- The divider P devides the reference frequency by p -- The divider M devides the VCO output frequency by m -- The divider S divides the VCO output frequency by s -- The phase frequency detector detects the phase difference between the reference frequency and the output frequency (after division) and controls the charge pump voltage. -- The loop filter removes high frequency components in charge pump voltage and does smooth and clean control of VCO The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL can be locked in the desired frequency. Fout = m * Fin / p*s If Fin = 14.318MHz, and m=M+8 , p=P+2, s=2^S Digital data format: Main Divider M7,M6,M5,M4,M3,M2,M1,M0
NOTES: 1. S[1] - S[0]: Output Frequency Scaler 2. M[7] - M[0]: VCO Frequency Divider 3. P[5] - P[0]: Reference Frequency Input Divider
Pre Divider P5,P4,P3,P2,P1,P0
Post Scaler S0,S1
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0.35m 20MHZ-170MHZ FSPLL
AL2007LA
OUTPUT FREQUENCY EQUATION & TABLE
Frequency Equation :
Table 1. Example of Divider Ratio
M7 0 M6 1 M5 0 M4 1 M3 0 M2 1 M1 0 M0 1
FOU T =
(m+8) (p+2) x 2 S
P6 0 P5 1 P4 0
x F IN
P3 1 P2 0 P1 1 P0 0 p P (p+2) S1 0 S0 0 2S
m 85
M (m+8) 93
42
44
1
NOTES: 1. Don't set the P or M as zero, that is 000000 / 00000000 2. The proper range of P and M : 1<=P<=62, 1<=M<=248 3. The P and M must be selected considering stability of PLL and VCO output frequency range 4. Please consult with SEC application engineer to select the proper P, M and S values
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AL2007LA
0.35m 20MHZ-170MHZ FSPLL
CORE EVALUATION GUIDE
For the embedded PLL, we must consider the test circuits for the embedded PLL core inmultiple applications. Hence the following requirements should be satisfied. -- The FILTER and FOUT pins must be bypassed for external test. -- For PLL test (Below 2 examples), it is needed to control the dividers - M[7:0],P[5:0] and S[1:0] -that generate multiple clocks. Example #1. Registers can be used for easy control of divider values. Example #2. N sample bits of 16-bit divider pins can be bypassed for test using MUX.
3.3V Power
Digital
3.3V Analog Power
External Clock Source FIN
GND
GND
VDD VSS
VDDA VSSA VBBA
FOUT PWRDN M[7:0]
AL2007LA
FILTER
#1.16bit Register Block
P[5:0]
820pF S[1:0] VSSA
Select Pin
NOTES
Test Pins of N Sample bits
Internal Divider Signal Line
#2 M U X
: 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 103 CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED
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0.35m 20MHZ-170MHZ FSPLL
AL2007LA
CORE LAYOUT GUIDE
-- The digital power(VDD,VSS) and the analog power(VDA,VSSA) must be dedicated to PLL only and seperated. If the dedicated VDD and VSS is not allowed that of the least power consuming block is shared with the PLL. -- The PIA pad is used as a FILTER pad that contains only ESD production diodes without any resistors and buffers. -- The FOUT and FILTER pins must be placed far from the internal signals in order to avoid overlapping signal lines. -- The blocks having a large digital switching current must be located away from the PLL core. -- The PLL core must be shielded by guardring. -- For the FOUT pad, you can use a custom drive buffer or POT12 buffer considering the drive current.
WITHOUT XTAL-DRIVER USERS GUIDE
-- There are two crystal driver cell (XTAL-OSC and PSOSCM2) options for the AL2007LA PLL core. 1. If the crystal component not used , an external clock source is applied to the FIN * Please contact an SEC application engineer when using a crystal. 2. If the crystal component not used , an external clock I/O Buffer offered from Samsung's STD90 library is recommanded for use - When implementing an embedded PLL block, the following pins must be bypassed externally for testing the PLL locking function: * Without Xtal-driver : FIN,FILTER,FOUT,VDDA,VSSA,VDD and VSS.
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AL2007LA
0.35m 20MHZ-170MHZ FSPLL
FILTER
FOUT
VDDA VSSA FIN VDD VSS VBBA
Used PICC_BB PAD
Divider P
PFD &CP
LF
VCO
Scaler S
PWRDN
Divider M
P[5:0] M[7:0] S[1:0] MUX
Glue Logic
* Divider Bus
* Optional Test Pins
Figure 1. The example of PLL block without crystal component (Normal Case)
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0.35m 20MHZ-170MHZ FSPLL
AL2007LA
PACKAGE CONFIGURATION
2bit Post Scaler Dummy Test Block Control pins 3.3V Digital PAD Power C
L H L H L H L H
3.3V I/O Power C
28 27 26 25
36
35
34
33
32
31
30
29
8bit Main Divider
L L L L L L L L L L L L H H H H H H H H H H H H
V D D 37 M0 D
38 M1 39 M2 40
V D D D
V S S D
V S S D
S 0
S 1
T S E L 0
T S E L 1
V D D O
V S S O
N C
N C NC
24
FOUT 23
M3
AL2007LA
C
10uF 103
NC NC
22 21
41 M4 42 M5 43 M6 44
VBBA 20 VBBA 19 PWRDN 18 FILTER NC
17 16
H L
820pF
External Clock Source
M7
45 P0 46 P1 47 P2 48 P3
FIN 15 VDDA 14 V S S A
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6bit Pre Divider Input
P 4
1
P 5
2
N C
3
N C
4
N C
5
N C
6
N C
7
N C
8
N C
9
N C
10
V VDDA S S A
12
13
C
3.3V Analog Power
H L
H L
NOTES: 1. TSEL0,TSEL1 pins are internal dummy block test pins. 2. NC is Noconnection pin
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AL2007LA
0.35m 20MHZ-170MHZ FSPLL
PACKAGE PIN DESCRIPTION
Name VDDD VSSD PWRDN Pin No 35,36 33,34 18 I/O Type DP DG DI Digital ground FSPLL clock power down -PWRDN is High, PLL do not operating under this condition. - If isn't used this pin, tied to VSS. Pre-Divider Input(LSB) Analog power supply Analog ground Analog / Digtal Sub Bias Power Crystal input or external FREF input 20MHZ~170MHz clock output Pump out is connected to the FILTER. A 820pF Capcitor is connected between the pin and analog pin FOUT divide control pins. -End users used not this pins, tied to VDD or VSS FOUT divide control pins. -End users used not this pins, tied to VDD or VSS Post scaler input 8bit main divider input I/O PAD Power I/O PAD Ground Pin Description Digital power supply
P[0]~P[5] VDDA VSSA VBBA FIN FOUT FILTER
1,2,45~48 13,14 11,12 19,20 15 22 17
DI AP AG AB/DB AI DO AO
TSEL0 TSEL1 S[0]~S[1] M[0]~M[7] VDDO VSSO
30 29 31,32 37~44 28 27
DI DI DI DI PP PG
NOTE: I/O TYPE PP and PG denote PAD power and PAD ground respectively.
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0.35m 20MHZ-170MHZ FSPLL
AL2007LA
DESIGN CONSIDERATIONS
The following design consideratios apply: * * * * * Phase tolerance and jitter are independent of the PLL frequency. Jitter is affected by the noise frequency in the power(VDD/VSS,VDDA/VSSA). It increases when the noise level increases. A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels such as TTL may degrade the tolerances. The use of two, or more PLLs requires special design considerations. Please consult your application engineer for more information. The following apply to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - Use wide PCB traces for POWER(VDD/VSS, VDDA/VSSA) connections to the PLL core. Seperate the traces from the chip's VDD/VSS,VDDA/VSSA supplies. - Use proper VDD/VSS,VDDA/VSSA de-coupling. - Use good power and ground sources on the board. - Use Power VBB for minimize substrate noise * * * The PLL core should be placed as close as possible to the dedicated loop filter and analog Power and ground pins. It is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL I/O cells. Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement restriction
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AL2007LA
0.35m 20MHZ-170MHZ FSPLL
FEEDBACK REQUEST
Thank you for having an interest in our products. Please fill out this form, especially the items which you want to request. Parameter Process Supply voltage (VDD) Input frequency (FIN) Output frequency (FOUT) Cycle to cycle jitter (TJCC) 100M ~ 200M 200M ~ 300M 300M ~ 400M 400M ~ 500M Period jitter (TJP) 100M ~ 200M 200M ~ 300M 300M ~ 400M 400M ~ 500M Output duty ratio (TOD) Lock up time (TLT) Dynamic current Stand by current Filter capacitor -- How many PLLs are embedded in your system ? -- Do you need synchronization between input clock and output clock ? -- Do you need another spec of jitter ? Parameter Long-term jitter (TJLT) Tracking Jitter (TJT) If you have another special request, please describe below. Customer Unit psec (pk-pk) psec (pk-pk) Customer SEC Unit
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0.35m 20MHZ-170MHZ FSPLL
AL2007LA
JITTER DEFINITION
Period Jitter Period jitter is the maximum deviation of output clock's transition from its ideal position.
T1 Ideal Cycle Fout
TJP
Cycle-to-Cycle Jitter Cycle-to-cycle jitter is the maximum deviation of output clock's transition from its corresponding position of the previous cycle.
Ti-1 Fout
Ti
Ti+1
TJCC = max (Ti+1 - Ti)
Long-Term Jitter Long-term jitter is the maximum deviation of output clock' transition from its ideal position, after many cycles. The term "many" depends on the application and the frequency.
Cycle 0
Cycle N
TJLP
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AL2007LA
0.35m 20MHZ-170MHZ FSPLL
Tracking Jitter Tracking jitter is the maximum deviation of output clock(FOUT)'s transition from input clock (FIN) position.
Trigger Fin
Delay
Fout
TJT
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