View VIRTEX-5_4203609.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

0
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
0 0
DS202 (v3.6) November 5, 2007
Advance Product Specification
VIRTEX-5 Electrical Characteristics
VirtexTM-5 FPGAs are available in -3, -2, -1 speed grades, with -3 having the highest performance. VIRTEX-5 DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This VIRTEX-5 data sheet, part of an overall set of documentation on the VIRTEX-5 family of FPGAs, is available on the Xilinx website: * * * * * * * * * * VIRTEX-5 Family Overview VIRTEX-5 User Guide VIRTEX-5 Configuration Guide VIRTEX-5 XtremeDSPTM Design Considerations VIRTEX-5 Packaging and Pinout Specification VIRTEX-5 RocketIOTM GTP Transceiver User Guide VIRTEX-5 Tri-mode Ethernet MAC User Guide VIRTEX-5 Integrated Endpoint Block User Guide for PCI Express(R) Designs VIRTEX-5 System Monitor User Guide VIRTEX-5 PCB Designer's Guide
All specifications are subject to change without notice.
VIRTEX-5 DC Characteristics
Table 1: Absolute Maximum Ratings Symbol
VCCINT VCCAUX VCCO VBATT VREF VIN(3)
Description
Internal supply voltage relative to GND Auxiliary supply voltage relative to GND Output drivers supply voltage relative to GND Key memory battery backup supply Input reference voltage 3.3V I/O input voltage relative to GND(4) (user and dedicated I/Os) 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) -0.5 to 1.1 -0.5 to 3.0 -0.5 to 3.75 -0.5 to 4.05 -0.5 to 3.75 -0.75 to 4.05 -0.75 to VCCO + 0.5 -0.75 to 4.05 -0.75 to VCCO + 0.5 -65 to 150 +220 +125
Units
V V V V V V V V V C C C
VTS
Voltage applied to 3-state 3.3V output(4) (user and dedicated I/Os) Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os)
TSTG TSOL TJ
Storage temperature (ambient) Maximum soldering temperature(2)
Maximum junction temperature(2)
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. For soldering guidelines and thermal considerations, see UG195: VIRTEX-5 Packaging and Pinout Specification on the Xilinx website. 3. 3.3V I/O absolute maximum limit applied to DC and AC signals. 4. For 3.3V I/O operation, refer to UG190: VIRTEX-5 User Guide, Chapter 6, 3.3V I/O Design Guidelines.
(c) 2006-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. PowerPC is a trademark of IBM, Inc. All specifications are subject to change without notice.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 1
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 2: Recommended Operating Conditions Symbol
VCCINT VCCAUX(1) VCCO(2,4,5)
Description
Internal supply voltage relative to GND, TJ = 0C to +85C Internal supply voltage relative to GND, TJ = -40C to +100C Auxiliary supply voltage relative to GND, TJ = 0C to +85C Auxiliary supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TJ = 0C to +85C Supply voltage relative to GND, TJ = -40C to +100C 3.3V supply voltage relative to GND, TJ = 0C to +85C 3.3V supply voltage relative to GND, TJ = -40C to +100C
Temperature Range
Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Min
0.95 0.95 2.375 2.375 1.14 1.14 GND - 0.20 GND - 0.20 GND - 0.20 GND - 0.20
Max
1.05 1.05 2.625 2.625 3.45 3.45 3.45 3.45 VCCO + 0.2 VCCO + 0.2 10 10
Units
V V V V V V V V V V mA mA V V
VIN
2.5V and below supply voltage relative to GND, TJ = 0C to +85C 2.5V and below supply voltage relative to GND, TJ = -40C to +100C
IIN VBATT(3)
Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. Battery voltage relative to GND, TJ = 0C to +85C Battery voltage relative to GND, TJ = -40C to +100C
1.0 1.0
3.6 3.6
Notes: 1. Recommended maximum voltage drop for VCCAUX is 10 mV/ms. 2. Configuration data is retained even if VCCO drops to 0V. 3. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX. 4. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. 5. The configuration supply voltage VCC_CONFIG is also known as VCCO_0
Table 3: DC Characteristics Over Recommended Operating Conditions Symbol
VDRINT VDRI IREF IL CIN IRPU(1)
Description
Data retention VCCINT voltage (below which configuration data might be lost) Data retention VCCAUX voltage (below which configuration data might be lost) VREF leakage current per pin Input or output leakage current per pin (sample-tested) Input capacitance (sample-tested) Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
Data Rate Min
0.75 2.0
Typ
Max Units
V V 10 10 8 A A pF A A A A A A nA n
20 10 5 3 2 5
150 90 45 30 15 110 150 1.0002 5.0
IRPD(1) IBATT(2) n r
Pad pull-down (when selected) @ VIN = 2.5V Battery supply current Temperature diode ideality factor Series resistance
Notes: 1. Typical values are specified at nominal voltage, 25C. 2. Maximum value specified for worst case process at 25C.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 2
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Important Note
Typical values for queiscent supply current are now specified at nominal voltage, 85C junction temperatures (Tj). Xilinx recommends analyzing static power consumption at Tj = 85C because the majority of designs operate near the high end of the commercial temperature range. Data sheets for older products (e.g., Virtex-4 devices) still specify typical quiescent supply current at Tj = 25C. Queiscent supply current is specified by speed grade for VIRTEX-5 devices. Use the XPOWERTM Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for conditions other than those specified in Table 4. Table 4: Typical Quiescent Supply Current Speed and Temperature Grade Symbol
ICCINTQ
Units
Description
Quiescent VCCINT supply current
Device
XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T
-3 (C)
480 507 651 689 1072 1115 1391 1448 N/A N/A N/A N/A 720 1092 N/A 1.5 1.5 2 2 3 3 4 4 N/A N/A N/A N/A 1.5 2 N/A
-2 (C & I)
480 507 651 689 1072 1115 1391 1448 2783 2844 4193 4267 720 1092 1924 1.5 1.5 2 2 3 3 4 4 8 8 12 12 1.5 2 4
-1 (C & I)
300 317 449 475 883 866 1109 1154 2278 2328 3432 3492 554 840 1475 1.5 1.5 2 2 3 3 4 4 8 8 12 12 1.5 2 4 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
ICCOQ
Quiescent VCCO supply current
XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 3
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 4: Typical Quiescent Supply Current (Continued) Speed and Temperature Grade Symbol
ICCAUXQ
Units
Description
Quiescent VCCAUX supply current
Device
XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T
-3 (C)
38 43 57 62 93 98 125 130 N/A N/A N/A N/A 49 74 N/A
-2 (C & I)
38 43 57 62 93 98 125 130 229 236 345 353 49 74 131
-1 (C & I)
38 43 57 62 93 98 125 130 229 236 345 353 49 74 131 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes: 1. Typical values are specified at nominal voltage, 85C junction temperatures (Tj). Industrial(I) grade devices have the same typical values as commercial (C) grade devices at 85C, but higher values at 100C. Use the XPE tool to calculate 100C values. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. The power supplies can be can be turned on in any sequence, though the specifications shown in Table 5 are for the recommended power-on sequence of VCCINT, VCCAUX, and VCCO. Xilinx does not specify the current for other power-on sequences. Table 5: Power-On Current for VIRTEX-5 Devices ICCINTMIN Device XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T Typ(1) 235 246 320 336 492 515 Max 76 86 114 124 186 196 ICCAUXMIN Typ(1) Max Typ(1) 50 50 50 50 100 100 ICCOMIN Max Units mA mA mA mA mA mA Table 5 shows the minimum current required by VIRTEX-5 devices for proper power-on and configuration. If the current minimums shown in Table 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. The FPGA must be configured after VCCINT is applied. Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 4
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 5: Power-On Current for VIRTEX-5 Devices (Continued) ICCINTMIN Device XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T Typ(1) 623 651 1023 1056 1470 1509 307 472 804 Max 250 260 458 472 690 706 98 148 262 ICCAUXMIN Typ(1) Max Typ(1) 100 100 150 150 150 150 50 50 100 ICCOMIN Max Units mA mA mA mA mA mA mA mA mA
Notes: 1. Typical values are specified at nominal voltage, 25C.
Table 6: Power Supply Ramp Time Symbol VCCINT VCCO VCCAUX Description Internal supply voltage relative to GND Output drivers supply voltage relative to GND Auxiliary supply voltage relative to GND Ramp Time 0.20 to 50.0 0.20 to 50.0 0.20 to 50.0 Units ms ms ms
SelectIOTM DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are choTable 7: SelectIO DC Input and Output Levels I/O Standard
LVTTL LVCMOS33, LVDCI33 LVCMOS25, LVDCI25 LVCMOS18, LVDCI18 LVCMOS15, LVDCI15 LVCMOS12 PCI33_3(5) PCI66_3(5) PCI-X(5)
sen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
VIL V, Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.2 -0.2 -0.2
VIH V, Min
2.0 2.0 1.7 65% VCCO 65% VCCO 65% VCCO 50% VCCO 50% VCCO 50% VCCO
VOL V, Max
3.45 3.45 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO VCCO VCCO
VOH V, Min
2.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.45 75% VCCO 75% VCCO 90% VCCO 90% VCCO 90% VCCO
IOL mA
Note(3) Note(3) Note(3) Note(4) Note(4) Note(6) Note(5) Note(5) Note(5)
IOH mA
Note(3) Note(3) Note(3) Note(4) Note(4) Note(6) Note(5) Note(5) Note(5)
V, Max
0.8 0.8 0.7 35% VCCO 35% VCCO 35% VCCO 30% VCCO 30% VCCO 35% VCCO
V, Max
0.4 0.4 0.4 0.45 25% VCCO 25% VCCO 10% VCCO 10% VCCO 10% VCCO
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 5
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 7: SelectIO DC Input and Output Levels (Continued) I/O Standard
GTLP GTL HSTL I_12 HSTL I(2)
VIL V, Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
VIH V, Min
VREF + 0.1 VREF + 0.05 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 50% VCCO + 0.1 50% VCCO + 0.1 VREF + 0.15 VREF + 0.15 50% VCCO + 0.15 50% VCCO + 0.15 VREF + 0.125 VREF + 0.125 50% VCCO + 0.125 50% VCCO + 0.125
VOL V, Max
- - VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3
VOH V, Min
N/A N/A 75% VCCO VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 - - VTT + 0.61 VTT + 0.81 - - VTT + 0.47 VTT + 0.60 - -
IOL mA
36 32 6.3 8 16 24 48 - - 8.1 16.2 - - 6.7 13.4 - -
IOH mA
N/A N/A 6.3 -8 -16 -8 -8 - - -8.1 -16.2 - - -6.7 -13.4 - -
V, Max
VREF - 0.1 VREF - 0.05 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 50% VCCO - 0.1 50% VCCO - 0.1 VREF - 0.15 VREF - 0.15 50% VCCO - 0.15 50% VCCO - 0.15 VREF - 0.125 VREF - 0.125 50% VCCO - 0.125 50% VCCO - 0.125
V, Max
0.6 0.4 25% VCCO 0.4 0.4 0.4 0.4 - - VTT - 0.61 VTT - 0.81 - - VTT - 0.47 VTT - 0.60 - -
HSTL II(2) HSTL III(2) HSTL IV(2) DIFF HSTL I(2)
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
DIFF HSTL II(2) SSTL2 I SSTL2 II DIFF SSTL2 I DIFF SSTL2 II SSTL18 I SSTL18 II DIFF SSTL18 I DIFF SSTL18 II
Notes: 1. Tested according to relevant specifications. 2. Applies to both 1.5V and 1.8V HSTL. 3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. 4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. 5. For more information on PCI33_3, PCI66_3, and PCI-X, refer to refer to UG190: VIRTEX-5 User Guide, Chapter 6, 3.3V I/O Design Guidelines. 6. Supported drive strengths of 2, 4, 6, or 8 mA.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 6
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
HT DC Specifications (HT_25)
Table 8: HT DC Specifications Symbol VCCO VOD VOD VOCM VOCM VID VID VICM VICM DC Parameter Supply Voltage Differential Output Voltage Change in VOD Magnitude Output Common Mode Voltage Change in VOCM Magnitude Input Differential Voltage Change in VID Magnitude Input Common Mode Voltage Change in VICM Magnitude RT = 100 across Q and Q signals RT = 100 across Q and Q signals Conditions Min 2.38 495 -15 495 -15 200 -15 440 -15 600 600 600 Typ 2.5 600 Max 2.63 715 15 715 15 1000 15 780 15 Units V mV mV mV mV mV mV mV mV
LVDS DC Specifications (LVDS_25)
Table 9: LVDS DC Specifications Symbol VCCO VOH VOL VODIFF VOCM VIDIFF VICM DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals 0.825 247 1.125 100 0.3 350 1.250 350 1.2 600 1.375 600 2.2 Conditions Min 2.38 Typ 2.5 Max 2.63 1.675 Units V V V mV V mV V
Extended LVDS DC Specifications (LVDSEXT_25)
Table 10: Extended LVDS DC Specifications Symbol VCCO VOH VOL VODIFF VOCM VIDIFF VICM DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals Common-mode input voltage = 1.25V Differential input voltage = 350 mV 0.715 350 1.125 100 0.3 Conditions Min 2.38 Typ 2.5 - - - 1.250 - 1.2 Max 2.63 1.785 - 820 1.375 1000 2.2 Units V V V mV V mV V
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 7
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower comTable 11: LVPECL DC Specifications Symbol
VOH VOL VICM VIDIFF
mon-mode ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see UG190: VIRTEX-5 User Guide, Chapter 6, SelectIO Resources.
DC Parameter
Output High Voltage Output Low Voltage Input Common-Mode Voltage Differential Input Voltage(1,2)
Min
VCC - 1.025 VCC - 1.81 0.6 0.100
Typ
1.545 0.795
Max
VCC - 0.88 VCC - 1.62 2.2 1.5
Units
V V V V
Notes: 1. Recommended input maximum voltage not to exceed VCCAUX + 0.2V. 2. Recommended input minimum voltage not to go below -0.5V.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 8
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
RocketIO GTP Transceiver Specifications
RocketIO GTP Transceiver DC Characteristics
Table 12: Absolute Maximum Ratings Symbol
MGTAVCCPLL MGTAVTTTX MGTAVTTRX MGTAVCC MGTAVTTRXC
Description
Analog supply voltage for the GTP_DUAL shared PLL relative to GND Analog supply voltage for the GTP_DUAL transmitters relative to GND Analog supply voltage for the GTP_DUAL receivers relative to GND Analog supply voltage for the GTP_DUAL common circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTP_DUAL column -0.5 to 1.32 -0.5 to 1.32 -0.5 to 1.32 -0.5 to 1.32 -0.5 to 1.32
Units
V V V V V
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 13: Recommended Operating Conditions(1)(2) Symbol
MGTAVTTTX(1) MGTAVTTRX(1) MGTAVCC(1)
Description
Min
1.14 1.14 1.14 0.95 1.14
Max
1.26 1.26 1.26 1.05 1.26
Units
V V V V V
MGTAVCCPLL(1) Analog supply voltage for the GTP_DUAL shared PLL relative to GND Analog supply voltage for the GTP_DUAL transmitters relative to GND Analog supply voltage for the GTP_DUAL receivers relative to GND Analog supply voltage for the GTP_DUAL common circuits relative to GND
MGTAVTTRXC(1) Analog supply voltage for the resistor calibration circuit of the GTP_DUAL column
Notes: 1. Each voltage listed requires the filter circuit described in UG196: VIRTEX-5 RocketIO GTP Transceiver User Guide. 2. Voltages are specified for the temperature range of TJ = -40C to +100C.
Table 14: DC Characteristics Over Recommended Operating Conditions(2) Symbol
IMGTAVTTTX IMGTAVCCPLL IMGTAVTTRXC IMGTAVTTRX IMGTAVCC RREF
Description
GTP_DUAL tile transmitter termination supply current(3) GTP_DUAL tile shared PLL supply current GTP_DUAL tile resistor termination calibration supply current GTP_DUAL tile receiver termination supply current(3) GTP_DUAL tile internal analog supply current Precision reference resistor for internal calibration termination
Min
Typ
71 36 0.1 0.1 56
Max
90 60 0.5 0.5 110 50.5
Units
mA mA mA mA mA
49.5
50
Notes: 1. Typical values are specified at nominal voltage, 25C, with a 3.2 Gb/s line rate. 2. ICC numbers are given per GTP_DUAL tile with both GTP devices operating with default settings. 3. AC coupled TX/RX link.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 9
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 15: Quiescent Supply Current Symbol ICCINTQ Description Quiescent internal supply current Device XC5VLX30T XC5VLX50T XC5VLX85T XC5VLX110T XC5VLX220T XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T IVTTTXQ Quiescent transmitter supply current XC5VLX30T XC5VLX50T XC5VLX85T XC5VLX110T XC5VLX220T XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T IAVCCPLLQ Quiescent GTP_DUAL PLL supply current XC5VLX30T XC5VLX50T XC5VLX85T XC5VLX110T XC5VLX220T XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T IVTTRXCQ Quiescent receiver termination switching supply current XC5VLX30T XC5VLX50T XC5VLX85T XC5VLX110T XC5VLX220T XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T Typ(1) Max Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 10
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 15: Quiescent Supply Current (Continued) Symbol ITTRXQ Description Quiescent receiver termination supply current Device XC5VLX30T XC5VLX50T XC5VLX85T XC5VLX110T XC5VLX220T XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T IVCCQ Quiescent internal analog supply current XC5VLX30T XC5VLX50T XC5VLX85T XC5VLX110T XC5VLX220T XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T
Notes: 1. Typical values are specified at nominal voltage, 25C. 2. Given for entire die. Powered and unconfigured. 3. Unconnected (if channel is driven to voltage). 4. More accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.
Typ(1)
Max
Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 11
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
RocketIO GTP Transceiver DC Input and Output Levels
Table 16 summarizes the DC output specifications of the VIRTEX-5 RocketIO GTP Transceivers. Figure 1 shows the single-ended output voltage swing. Figure 2 shows the Table 16: GTP Transceiver DC Specifications Symbol
DVPPIN VIN VCMIN DVPPOUT VSEOUT VCMOUT RIN ROUT TOSKEW CEXT
peak-to-peak differential output voltage. Consult UG196: VIRTEX-5 RocketIO GTP Transceiver User Guide for further details.
DC Parameter
Differential peak-to-peak input voltage Absolute input voltage Common mode input voltage Differential peak-to-peak output voltage (1) Single-ended output voltage swing (1) Common mode output voltage Differential input resistance Differential output resistance Transmitter output skew Recommended external AC coupling
Conditions
External AC coupled 3.2 Gb/s External AC coupled > 3.2 Gb/s DC coupled MGTAVTTRX = 1.2V DC coupled MGTAVTTRX = 1.2V TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON Equation based MGTAVTTTX = 1.2V
Min
150 180 -400
Typ
Max
2000 2000 1200
Units
mV mV mV mV
800 1400 700 1200 - Amplitude/2 90 90 100 100 120 120 15
mV mV mV

ps nF
capacitor(2)
75
100
200
Notes: 1. The output swing and preemphasis levels are programmable using the attributes discussed in UG196:VIRTEX-5 RocketIO GTP Transceiver User Guide and can result in values lower than reported in this table. 2. Values outside of this range can be used as appropriate to conform to specific protocols and standards.
+V
P VSEOUT
ds202_01_051607
N 0
Figure 1: Single-Ended Output Voltage Swing
+V
0
DVPPOUT DVPPIN
-V
P-N
ds202_02_051607
Figure 2: Peak-to-Peak Differential Output Voltage
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 12
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics peak-to-peak differential clock input voltage swing. Consult UG196: VIRTEX-5 RocketIO GTP Transceiver User Guide for further details.
Table 17 summarizes the DC input specifications of the VIRTEX-5 RocketIO GTP Transceivers. Figure 3 shows the single-ended input voltage swing. Figure 4 shows the
Table 17: RocketIO GTP Clock DC Input Level Specification(1) Symbol
DVPPIN VSEIN RIN CEXT
DC Parameter
Differential peak-to-peak input voltage Single-ended input voltage Differential input resistance Required external AC coupling capacitor
Conditions
Min
200 100 80 75
Typ
800 400 105 100
Max
2000 1000 130 200
Units
mV mV
nF
Notes: 1. VMIN = 0V and VMAX = 1200mV
+V
P
VSEIN
N
0
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
ds202_03_051607
+V
P-N
0
DVPPIN
-V
ds202_04_051607
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 13
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
RocketIO GTP Switching Characteristics
Consult UG196:VIRTEX-5 RocketIO GTP Transceiver User Guide for further information. Table 18: GTP Transceiver Performance Speed Grade Symbol
FGTPMAX FGPLLMAX FGPLLMIN
Description
Maximum GTP transceiver data rate Maximum PLL frequency Minimum PLL frequency
-3
3.75 2.0 1.0
-2
3.75 2.0 1.0
-1
3.2 2.0 1.0
Units
Gb/s GHz GHz
Table 19: CRC Block Switching Characteristics Speed Grade Symbol
FCRC
Description
CRCCLK maximum frequency
-3
320
-2
320
-1
250
Units
MHz
Table 20: GTP Transceiver Reference Clock Switching Characteristics
All Speed Grades Symbol
FGCLK TRCLK TFCLK TDCREF TGJTT TLOCK TPHASE
Description
Reference clock frequency Reference clock rise time Reference clock fall time Reference clock duty cycle Reference clock total jitter, peak-peak (2) Clock recovery frequency acquisition time Clock recovery phase acquisition time range(1) CLK
Conditions
20% - 80% 80% - 20% CLK CLK Initial PLL lock Lock to data after PLL has relocked to the reference clock. Includes lock to reference time.
Min
60
Typ
200 200
Max
350 400 400 55 40 1 200
Units
MHz ps ps % ps ms s
45
50
Notes: 1. The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s. 2. Measured at the package pin.
TRCLK
80%
20%
TFCLK
ds202_05_100506
Figure 5: Reference Clock Timing Parameters
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 14
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 21: GTP User Clock Switching Characteristics(1) Speed Grade
Symbol
FTXOUT FRXREC TRX TRX2 TTX TTX2
Description
TXOUTCLK maximum frequency RXRECCLK maximum frequency RXUSRCLK maximum frequency RXUSRCLK2 maximum frequency TXUSRCLK maximum frequency TXUSRCLK2 maximum frequency
Conditions
-3
375 375 375
-2
375 375 375 350 187.5 375 350 187.5
-1
320 320 320 320 160 320 320 160
Units
MHz MHz MHz MHz MHz MHz MHz MHz
RXDATAWIDTH = 0 RXDATAWIDTH = 1 TXDATAWIDTH = 0 TXDATAWIDTH = 1
350 187.5 375 350 187.5
Notes: 1. Clocking must be implemented as described in UG196: VIRTEX-5 RocketIO GTP Transceiver User Guide
Table 22: GTP Transmitter Switching Characteristics
Symbol FGTX TRTX TFTX TLLSKEW VTXOOBVDPP TTXOOBTRANS TJ3.75 DJ3.75 TJ3.2 DJ3.2 TJ2.5 DJ2.5 TJ2.0 DJ2.0 TJ1.25 DJ1.25 TJ1.00 DJ1.00 TJ500 DJ500 TJ100 DJ100 Serial data rate range TX Rise time TX Fall time TX lane-to-lane skew(1) Electrical idle amplitude Electrical idle transition time Total Jitter(2) 3.75 Gb/s 3.20 Gb/s Jitter(2) 2.50 Gb/s 2.00 Gb/s Jitter(2) 1.25 Gb/s 1.00 Gb/s Jitter(2) 500 Mb/s 100 Mb/s Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Total Jitter(2) Description Min 0.1 140 120 2 + 500 ps 20 40 0.35 0.19 0.35 0.19 0.30 0.14 0.30 0.14 0.20 0.10 0.20 0.10 0.10 0.04 0.02 0.01 Typ Max FGTPMAX Units Gb/s ps ps UI mV ns UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI
Deterministic Jitter(2) Total Jitter(2) Deterministic Total Jitter(2)
Deterministic Jitter(2) Total Jitter(2) Deterministic Total Jitter(2)
Deterministic Jitter(2) Total Jitter(2) Deterministic
Notes: 1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites. 2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. 3. All jitter values are based on a Bit-Error Ratio of 1e-12.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 15
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 23: GTP Receiver Switching Characteristics Symbol
FGRX RXOOBVDPP RXSST RXRL RXPPMTOL Serial data rate RX oversampler enabled OOB detect threshold peak-to-peak Receiver spread-spectrum tracking(1) Run length (CID) Data/REFCLK PPM offset tolerance OOBDETECT_THRESHOLD = 100 Modulated @ 33 KHz Internal AC capacitor bypassed ACDR 2nd-order loop enabled -1000 0.1 60 -5000 105
Description
RX oversampler not enabled
Min 0.5
Typ
Max FGTPMAX 0.5 165 0 150 1000
Units Gb/s Gb/s mV ppm UI ppm
SJ Jitter Tolerance
JT_SJ3.75 JT_SJ3.2 JT_SJ2.50 JT_SJ2.00 JT_SJ1.00 JT_SJ500 JT_SJ500 JT_SJ100 Sinusoidal Jitter(2) Sinusoidal Jitter(2) Sinusoidal Sinusoidal Jitter(2) Jitter(2) 3.75 Gb/s 3.20 Gb/s 2.50 Gb/s 2.00 Gb/s 1.00 Gb/s 500 Mb/s 500 Mb/s OS 100 Mb/s OS 0.30 0.40 0.40 0.40 0.30 0.30 0.30 0.30 UI UI UI UI UI UI UI UI
Sinusoidal Jitter(2) Sinusoidal Jitter(2) Sinusoidal Sinusoidal Jitter(2) Jitter(2)
SJ Jitter Tolerance with Stressed Eye
JT_TJSE3.2 JT_SJSE3.2 Notes:
1. 2. 3. 4. Using PLL_RX_DIVSEL_OUT = 1. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter. Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled. All jitter values are based on a Bit Error Ratio of 1e-12.
Total Jitter with Stressed Eye(3) Sinusoidal Jitter with Stressed Eye(3)
3.20 Gb/s 3.20 Gb/s
0.87 0.30
UI UI
Ethernet MAC Switching Characteristics
Consult UG194:VIRTEX-5 Tri-mode Ethernet Media Access Controller User Guide for further information. Table 24: Maximum Ethernet MAC Performance Speed Grade Description
Ethernet MAC Maximum Performance
-3
-2
10/100/1000
-1
Units
Mb/s
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 16
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
System Monitor Analog-to-Digital Converter Specification
Table 25: Analog-to-Digital Specifications Parameter Symbol Comments/Conditions Min Typ Max Units
AVDD = 2.5V 2%, VREFP = 2.5V, VREFN = 0V, ADCCLK = 5.2 MHz, TA = TMIN to TMAX, Typical values at TA=+25C DC Accuracy: All external input channels such as VP/VN and VAUXP[15:0]/VAUXN[15:0], Unipolar Mode, and Common Mode = 0V Resolution Integral Nonlinearity Differential Nonlinearity Unipolar Offset Error(1) Bipolar Offset Gain Error(1) Bipolar Gain Error(1) Total Unadjusted Error (Uncalibrated) Total Unadjusted Error (Calibrated) Calibrated Gain Temperature Coefficient DC Common-Mode Reject Conversion Rate(2) Conversion Time - Continuous Conversion Time - Event T/H Acquisition Time DRP Clock Frequency ADC Clock Frequency CLK Duty cycle Analog Inputs(3) Dedicated Analog Inputs Input Voltage Range VP - VN Unipolar Operation Differential Inputs Unipolar Common Mode Range (FS input) Differential Common Mode Range (FS input) Bandwidth Auxiliary Analog Inputs Input Voltage Range VAUXP[0] /VAUXN[0] to VAUXP[15] /VAUXN[15] Unipolar Operation Differential Operation Unipolar Common Mode Range (FS input) Differential Common Mode Range (FS input) Bandwidth Input Leakage Current A/D not converting, ADCCLK stopped 0 -0.25 0 +0.3 10 1.0 0 -0.25 0 +0.3 20 1 +0.25 +0.5 +0.7 kHz A 1 +0.25 +0.5 +0.7 MHz Volts Volts tCONV tCONV tACQ DCLK ADCCLK Number of CLK cycles Number of CLK cycles Number of CLK cycles DRP clock frequency Derived from DCLK 4 8 1 40 250 5.2 60 MHz MHz % 26 32 21 CMRRDC TUE TUE Error(1) INL DNL No missing codes (TMIN to TMAX) Guaranteed Monotonic Uncalibrated Uncalibrated measured in bipolar mode Uncalibrated Uncalibrated measured in bipolar mode Deviation from ideal transfer function. VREFP - VREFN = 2.5V Deviation from ideal transfer function. VREFP - VREFN = 2.5V Variation of FS code with temperature VN = VCM = 0.5V 0.5V, VP - VN = 100mV 2 2 0.2 0.2 10 1 0.01 70 2 30 30 2 2 LSBs LSBs % % LSBs LSBs LSB/C dB 10 2 0.9 Bits LSBs LSBs
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 17
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 25: Analog-to-Digital Specifications (Continued) Parameter
Input Capacitance On-chip Supply Monitor Error On-chip Temperature Monitor Error External Reference Inputs(4) Positive Reference Input Voltage Range Negative Reference Input Voltage Range Input current Power Requirements Analog Power Supply Analog Supply Current AVDD AIDD Measured Relative to AVSS ADCCLK = 5.2 MHz 2.45 5 2.5 2.55 8 Volts mA VREFP VREFN IREF Measured Relative to VREFN Measured Relative to AGND ADCCLK = 5.2 MHz 2.45 -50 2.5 0 2.55 100 100 Volts mV A VCCINT and VCCAUX with calibration enabled -40C to +125C with calibration enabled
Symbol
Comments/Conditions
Min
Typ
10
Max
Units
pF
1.0 4
% Reading C
Notes: 1. Offset and gain errors are removed by enabling the System Monitor automatic gain calibration feature. See UG192: VIRTEX-5 System Monitor User Guide. 2. See "System Monitor Timing" in UG192: VIRTEX-5 System Monitor User Guide. 3. See "Analog Inputs" in UG192: VIRTEX-5 System Monitor User Guide for a detailed description. 4. Any variation in the reference voltage from the nominal VREFP = 2.5V and VREFN = 0V will result is a deviation from the ideal transfer function.This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing the supply voltage and reference to vary by 2% is permitted.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 18
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in VIRTEX-5 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the Switching Characteristics, page 21. Table 26 shows internal (register-to-register) performance. Table 26: Register-to-Register Performance Register-to-Register (with I/O Delays) Speed Grade Description
Basic Functions
16:1 Multiplexer 32:1 Multiplexer 64:1 Multiplexer 9 x 9 Logic Multiplier with 4 pipe stages 9 x 9 Logic Multiplier with 5 pipe stages 16-bit Adder 32-bit Adder 64-bit Adder Register to LUT to Register 16-bit Counter 32-bit Counter 64-bit Counter 550 550 511 468 550 550 550 423 550 550 550 428 500 500 467 438 500 500 500 377 500 500 500 381 450 450 407 428 428 450 447 323 450 450 450 333 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
-3
-2
-1
Units
Memory Cascaded block RAM (64K) Block RAM Pipelined Single-Port 512 x 36 bits Single-Port 4096 x 4 bits Dual-Port A: 4096 x 4 bits and B: 1024 x 18 bits Distributed RAM Single-Port 16 x 8 Single-Port 32 x 8 Single-Port 64 x 8 Dual-Port 16 x 8 Shift Register Chain 16-bit 32-bit 64-bit 550 550 550 500 500 500 450 450 438 MHz MHz MHz 550 550 550 500 500 500 450 450 450 MHz MHz MHz MHz 550 550 550 500 500 500 450 450 450 MHz MHz MHz 500 450 400 MHz
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 19
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 26: Register-to-Register Performance (Continued) Register-to-Register (with I/O Delays) Speed Grade Description
Dedicated Arithmetic Logic DSP48E Quad 12-bit Adder/Subtracter DSP48E Dual 24-bit Adder/Subtracter DSP48E 48-bit Adder/Subtracter DSP48E 48-bit Counter DSP48E 48-bit Comparator DSP48E 25 x 18 bit Pipelined Multiplier DSP48E Direct 4-tap FIR Filter Pipelined DSP48E Systolic n-tap FIR Filter Pipelined
Notes: 1. Deviced used is the XC5VLX50T- FF1136
-3
-2
-1
Units
550 550 550 550 550 550 510 550
500 500 500 500 500 500 458 500
450 450 450 450 450 450 397 450
MHz MHz MHz MHz MHz MHz MHz MHz
Table 27: Interface Performances Speed Grade Description
Networking Applications
-3
-2
-1
SFI-4.1 (SDR LVDS Interface) SPI-4.2 (DDR LVDS Interface)
Memory Interfaces
710 MHz 1.25 Gb/s
710 MHz 1.0 Gb/s
645 MHz 1.0 Gb/s
DDR DDR2 QDR II SRAM RLDRAM II
200 MHz 333 MHz 300 MHz 333 MHz
200 MHz 300 MHz 300 MHz 300 MHz
200 MHz 267 MHz 250 MHz 250 MHz
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 20
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Switching Characteristics
All values represented in this data sheet are based on speed specification version 1.57. Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. All specifications are always representative of worst-case supply voltage and junction temperature conditions. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 28 correlates the current status of each VIRTEX-5 device on a per speed grade basis. Table 28: VIRTEX-5 Device Speed Grade Designations Speed Grade Designations Device
XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T
Advance
Preliminary
Production
-3, -2, -1 -3, -2, -1 -3, -2, -1 -3, -2, -1 -3, -2, -1 -3, -2, -1 -3, -2, -1 -3, -2, -1 -2, -1 -2, -1 -2, -1 -2, -1 -3, -2, -1 -3, -2, -1 -2, -1
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all VIRTEX-5 devices.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 21
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 29 lists the production released VIRTEX-5 family member, speed grade, and the corresponding supported speed specification version and ISE software revisions. Table 29: VIRTEX-5 Production Software and Speed Specification Release Speed Grade Designations Device
XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T
-3
-2
ISE 9.2i SP2 v1.56 ISE 9.2i SP2 v1.56
-1
ISE 9.2i SP2 v1.56 ISE 9.2i SP2 v1.56 ISE 9.2i SP2 v1.56 ISE 9.2i SP2 v1.56
ISE 9.2i SP1 v1.55 ISE 9.2i SP1 v1.55 ISE 9.2i SP1 v1.55 ISE 9.2i SP1 v1.55
ISE 9.2i SP2 v1.56 ISE 9.2i SP2 v1.56 N/A N/A N/A N/A ISE 9.2i SP3 v1.57 N/A ISE 9.2i SP3 v1.57 ISE 9.2i SP3 v1.57 ISE 9.2i SP3 v1.57 ISE 9.2i SP3 v1.57 ISE 9.2i SP2 v1.56 ISE 9.2i SP3 v1.57
ISE 9.2i SP3 v1.57
Notes: 1. Blank entries indicate a device and/or speed grade in advance or preliminary status.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 22
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
IOB Pad Input/Output/3-State Switching Characteristics
Table 30 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. Table 30: IOB Switching Characteristics TIOPI I/O Standard -3
LVDS_25 LVDSEXT_25 HT_25 BLVDS_25 RSDS_25 (point to point) ULVDS_25 PCI33_3 PCI66_3 PCI-X GTL GTLP HSTL_I HSTL_II HSTL_III HSTL_IV HSTL_I _18 HSTL_II _18 HSTL_III _18 HSTL_IV_18 SSTL2_I SSTL2_II LVTTL, Slow, 2 mA LVTTL, Slow, 4 mA LVTTL, Slow, 6 mA LVTTL, Slow, 8 mA LVTTL, Slow, 12 mA LVTTL, Slow, 16 mA 0.80 1.01 0.80 0.80 0.80 0.80 0.62 0.62 0.62 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.62 0.62 0.62 0.62 0.62 0.62 Speed Grade
TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. Table 31 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
TIOOP
Speed Grade
TIOTP
Speed Grade
Units -1
1.44 1.49 1.40 1.58 1.44 1.41 2.38 2.38 1.80 1.86 1.93 1.79 1.74 1.85 1.83 1.77 1.72 1.85 1.81 1.87 1.76 5.01 3.41 3.29 2.61 2.46 2.34 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
0.90 1.16 0.90 0.90 0.90 0.90 0.70 0.70 0.70 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.70 0.70 0.70 0.70 0.70 0.70
-1
1.06 1.30 1.06 1.06 1.06 1.06 0.82 0.82 0.82 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 0.82 0.82 0.82 0.82 0.82 0.82
-3
1.13 1.17 1.10 1.24 1.13 1.10 1.85 1.85 1.40 1.47 1.51 1.42 1.39 1.44 1.44 1.40 1.36 1.45 1.41 1.48 1.40 4.10 2.87 2.66 2.09 1.94 1.84
-2
1.29 1.34 1.26 1.38 1.29 1.27 2.06 2.06 1.56 1.63 1.68 1.57 1.53 1.60 1.60 1.55 1.51 1.61 1.57 1.64 1.55 4.47 3.09 2.91 2.30 2.15 2.04
-1
1.44 1.49 1.40 1.58 1.44 1.41 2.38 2.38 1.80 1.86 1.93 1.79 1.74 1.85 1.83 1.77 1.72 1.85 1.81 1.87 1.76 5.01 3.41 3.29 2.61 2.46 2.34
-3
1.13 1.17 1.10 1.24 1.13 1.10 1.85 1.85 1.40 1.47 1.51 1.42 1.39 1.44 1.44 1.40 1.36 1.45 1.41 1.48 1.40 4.10 2.87 2.66 2.09 1.94 1.84
-2
1.29 1.34 1.26 1.38 1.29 1.27 2.06 2.06 1.56 1.63 1.68 1.57 1.53 1.60 1.60 1.55 1.51 1.61 1.57 1.64 1.55 4.47 3.09 2.91 2.30 2.15 2.04
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 23
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 30: IOB Switching Characteristics (Continued) TIOPI I/O Standard -3
LVTTL, Slow, 24 mA LVTTL, Fast, 2 mA LVTTL, Fast, 4 mA LVTTL, Fast, 6 mA LVTTL, Fast, 8 mA LVTTL, Fast, 12 mA LVTTL, Fast, 16 mA LVTTL, Fast, 24 mA LVCMOS33, Slow, 2 mA LVCMOS33, Slow, 4 mA LVCMOS33, Slow, 6 mA LVCMOS33, Slow, 8 mA LVCMOS33, Slow, 12 mA LVCMOS33, Slow, 16 mA LVCMOS33, Slow, 24 mA LVCMOS33, Fast, 2 mA LVCMOS33, Fast, 4 mA LVCMOS33, Fast, 6 mA LVCMOS33, Fast, 8 mA LVCMOS33, Fast, 12 mA LVCMOS33, Fast, 16 mA LVCMOS33, Fast, 24 mA LVCMOS25, Slow, 2 mA LVCMOS25, Slow, 4 mA LVCMOS25, Slow, 6 mA LVCMOS25, Slow, 8 mA LVCMOS25, Slow, 12 mA LVCMOS25, Slow, 16 mA LVCMOS25, Slow, 24 mA LVCMOS25, Fast, 2 mA LVCMOS25, Fast, 4 mA LVCMOS25, Fast, 6 mA LVCMOS25, Fast, 8 mA LVCMOS25, Fast, 12 mA LVCMOS25, Fast, 16 mA LVCMOS25, Fast, 24 mA 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.62 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 Speed Grade
TIOOP
Speed Grade
TIOTP
Speed Grade
Units -1
2.38 4.05 2.90 2.63 2.09 1.89 1.81 1.74 4.44 3.49 3.24 2.57 2.42 2.31 2.35 3.59 2.84 2.59 2.05 1.86 1.80 1.74 4.42 2.94 2.74 2.56 2.63 2.30 2.34 3.82 2.37 2.20 2.09 1.94 1.85 1.76 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70
-1
0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82
-3
1.87 3.32 2.32 2.10 1.65 1.47 1.41 1.36 3.63 2.82 2.61 2.06 1.95 1.86 1.87 2.94 2.27 2.06 1.61 1.45 1.40 1.35 3.67 2.37 2.19 2.05 2.10 1.84 1.83 3.14 1.89 1.74 1.66 1.52 1.43 1.40
-2
2.07 3.61 2.55 2.31 1.82 1.63 1.57 1.52 3.96 3.09 2.86 2.26 2.14 2.04 2.07 3.20 2.50 2.27 1.79 1.61 1.56 1.51 3.97 2.60 2.41 2.26 2.31 2.02 2.04 3.41 2.08 1.92 1.83 1.69 1.60 1.54
-1
2.38 4.05 2.90 2.63 2.09 1.89 1.81 1.74 4.44 3.49 3.24 2.57 2.42 2.31 2.35 3.59 2.84 2.59 2.05 1.86 1.80 1.74 4.42 2.94 2.74 2.56 2.63 2.30 2.34 3.82 2.37 2.20 2.09 1.94 1.85 1.76
-3
1.87 3.32 2.32 2.10 1.65 1.47 1.41 1.36 3.63 2.82 2.61 2.06 1.95 1.86 1.87 2.94 2.27 2.06 1.61 1.45 1.40 1.35 3.67 2.37 2.19 2.05 2.10 1.84 1.83 3.14 1.89 1.74 1.66 1.52 1.43 1.40
-2
2.07 3.61 2.55 2.31 1.82 1.63 1.57 1.52 3.96 3.09 2.86 2.26 2.14 2.04 2.07 3.20 2.50 2.27 1.79 1.61 1.56 1.51 3.97 2.60 2.41 2.26 2.31 2.02 2.04 3.41 2.08 1.92 1.83 1.69 1.60 1.54
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 24
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 30: IOB Switching Characteristics (Continued) TIOPI I/O Standard -3
LVCMOS18, Slow, 2 mA LVCMOS18, Slow, 4 mA LVCMOS18, Slow, 6 mA LVCMOS18, Slow, 8 mA LVCMOS18, Slow, 12 mA LVCMOS18, Slow, 16 mA LVCMOS18, Fast, 2 mA LVCMOS18, Fast, 4 mA LVCMOS18, Fast, 6 mA LVCMOS18, Fast, 8 mA LVCMOS18, Fast, 12 mA LVCMOS18, Fast, 16 mA LVCMOS15, Slow, 2 mA LVCMOS15, Slow, 4 mA LVCMOS15, Slow, 6 mA LVCMOS15, Slow, 8 mA LVCMOS15, Slow, 12 mA LVCMOS15, Slow, 16 mA LVCMOS15, Fast, 2 mA LVCMOS15, Fast, 4 mA LVCMOS15, Fast, 6 mA LVCMOS15, Fast, 8 mA LVCMOS15, Fast, 12 mA LVCMOS15, Fast, 16 mA LVCMOS12, Slow, 2 mA LVCMOS12, Slow, 4 mA LVCMOS12, Slow, 6 mA LVCMOS12, Slow, 8 mA LVCMOS12, Fast, 2 mA LVCMOS12, Fast, 4 mA LVCMOS12, Fast, 6 mA LVCMOS12, Fast, 8 mA 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.73 0.84 0.84 0.84 0.84 0.84 0.84 0.84 0.84 Speed Grade
TIOOP
Speed Grade
TIOTP
Speed Grade
Units -1
5.09 3.75 2.97 2.69 2.47 2.45 4.16 2.98 2.35 2.13 1.93 1.86 4.34 2.74 2.52 2.43 2.25 2.20 3.48 2.23 2.06 2.00 1.86 1.77 4.58 2.66 2.45 2.48 3.87 2.20 2.08 1.97 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.96 0.96 0.96 0.96 0.96 0.96 0.96 0.96
-1
0.89 0.89 0.89 0.89 0.89 0.89 0.89 0.89 0.89 0.89 0.89 0.89 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14
-3
4.20 3.03 2.37 2.15 1.95 1.93 3.41 2.36 1.87 1.69 1.51 1.44 3.50 2.17 1.99 1.91 1.74 1.71 2.80 1.76 1.62 1.57 1.43 1.37 3.58 2.10 2.00 1.91 3.05 1.71 1.58 1.52
-2
4.56 3.32 2.61 2.37 2.16 2.14 3.71 2.61 2.06 1.87 1.68 1.61 3.84 2.40 2.20 2.12 1.95 1.91 3.07 1.95 1.80 1.74 1.60 1.53 3.98 2.33 2.18 2.14 3.38 1.91 1.78 1.70
-1
5.09 3.75 2.97 2.69 2.47 2.45 4.16 2.98 2.35 2.13 1.93 1.86 4.34 2.74 2.52 2.43 2.25 2.20 3.48 2.23 2.06 2.00 1.86 1.77 4.58 2.66 2.45 2.48 3.87 2.20 2.08 1.97
-3
4.20 3.03 2.37 2.15 1.95 1.93 3.41 2.36 1.87 1.69 1.51 1.44 3.50 2.17 1.99 1.91 1.74 1.71 2.80 1.76 1.62 1.57 1.43 1.37 3.58 2.10 2.00 1.91 3.05 1.71 1.58 1.52
-2
4.56 3.32 2.61 2.37 2.16 2.14 3.71 2.61 2.06 1.87 1.68 1.61 3.84 2.40 2.20 2.12 1.95 1.91 3.07 1.95 1.80 1.74 1.60 1.53 3.98 2.33 2.18 2.14 3.38 1.91 1.78 1.70
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 25
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 30: IOB Switching Characteristics (Continued) TIOPI I/O Standard -3
LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 GTL_DCI GTLP_DCI LVPECL_25 HSTL_I_12 HSTL_I_DCI HSTL_II_DCI HSTL_II_T_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_II _T_DCI_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 DIFF_HSTL_I_18 DIFF_HSTL_I_DCI_18 DIFF_HSTL_I DIFF_HSTL_I_DCI DIFF_HSTL_II_18 DIFF_HSTL_II_DCI_18 DIFF_HSTL_II DIFF_HSTL_II_DCI 0.62 0.61 0.67 0.73 0.61 0.67 0.73 0.76 0.76 0.80 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.80 Speed Grade
TIOOP
Speed Grade
TIOTP
Speed Grade
Units -1
1.90 1.93 1.99 2.02 1.74 1.85 1.91 1.65 1.76 1.62 1.85 1.77 1.69 1.77 1.95 1.64 1.70 1.64 1.70 1.91 1.62 1.77 1.70 1.79 1.77 1.72 1.64 1.74 1.69 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
0.70 0.70 0.76 0.83 0.70 0.76 0.83 0.85 0.85 0.90 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.90 0.90 0.90 0.90 0.90 0.90 0.90 0.90
-1
0.82 0.82 0.89 0.98 0.82 0.89 0.98 1.00 1.00 1.06 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06
-3
1.50 1.55 1.65 1.58 1.36 1.43 1.48 1.36 1.37 1.28 1.45 1.41 1.34 1.41 1.57 1.34 1.36 1.30 1.36 1.55 1.31 1.40 1.36 1.42 1.41 1.36 1.30 1.39 1.34
-2
1.66 1.71 1.78 1.75 1.51 1.60 1.65 1.47 1.52 1.42 1.61 1.56 1.48 1.56 1.72 1.46 1.50 1.43 1.50 1.69 1.44 1.55 1.50 1.57 1.56 1.51 1.43 1.53 1.48
-1
1.90 1.93 1.99 2.02 1.74 1.85 1.91 1.65 1.76 1.62 1.85 1.77 1.69 1.77 1.95 1.64 1.70 1.64 1.70 1.91 1.62 1.77 1.70 1.79 1.77 1.72 1.64 1.74 1.69
-3
1.50 1.55 1.65 1.58 1.36 1.43 1.48 1.36 1.37 1.28 1.45 1.41 1.34 1.41 1.57 1.34 1.36 1.30 1.36 1.55 1.31 1.40 1.36 1.42 1.41 1.36 1.30 1.39 1.34
-2
1.66 1.71 1.78 1.75 1.51 1.60 1.65 1.47 1.52 1.42 1.61 1.56 1.48 1.56 1.72 1.46 1.50 1.43 1.50 1.69 1.44 1.55 1.50 1.57 1.56 1.51 1.43 1.53 1.48
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 26
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 30: IOB Switching Characteristics (Continued) TIOPI I/O Standard -3
SSTL2_I_DCI SSTL2_II_DCI SSTL2_II_T_DCI SSTL18_I SSTL18_II SSTL18_I_DCI SSTL18_II_DCI SSTL18_II_T_DCI DIFF_SSTL2_I DIFF_SSTL2_I_DCI DIFF_SSTL18_I DIFF_SSTL18_I_DCI DIFF_SSTL2_II DIFF_SSTL2_II_DCI DIFF_SSTL18_II DIFF_SSTL18_II_DCI 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.80 Speed Grade
TIOOP
Speed Grade
TIOTP
Speed Grade
Units -1
1.78 1.70 1.78 1.84 1.75 1.74 1.64 1.74 1.87 1.78 1.84 1.74 1.76 1.70 1.75 1.64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.90 0.90 0.90 0.90 0.90 0.90 0.90 0.90
-1
1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06
-3
1.42 1.34 1.42 1.46 1.39 1.39 1.30 1.39 1.48 1.42 1.46 1.39 1.40 1.34 1.39 1.30
-2
1.56 1.48 1.56 1.61 1.53 1.53 1.44 1.53 1.64 1.56 1.61 1.53 1.55 1.48 1.53 1.44
-1
1.78 1.70 1.78 1.84 1.75 1.74 1.64 1.74 1.87 1.78 1.84 1.74 1.76 1.70 1.75 1.64
-3
1.42 1.34 1.42 1.46 1.39 1.39 1.30 1.39 1.48 1.42 1.46 1.39 1.40 1.34 1.39 1.30
-2
1.56 1.48 1.56 1.61 1.53 1.53 1.44 1.53 1.64 1.56 1.61 1.53 1.55 1.48 1.53 1.44
Table 31: IOB 3-state ON Output Switching Characteristics (TIOTPHZ) Speed Grade Symbol TIOTPHZ Description T input to Pad high-impedance -3 0.88 -2 1.01 -1 1.12 Units ns
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 27
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 32 shows the test setup parameters used for measuring input delay. Table 32: Input Delay Measurement Methodology
I/O Standard
Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI, 66 MHz, 3.3V PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) GTL Plus HSTL (High-Speed Transceiver Logic), Class I & II HSTL, Class III & IV HSTL, Class I & II, 1.8V HSTL, Class III & IV, 1.8V SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V SSTL, Class I & II, 2.5V SSTL, Class I & II, 1.8V AGP-2X/AGP (Accelerated Graphics Port) LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V LDT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Electron-Coupled Logic), 2.5V LVTTL
Attribute
LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 PCI66_3 PCIX GTL GTLP HSTL_I, HSTL_II HSTL_III, HSTL_IV HSTL_I_18, HSTL_II_18 HSTL_III_18, HSTL_IV_18 SSTL3_I, SSTL3_II SSTL2_I, SSTL2_II SSTL18_I, SSTL18_II AGP LVDS_25 LVDSEXT_25 LDT_25 LVPECL_25
VL (1,2)
0 0 0 0 0
VH (1,2)
3.0 3.3 2.5 1.8 1.5
VMEAS
(1,4,5)
VREF (1,3,5)
- - - - - - - -
1.4 1.65 1.25 0.9 0.75
Per PCI Specification Per PCI Specification Per PCI-X Specification VREF - 0.2 VREF - 0.2 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 1.00 VREF - 0.75 VREF - 0.5 VREF - (0.2 x VCCO) 1.2 - 0.125 1.2 - 0.125 0.6 - 0.125 1.15 - 0.3 VREF + 0.2 VREF + 0.2 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 1.00 VREF + 0.75 VREF + 0.5 VREF + (0.2 x VCCO) 1.2 + 0.125 1.2 + 0.125 0.6 + 0.125 1.15 - 0.3 VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF 1.2 1.2 0.6 1.15
0.80 1.0 0.75 0.90 0.90 1.08 1.5 1.25 0.90 AGP Spec
Notes: 1. Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage. Parameters for all other DCI standards are the same as for the corresponding non-DCI standards. 2. Input waveform switches between VLand VH. 3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. 4. Input voltage level from which measurement starts. 5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 6.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 28
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setup shown in Figure 6. Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: 1. Simulate the output driver of choice into the generalized test setup, using values from Table 33. 2. Record the time to VMEAS . 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to VMEAS . 5. Compare the results of steps 2 and 4. The increase or decrease in delay yields the actual worst-case propagation delay (clock-to-input) of the PCB trace.
VREF
FPGA Output
RREF
VMEAS
(voltage level when taking delay measurement)
CREF
(probe capacitance)
ds202_06_041107
Figure 6: Generalized Test Setup Table 33: Output Delay Measurement Methodology Description LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS ), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V LVCMOS, 1.2V PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI, 66 MHz, 3.3V PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) GTL Plus HSTL (High-Speed Transceiver Logic), Class I HSTL, Class II HSTL, Class III HSTL, Class IV HSTL, Class I, 1.8V HSTL, Class II, 1.8V I/O Standard Attribute LVTTL (all) LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 (rising edge) PCI33_3 (falling edge) PCI66_3 (rising edge) PCI66_3 (falling edge) PCIX (rising edge) PCIX (falling edge GTL GTLP HSTL_I HSTL_II HSTL_III HSTL_IV HSTL_I_18 HSTL_II_18 RREF ( ) 1M 1M 1M 1M 1M 1M 25 25 25 25 25 25 25 25 50 25 50 25 50 25 CREF(1) ( pF ) 0 0 0 0 0 0 10 (2) 10 (2) 10 (2) 10 (2) 10 (3) 10 (3) 0 0 0 0 0 0 0 0 VMEAS (V) 1.4 1.65 1.25 0.9 0.75 0.75 0.94 2.03 0.94 2.03 0.94 2.03 0.8 1.0 VREF VREF 0.9 0.9 VREF VREF 3.3 1.2 1.5 0.75 0.75 1.5 1.5 0.9 0.9 VREF (V) 0 0 0 0 0 0 0 3.3 0 3.3
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 29
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 33: Output Delay Measurement Methodology (Continued) Description HSTL, Class III, 1.8V HSTL, Class IV, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V BLVDS (Bus LVDS), 2.5V LDT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V LVDCI/HSLVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI/HSLVDCI, 2.5V LVDCI/HSLVDCI, 1.8V LVDCI/HSLVDCI, 1.5V HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL, Class III & IV, with DCI HSTL, Class I & II, 1.8V, with DCI HSTL, Class III & IV, 1.8V, with DCI SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL, Class I & II, 2.5V, with DCI GTL (Gunning Transceiver Logic) with DCI GTL Plus with DCI
Notes: 1. CREF is the capacitance of the probe, nominally 0 pF. 2. Per PCI specifications. 3. Per PCI-X specifications.
I/O Standard Attribute HSTL_III_18 HSTL_IV_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II LVDS_25 LVDS_25 BLVDS_25 LDT_25 LVPECL_25 LVDCI_33, HSLVDCI_33 LVDCI_25, HSLVDCI_25 LVDCI_18, HSLVDCI_18 LVDCI_15, HSLVDCI_15 HSTL_I_DCI, HSTL_II_DCI HSTL_III_DCI, HSTL_IV_DCI HSTL_I_DCI_18, HSTL_II_DCI_18 HSTL_III_DCI_18, HSTL_IV_DCI_18 SSTL18_I_DCI, SSTL18_II_DCI SSTL2_I_DCI, SSTL2_II_DCI GTL_DCI GTLP_DCI
RREF ( ) 50 25 50 25 50 25 50 50 1M 50 1M 1M 1M 1M 1M 50 50 50 50 50 50 50 50
CREF(1) ( pF ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VMEAS (V) 1.1 1.1 VREF VREF VREF VREF VREF VREF 1.2 VREF 0.90 1.65 1.25 0.9 0.75 VREF 0.9 VREF 1.1 VREF VREF 0.8 1.0
VREF (V) 1.8 1.8 0.9 0.9 1.25 1.25 1.2 1.2 0 0.6 0 0 0 0 0 0.75 1.5 0.9 1.8 0.9 1.25 1.2 1.5
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 30
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 34: ILOGIC Switching Characteristics Speed Grade Symbol
Setup/Hold TICE1CK/TICKCE1 TISRCK/TICKSR TIDOCK/TIOCKD TIDOCKD/TIOCKDD Combinatorial TIDI TIDID Sequential Delays TIDLO TIDLOD TICKQ TRQ TGSRQ Set/Reset TRPW Minimum Pulse Width, SR/REV inputs D pin to Q1 pin using flip-flop as a latch without Delay DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY) CLK to Q outputs SR/REV pin to OQ/TQ out Global Set/Reset to Q outputs D pin to O pin propagation delay, no Delay DDLY pin to O pin propagation delay (using IODELAY) CE1 pin Setup/Hold with respect to CLK SR/REV pin Setup/Hold with respect to CLK D pin Setup/Hold with respect to CLK without Delay DDLY pin Setup/Hold with respect to CLK (using IODELAY)
Description
-3
-2
-1
Units
0.43 -0.24 0.85 -0.20 0.34 -0.12 0.31 -0.09
0.49 -0.24 1.00 -0.20 0.37 -0.12 0.33 -0.09
0.59 -0.24 1.22 -0.20 0.39 -0.12 0.36 -0.08
ns ns ns ns
0.24 0.20
0.26 0.22
0.30 0.26
ns ns
0.44 0.41 0.47 1.12 7.30
0.50 0.46 0.52 1.28 7.30
0.58 0.55 0.60 1.53 10.10
ns ns ns ns ns
0.78
0.95
1.20
ns, Min
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 31
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 35: OLOGIC Switching Characteristics Speed Grade Symbol
Setup/Hold TODCK/TOCKD TOOCECK/TOCKOCE TOSRCK/TOCKSR TOTCK/TOCKT TOTCECK/TOCKTCE Combinatorial TDOQ Sequential Delays TOCKQ TRQ TGSRQ Set/Reset TRPW Minimum Pulse Width, SR/REV inputs CLK to OQ/TQ out SR/REV pin to OQ/TQ out Global Set/Reset to Q outputs D1 to OQ out or T1 to TQ out D1/D2 pins Setup/Hold with respect to CLK OCE pin Setup/Hold with respect to CLK SR/REV pin Setup/Hold with respect to CLK T1/T2 pins Setup/Hold with respect to CLK TCE pin Setup/Hold with respect to CLK
Description
-3
-2
-1
Units
0.30 -0.21 0.16 -0.07 0.93 -0.20 0.28 -0.18 0.20 -0.06
0.36 -0.21 0.19 -0.07 1.02 -0.20 0.34 -0.18 0.23 -0.06
0.44 -0.21 0.23 -0.07 1.16 -0.20 0.41 -0.18 0.29 -0.06
ns ns ns ns ns
0.62
0.70
0.83
ns
0.61 1.63 7.30
0.62 1.89 7.30
0.62 2.27 10.10
ns ns ns
0.80
0.98
1.25
ns, Min
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 32
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 36: ISERDES Switching Characteristics Speed Grade Symbol
Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP TISCCK_CE / TISCKC_CE(2) TISCCK_CE2 / TISCKC_CE2(2) Setup/Hold for Data Lines TISDCK_D /TISCKD_D TISDCK_DDLY /TISCKD_DDLY TISDCK_DDR /TISCKD_DDR TISDCK_DDLY_DDR TISCKD_DDLY_DDR Sequential Delays TISCKO_Q Propagation Delays TISDO_DO D input to DO output pin CLKDIV to out at Q pin D pin Setup/Hold with respect to CLK DDLY pin Setup/Hold with respect to CLK (using IODELAY) D pin Setup/Hold with respect to CLK at DDR mode D pin Setup/Hold with respect to CLK at DDR mode (using IODELAY) BITSLIP pin Setup/Hold with respect to CLKDIV CE pin Setup/Hold with respect to CLK (for CE1) CE pin Setup/Hold with respect to CLKDIV (for CE2)
Description
-3
-2
-1
Units
0.10 0.00 0.43 -0.24 0.03 0.11
0.11 0.00 0.49 -0.24 0.04 0.13
0.12 0.00 0.59 -0.24 0.06 0.15
ns ns ns
0.34 -0.12 0.31 -0.09 0.34 -0.12 0.31 -0.09
0.37 -0.12 0.33 -0.09 0.37 -0.12 0.33 -0.09
0.39 -0.12 0.36 -0.08 0.39 -0.12 0.36 -0.08
ns ns ns ns
0.46
0.51
0.60
ns
0.20
0.22
0.26
ns
Notes: 1. Recorded at 0 tap value. 2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in TRACE report.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 33
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics Input Delay Switching Characteristics
Table 37: OSERDES Switching Characteristics Speed Grade Symbol
Setup/Hold TOSDCK_D/TOSCKD_D TOSDCK_T/TOSCKD_T(1) TOSDCK_T2/TOSCKD_T2(1) TOSCCK_OCE/TOSCKC_OCE TOSCCK_S TOSCCK_TCE/TOSCKC_TCE Sequential Delays TOSCKO_OQ TOSCKO_TQ Combinatorial TOSDO_TTQ TOSCO_OQ TOSCO_TQ T input to TQ Out Asynchronous Reset to OQ Asynchronous Reset to TQ Clock to out from CLK to OQ Clock to out from CLK to TQ D input Setup/Hold with respect to CLKDIV T input Setup/Hold with respect to CLK T input Setup/Hold with respect to CLKDIV OCE input Setup/Hold with respect to CLK SR (Reset) input Setup with respect to CLKDIV TCE input Setup/Hold with respect to CLK
Description
-3
-2
-1
Units
0.21 -0.02 0.28 -0.18 0.21 -0.03 0.16 -0.07 0.52 0.20 -0.06
0.24 -0.02 0.34 -0.18 0.24 -0.03 0.19 -0.07 0.58 0.23 -0.06
0.30 -0.02 0.41 -0.18 0.28 -0.03 0.23 -0.07 0.70 0.29 -0.06
ns ns ns ns ns ns
0.59 0.61
0.60 0.62
0.61 0.62
ns ns
0.62 1.57 1.63
0.70 1.82 1.89
0.83 2.19 2.27
ns ns ns
Notes: 1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 34
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 38: Input/Output Delay Switching Characteristics Speed Grade Symbol
TIDELAYRESOLUTION TIDELAYCTRLCO_RDY FIDELAYCTRL_REF
Description
IODELAY Chain Delay Resolution Reset to Ready for IDELAYCTRL REFCLK frequency
-3
-2 1/(64 x FREF x 1e6)(1)
-1
Units
ps
3.00 200.00 10 50.00 0 5
300
3.00 200.00 10 50.00 0 5
250
3.00 200.00 10 50.00 0 5
250
s MHz MHz ns Note 2 Note 2 MHz ns ns ns
IDELAYCTRL_REF_PRECISION REFCLK precision TIDELAYCTRL_RPW TIDELAYPAT_JIT Minimum Reset pulse width Pattern dependent period jitter in delay chain for clock pattern Pattern dependent period jitter in delay chain for randon data pattern (PRBS 23) TIODELAY_CLK_MAX TIODCCK_CE / TIODCKC_CE TIODCK_INC/ TIODCKC_INC TIODCK_RST/ TIODCKC_RST Maximum frequency of CLK input to IODELAY CE pin Setup/Hold with respect to CK INC pin Setup/Hold with respect to CK RST pin Setup/Hold with respect to CK
0.29 -0.06 0.18 0.02 0.25 -0.12
0.34 -0.06 0.20 0.04 0.28 -0.12
0.42 -0.06 0.24 0.06 0.33 -0.12
Notes: 1. Average Tap Delay at 200 MHz = 78 ps. 2. Units in ps, peak-to-peak per tap, in High Performance mode.
CLB Switching Characteristics
Table 39: CLB Switching Characteristics Speed Grade Symbol
Combinatorial Delays An - Dn LUT address to A TILO An - Dn LUT address to AMUX/CMUX An - Dn LUT address to BMUX_A TITO TAXA TAXB TAXC TAXD TBXB TBXD TCXB TCXD TDXD An - Dn inputs to A - D Q outputs AX inputs to AMUX output AX inputs to BMUX output AX inputs to CMUX output AX inputs to DMUX output BX inputs to BMUX output BX inputs to DMUX output CX inputs to CMUX output CX inputs to DMUX output DX inputs to DMUX output
Description
-3
-2
-1
Units
0.08 0.20 0.31 0.67 0.39 0.46 0.31 0.55 0.36 0.45 0.33 0.37 0.38
0.09 0.22 0.35 0.77 0.44 0.52 0.36 0.62 0.41 0.51 0.36 0.42 0.42
0.10 0.25 0.40 0.90 0.53 0.61 0.42 0.73 0.48 0.59 0.42 0.49 0.49
ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 35
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 39: CLB Switching Characteristics (Continued) Speed Grade Symbol
TOPCYA TOPCYB TOPCYC TOPCYD TAXCY TBXCY TCXCY TDXCY TBYP TCINA TCINB TCINC TCIND Sequential Delays TCKO Clock to AQ - DQ outputs
Description
An input to COUT output Bn input to COUT output Cn input to COUT output Dn input to COUT output AX input to COUT output BX input to COUT output CX input to COUT output DX input to COUT output CIN input to COUT output CIN input to AMUX output CIN input to BMUX output CIN input to CMUX output CIN input to DMUX output
-3 0.43 0.39 0.33 0.30 0.36 0.26 0.20 0.20 0.09 0.24 0.27 0.29 0.31
-2 0.50 0.44 0.37 0.34 0.42 0.30 0.22 0.22 0.10 0.27 0.30 0.32 0.35
-1 0.59 0.51 0.43 0.40 0.50 0.37 0.26 0.26 0.11 0.31 0.35 0.36 0.41
Units
ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
0.35
0.40
0.47
ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TDICK/TCKDI TRCK TCECK/TCKCE TSRCK/TCKSR TCINCK/TCKCIN Set/Reset TSRMIN TRQ TCEO FTOG SR input minimum pulse width Delay from SR or REV input to AQ - DQ flip-flops Delay from CE input to AQ - DQ flip-flops Toggle frequency (for export control) A - D input to CLK on A - D Flip Flops DX input to CLK when used as REV CE input to CLK on A - D Flip Flops SR input to CLK on A - D Flip Flops CIN input to CLK on A - D Flip Flops
0.36 0.19 0.37 0.18 -0.04 0.41 -0.19 0.14 0.14
0.41 0.21 0.42 0.20 -0.04 0.49 -0.19 0.16 0.16
0.49 0.24 0.51 0.23 -0.04 0.59 -0.19 0.18 0.19
ns, Min ns, Min ns, Min ns, Min ns, Min
0.90 0.74 0.46 1412
0.90 0.86 0.52 1265
0.90 1.03 0.63 1098
ns, Min ns, Max ns, Max MHz
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. These items are of interest for Carry Chain applications.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 36
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 40: CLB Distributed RAM Switching Characteristics Speed Grade Symbol
Sequential Delays TSHCKO TSHCKO_1 Clock to A - B outputs Clock to AMUX - BMUX outputs
Description
-3
-2
-1
Units
1.08 1.19
1.26 1.38
1.54 1.68
ns, Max ns, Max
Setup and Hold Times Before/After Clock CLK TDS/TDH TAS/TAH TWS/TWH TCECK/TCKCE Clock CLK TMPW TMCP Minimum pulse width Minimum clock period A - D inputs to CLK Address An inputs to clock WE input to clock CE input to CLK
0.72 0.20 0.41 0.20 0.34 -0.06 0.36 -0.08
0.84 0.22 0.46 0.22 0.39 -0.04 0.42 -0.07
1.03 0.26 0.54 0.27 0.46 -0.02 0.51 -0.06
ns, Min ns, Min ns, Min ns, Min
0.70 1.40
0.82 1.64
1.00 2.00
ns, Min ns, Min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 41: CLB Shift Register Switching Characteristics Speed Grade Symbol
Sequential Delays TREG TREG_MUX TREG_M31 Clock to A - D outputs Clock to AMUX - DMUX output Clock to DMUX output via M31 output
Description
-3
-2
-1
Units
1.23 1.33 0.99
1.43 1.55 1.15
1.73 1.87 1.38
ns, Max ns, Max ns, Max
Setup and Hold Times Before/After Clock CLK TWS/TWH TCECK/TCKCE TDS/TDH WE input CE input to CLK A - D inputs to CLK
0.21 -0.06 0.23 -0.08 0.57 0.07
0.24 -0.04 0.27 -0.07 0.66 0.09
0.29 -0.02 0.33 -0.06 0.78 0.11
ns, Min ns, Min ns, Min
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 37
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 41: CLB Shift Register Switching Characteristics (Continued) Speed Grade Symbol
Clock CLK TMPW Minimum pulse width
Description
-3
-2
-1
Units
0.60
0.70
0.85
ns, Min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
Block RAM and FIFO Switching Characteristics
Table 42: Block RAM and FIFO Switching Characteristics Speed Grade Symbol
Block RAM and FIFO Clock to Out Delays TRCKO_DO and TRCKO_DOR(1) Clock CLK to DOUT output (without output register)(2)(3) Clock CLK to DOUT output (with output register)(4)(5) Clock CLK to DOUT output with ECC (without output register)(2)(3) Clock CLK to DOUT output with ECC (with output register)(4)(5) Clock CLK to DOUT output with Cascade (without output register)(2) Clock CLK to DOUT output with Cascade (with output register)(4) TRCKO_FLAGS TRCKO_POINTERS TRCKO_ECCR Clock CLK to FIFO flags outputs(6) Clock CLK to FIFO pointer outputs(7) Clock CLK to BITERR (with output register) Clock CLK to BITERR (without output register) TRCKO_ECC Clock CLK to ECCPARITY in standard ECC mode Clock CLK to ECCPARITY in ECC encode only mode 1.79 0.61 2.64 0.66 2.10 0.91 0.76 1.10 0.66 2.48 1.29 0.77 1.92 0.69 3.03 0.77 2.44 1.07 0.87 1.26 0.77 2.85 1.47 0.89 2.19 0.82 3.61 0.93 2.94 1.30 1.02 1.48 0.93 3.41 1.74 1.05 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
Description
-3
-2
-1
Units
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 38
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 42: Block RAM and FIFO Switching Characteristics (Continued) Speed Grade Symbol
Setup and Hold Times Before/After Clock CLK TRCCK_ADDR/TRCKC_ADDR TRDCK_DI/TRCKD_DI ADDR inputs DIN inputs(8) DIN inputs with ECC in standard mode(8) TRDCK_DI_ECC/TRCKD_DI_ECC DIN inputs with ECC encode only(8) Block RAM Enable (EN) input CE input of output register Synchronous Set/ Reset (SSR) input Write Enable (WE) input WREN/RDEN FIFO inputs(9) 0.34 0.30 0.27 0.28 0.33 0.32 0.68 0.32 0.32 0.15 0.15 0.22 0.17 0.23 0.44 0.16 0.36 0.30 0.40 0.32 0.30 0.28 0.37 0.33 0.72 0.33 0.36 0.15 0.16 0.24 0.21 0.25 0.51 0.17 0.41 0.34 0.48 0.36 0.35 0.29 0.42 0.36 0.77 0.36 0.42 0.15 0.18 0.27 0.26 0.28 0.63 0.18 0.48 0.40 ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min
Description
-3
-2
-1
Units
TRCCK_EN/TRCKC_EN TRCCK_REGCE/TRCKC_REGCE TRCCK_SSR/TRCKC_SSR TRCCK_WE/TRCKC_WE TRCCK_WREN/TRCKC_WREN Reset Delays TRCO_FLAGS Maximum Frequency FMAX FMAX_CASCADE FMAX_FIFO FMAX_ECC
Reset RST to FIFO Flags/Pointers(10)
1.10
1.26
1.48
ns, Max
Block RAM in all modes Block RAM in Cascade mode FIFO in all modes Block RAM in ECC mode
550 500 550 415
500 450 500 375
450 400 450 325
MHz MHz MHz MHz
Notes: 1. Trace will report all of these parameters as TRCKO_DO. 2. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. 3. These parameters also apply to synchronous FIFO with DO_REG = 0. 4. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. 5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. 6. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. 7. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. 8. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B. 9. These parameters also apply to RDEN. 10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 39
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
DSP48E Switching Characteristics
Table 43: DSP48E Switching Characteristics Symbol Description Speed -3 -2 -1 Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/ TDSPCKD_{AA, BB, ACINA, BCINB} TDSPDCK_CC/TDSPCKD_CC {A, B, ACIN, BCIN} input to {A, B} register CLK C input to C register CLK 0.17 0.17 0.14 0.26 0.21 0.23 0.16 0.31 0.26 0.30 0.20 0.37 ns ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/ TDSPCKD_{AM, BM, ACINM, BCINM} {A, B, ACIN, BCIN} input to M register CLK 1.30 0.19 1.44 0.19 1.71 0.19 ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/ TDSPCKD_{AP, BP, ACINP, BCINP}_M TDSPDCK_{AP, BP, ACINP, BCINP}_NM/ TDSPCKD_{AP, BP, ACINP, BCINP}_NM TDSPDCK_CP/TDSPCKD_CP TDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/ TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP} {A, B, ACIN, BCIN} input to P register CLK using multiplier {A, B, ACIN, BCIN} input to P register CLK not using multiplier C input to P register CLK {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK 2.39 -0.30 1.35 -0.10 1.30 -0.13 1.06 0.11 2.74 -0.30 1.54 -0.10 1.42 -0.13 1.17 0.11 3.25 -0.30 1.83 -0.10 1.70 -0.13 1.31 0.11 ns ns ns ns
Setup and Hold Times of the CE Pins
TDSPCCK_{CEA1A, CEA2A, CEB1B, CEB2B}/ TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B} TDSPCCK_CECC/TDSPCKC_CECC TDSPCCK_CEMM/TDSPCKC_CEMM TDSPCCK_CEPP/TDSPCKC_CEPP {CEA1, CEA2A, CEB1B, CEB2B} input to {A, B} register CLK CEC input to C register CLK CEM input to M register CLK CEP input to P register CLK 0.24 0.21 0.19 0.17 0.25 0.18 0.56 0.01 0.28 0.25 0.21 0.21 0.29 0.21 0.63 0.01 0.33 0.31 0.26 0.28 0.36 0.26 0.73 0.01 ns ns ns ns
Setup and Hold Times of the RST Pins
TDSPCCK_{RSTAA, RSTBB}/ TDSPCKC_{RSTAA, RSTBB} TDSPCCK_RSTCC/ TDSPCKC_RSTCC TDSPCCK_RSTMM/ TDSPCKC_RSTMM TDSPCCK_RSTPP/TDSPCKC_RSTPP {RSTA, RSTB} input to {A, B} register CLK RSTC input to C register CLK RSTM input to M register CLK RSTP input to P register CLK 0.24 0.23 0.19 0.17 0.25 0.18 0.56 0.01 0.28 0.26 0.21 0.21 0.29 0.21 0.63 0.01 0.33 0.31 0.26 0.28 0.36 0.26 0.73 0.01 ns ns ns ns
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 40
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 43: DSP48E Switching Characteristics (Continued) Symbol
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM TDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT} {A, B} input to {P, CARRYOUT} output using multiplier {A, B} input to {P, CARRYOUT} output not using multiplier {C, CARRYIN} input to {P, CARRYOUT} output 2.78 1.59 1.50 3.22 1.77 1.67 3.84 2.22 2.08 ns ns ns
Description
Speed -3 -2 -1
Units
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{AACOUT, BBCOUT} TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT, CRYINPCOUT, CRYINCRYCOUT, CRYINMULTSIGNOUT} {A, B} input to {ACOUT, BCOUT} output {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier {C, CARRYIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 1.00 2.78 1.12 3.22 1.31 3.84 ns ns
1.72
1.92
2.42
ns
1.63
1.82
2.28
ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_M TDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_NM TDSPDO_{ACINACOUT, BCINBCOUT} TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT, BCINMULTSIGNOUT}_M TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT, BCINMULTSIGNOUT}_NM TDSPDO_{PCINP, CRYCINP, MULTSIGNINP, PCINCRYOUT, CRYCINCRYOUT, MULTSIGNINCRYOUT} TDSPDO_{PCINPCOUT, CRYCINPCOUT, MULTSIGNINPCOUT, PCINCRYCOUT, CRYCINCRYCOUT, MULTSIGNINCRYCOUT, PCINMULTSIGNOUT, CRYCINMULTSIGNOUT, MULTSIGNINMULTSIGNOUT} {ACIN, BCIN} input to {P, CARRYOUT} output using multiplier {ACIN, BCIN} input to {P, CARRYOUT} output not using multiplier {ACIN, BCIN} input to {ACOUT, BCOUT} output {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier {PCIN, CARRYCASCIN, MULTSIGNIN} input to {P, CARRYOUT} output {PCIN, CARRYCASCIN, MULTSIGNIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 2.78 1.59 1.00 2.78 3.22 1.77 1.12 3.22 3.84 2.22 1.31 3.84 ns ns ns ns
1.72
1.92
2.42
ns
1.30
1.45
1.82
ns
1.43
1.60
2.02
ns
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{PP, CRYOUTP} TDSPCKO_{CRYCOUTP, PCOUTP, MULTSIGNOUTP} CLK (PREG) to {P, CARRYOUT} output CLK (PREG) to {CARRYCASCOUT, PCOUT, MULTSIGNOUT} output 0.45 0.48 0.48 0.53 0.56 0.62 ns ns
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 41
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 43: DSP48E Switching Characteristics (Continued) Symbol
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{PM, CRYOUTM} TDSPCKO_{PCOUTM, CRYCOUTM, MULTSIGNOUTM} CLK (MREG) to {P, CARRYOUT} output CLK (MREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 1.81 1.91 2.10 2.13 2.47 2.66 ns ns
Description
Speed -3 -2 -1
Units
Clock to Outs from Input Register Clock to Output Pins TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_M TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_NM TDSPCKO_{PC, CRYOUTC} CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier CLK (AREG, BREG) to {P, CARRYOUT} output not using multiplier CLK (CREG) to {P, CARRYOUT} output 3.09 1.90 1.89 3.57 2.11 2.11 4.23 2.63 2.62 ns ns ns
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUTA, BCOUTB} TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA, PCOUTB, CRYCOUTB, MULTSIGNOUTB}_M TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA, PCOUTB, CRYCOUTB, MULTSIGNOUTB}_NM TDSPCKO_{PCOUTC, CRYCOUTC, MULTSIGNOUTC} CLK (AREG, BREG) to {ACOUT, BCOUT} CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier CLK (CREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 0.61 3.09 0.68 3.57 0.79 4.23 ns ns
2.03
2.27
2.82
ns
2.03
2.26
2.82
ns
Maximum Frequency
FMAX FMAX_PATDET FMAX_MULT_NOMREG FMAX_MULT_NOMREG_PATDET With all registers used With pattern detector Two register multiply without MREG Two register multiply without MREG with pattern detect 550 515 374 345 500 465 324 300 450 410 275 254 MHz MHz MHz MHz
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 42
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 44: Configuration Switching Characteristics Speed Grade Symbol
Power-up Timing Characteristics TPL TPOR TICCK TPROGRAM Program Latency Power-on-Reset CCLK (output) delay Program Pulse Width 3 10 50 400 250 3 10 50 400 250 3 10 50 400 250 ms, Max ms, Min/Max ns, Min ns, Min
Description
-3
-2
-1
Units
Master/Slave Serial Mode Programming Switching(1) TDCCK/TCCKD TDSCCK/TSCCKD TCCO FMCCK FMCCKTOL FMSCCK SelectMAP Mode Programming TSMDCCK/TSMCCKD TSMCSCCK/TSMCCKCS TSMCCKW/TSMWCCK TSMCKBY TSMCKCSO TSMCO TSMCKBY FSMCCK FMCCKTOL DIN Setup/Hold, slave mode DIN Setup/Hold, master mode DOUT Maximum Frequency, master mode with respect to nominal CCLK. Frequency Tolerance, master mode with respect to nominal CCLK. Slave mode external CCLK Switching(1) SelectMAP Data Setup/Hold CS_B Setup/Hold RDWR_B Setup/Hold BUSY Propagation Delay CSO_B clock to out (330 pull-up resistor required) CCLK to DATA out in readback CCLK to BUSY out in readback Maximum Frequency, master mode with respect to nominal CCLK. Frequency Tolerance, master mode with respect to nominal CCLK. 3.0 0.5 3.0 0.5 8.0 0.5 7.5 10 9.0 7.5 100 50 3.0 0.5 3.0 0.5 8.0 0.5 7.5 10 9.0 7.5 100 50 3.0 0.5 3.0 0.5 8.0 0.5 7.5 10 9.0 7.5 100 50 ns, Min ns, Min ns, Min ns, Max ns, Min ns, Max ns, Max MHz, Max % 4.0 0.0 4.0 0.0 7.5 100 50 100 4.0 0.0 4.0 0.0 7.5 100 50 100 4.0 0.0 4.0 0.0 7.5 100 50 100 ns, Min ns, Min ns, Max MHz, Max % MHz
Boundary-Scan Port Timing Specifications TTAPTCK TTCKTAP TTCKTDO TMS and TDI Setup time before TCK TMS and TDI Hold time after TCK TCK falling edge to TDO output valid 1.0 2.0 6 1.0 2.0 6 1.0 2.0 6 ns, Min ns, Min ns, Max
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 43
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 44: Configuration Switching Characteristics (Continued) Speed Grade Symbol
FTCK FTCKB
Description
Maximum configuration TCK clock frequency Maximum boundary-scan TCK clock frequency
-3
66 66
-2
66 66
-1
66 66
Units
MHz, Max MHz, Max
BPI Master Flash Mode Programming Switching
TBPICCO(4) TBPIDCC/TBPICCD TINITADDR ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs valid after CCLK rising edge Setup/Hold on D[15:0] data input pins Minimum period of initial ADDR[25:0] address cycles 10 3.0 0.5 3.0 10 3.0 0.5 3.0 10 3.0 0.5 3.0 ns ns CCLK cycles
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPIDCCD TSPICCM TSPICCFC TFSINIT/TFSINITH DIN Setup/Hold before/after the rising CCLK edge MOSI clock to out FCS_B clock to out FS[2:0] to INIT_B rising edge Setup and Hold 4.0 0.0 10 10 2 4.0 0.0 10 10 2 4.0 0.0 10 10 2 ns ns ns s
CCLK Output (Master Modes)
TMCCKL TMCCKH Master CCLK clock minimum Low time Master CCLK clock minimum High time 3.0 3.0 3.0 3.0 3.0 3.0 ns, Min ns, Min
CCLK Input (Slave Modes)
TSCCKL TSCCKH Slave CCLK clock minimum Low time Slave CCLK clock minimum High time 2.0 2.0 2.0 2.0 2.0 2.0 ns, Min ns, Min
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK FDCK TDMCCK_DADDR/TDMCKC_DADDR TDMCCK_DI/TDMCKC_DI TDMCCK_DEN/TDMCKC_DEN TDMCCK_DWE/TDMCKC_DWE TDMCKO_DO TDMCKO_DRDY/TDMCKCO_DRDY Maximum frequency for DCLK DADDR Setup/Hold DI Setup/Hold DEN Setup/Hold time DWE Setup/Hold time CLK to out of DO(3) CLK to out of DRDY 500 1.2 0.0 1.2 0.0 1.2 0.0 1.2 0.0 1.0 1.0 450 1.35 0.0 1.35 0.0 1.35 0.0 1.35 0.0 1.12 1.12 400 1.56 0.0 1.56 0.0 1.56 0.0 1.56 0.0 1.3 1.3 MHz ns ns ns ns ns ns
Notes: 1. Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages. 2. To support longer delays in configuration, use the design solutions described in UG190: VIRTEX-5 User Guide. 3. DO will hold until next DRP operation. 4. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 44
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 45: Global Clock Switching Characteristics (Including BUFGCTRL) Speed Grade Symbol
TBCCCK_CE/TBCCKC_CE(1) TBCCCK_S/TBCCKC_S(1) TBCCKO_O TBGCKO_O Maximum Frequency FMAX FMAX Global clock tree (BUFG) for LX30, LX30T, LX50, LX50T, LX85, LX85T, LX110, LX110T, SX35T, and SX50T devices Global clock tree (BUFG) for LX220, LX220T, LX330, LX330T, and SX95T devices 710 N/A 650 500 600 450 MHz MHz CE pins Setup/Hold S pins Setup/Hold BUFGCTRL delay from I0/I1 to O BUFG delay from I0 to O
Description
-3
0.27 0.00 0.27 0.00 0.19 0.19
-2
0.27 0.00 0.27 0.00 0.22 0.22
-1
0.31 0.00 0.31 0.00 0.25 0.25
Units
ns ns ns ns
Notes: 1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks.
Table 46: Input/Output Clock Switching Characteristics (BUFIO) Speed Grade Symbol
TBUFIOCKO_O Maximum Frequency FMAX I/O clock tree (BUFIO) 710 710 644 MHz
Description
Clock to out delay from I to O
-3
1.08
-2
1.16
-1
1.29
Units
ns
Table 47: Regional Clock Switching Characteristics (BUFR) Speed Grade Symbol
TBRCKO_O TBRCKO_O_BYP TBRDO_CLRO Maximum Frequency FMAX Regional clock tree (BUFR) 300 250 250 MHz
Description
Clock to out delay from I to O Clock to out delay from I to O with Divide Bypass attribute set Propagation delay from CLR to O
-3
0.56 0.23 0.61
-2
0.59 0.24 0.70
-1
0.67 0.26 0.82
Units
ns ns ns
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 45
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
PLL Specification
Table 48: PLL Specification Speed Grade Symbol
FINMAX FINMIN FINJITTER FINDUTY
Description
Maximum Input Clock Frequency Minimum Input Clock Frequency Maximum Input Clock Period Jitter Allowable Input Duty Cycle: 19--49 MHz Allowable Input Duty Cycle: 50--199 MHz Allowable Input Duty Cycle: 200--399 MHz Allowable Input Duty Cycle: 400--499 MHz Allowable Input Duty Cycle: >500 MHz
-3
710 19
-2
710 19
-1
645 19
Units
MHz MHz
<20% of clock input period or 1 ns Max 25/75 30/70 35/65 40/60 45/55 400 1440 1 4 120 400 1200 1 4 120 Note 1 150 100 710 200 100 650 200 100 600 ps s MHz 400 1000 1 4 120 % % % % % MHz MHz MHz MHz ps
FVCOMIN FVCOMAX FBANDWIDTH
Minimum PLL VCO Frequency Maximum PLL VCO Frequency Low PLL Bandwidth at Typical High PLL Bandwidth at Typical
TSTAPHAOFFSET TOUTJITTER TOUTDUTY TLOCKMAX FOUTMAX
Static Phase Offset of the PLL Outputs PLL Output Jitter(1) PLL Output Clock Duty Cycle Precision(2) PLL Maximum Lock Time(4)
PLL Maximum Output Frequency for LX30, LX30T, LX50, LX50T, LX85, LX85T, LX110, LX110T, SX35T, and SX50T devices PLL Maximum Output Frequency for LX220, LX220T, LX330, LX330T, and SX95T devices
N/A 3.125
500 3.125
450 3.125
MHz MHz
FOUTMIN TEXTFDVAR RSTMINPULSE FPFDMAX FPFDMIN TFBDELAY
PLL Minimum Output Frequency(3) External Clock Feedback Variation Minimum Reset Pulse Width Maximum Frequency at the Phase Frequency Detector Minimum Frequency at the Phase Frequency Detector Maximum Delay in the Feedback Path
<20% of clock input period or 1 ns Max 5 550 19 5 500 19 5 450 19 ns MHz MHz
3 ns Max or one CLKIN cycle
Notes: 1. Values for this parameter are available in the Architecture Wizard. 2. Includes global clock buffer. 3. Calculated as FVCO/128 assuming output duty cycle is 50%. 4. The LOCK signal must be sampled after TLOCKMAX. The LOCK signal is invalid after configuration or reset until the TLOCKMAX time has expired.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 46
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
DCM Switching Characteristics
Table 49: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode Speed Grade Symbol
Outputs Clocks (Low Frequency Mode) F1XLFMSMIN F1XLFMSMAX F2XLFMSMIN F2XLFMSMAX FDVLFMSMIN FDVLFMSMAX FFXLFMSMIN FFXLFMSMAX Input Clocks (Low Frequency Mode) FDLLLFMSMIN FDLLLFMSMAX FCLKINLFFXMSMIN FCLKINLFFXMSMAX FPSCLKLFMSMIN FPSCLKLFMSMAX Outputs Clocks (High Frequency Mode) F1XHFMSMIN F1XHFMSMAX F2XHFMSMIN F2XHFMSMAX FDVHFMSMIN FDVHFMSMAX FFXHFMSMIN FFXHFMSMAX Input Clocks (High Frequency Mode) FDLLHFMSMIN FDLLHFMSMAX FCLKINHFFXMSMIN FCLKINHFFXMSMAX FPSCLKHFMSMIN FPSCLKHFMSMAX PSCLK CLKIN (using DFS outputs only)(2, 3, 4) CLKIN (using DLL outputs)(1, 3, 4) 120.00 550.00 25.00 400.00 1.00 550.00 120.00 500.00 25.00 375.00 1.00 500.00 120.00 450.00 25.00 350.00 1.00 450.00 MHz MHz MHz MHz KHz MHz CLKFX, CLKFX180 CLKDV CLK2X, CLK2X180 CLK0, CLK90, CLK180, CLK270 120.00 550.00 240.00 550.00 7.5 366.67 140.00 400.00 120.00 500.00 240.00 500.00 7.5 333.34 140.00 375.00 120.00 450.00 240.00 450.00 7.5 300.00 140.00 350.00 MHz MHz MHz MHz MHz MHz MHz MHz PSCLK CLKIN (using DFS outputs only)(2, 3, 4) CLKIN (using DLL outputs)(1, 3, 4) 32.00 150.00 1.00 180.00 1.00 550.00 32.00 135.00 1.00 160.00 1.00 500.00 32.00 120.00 1.00 140.00 1.00 450.00 MHz MHz MHz MHz KHz MHz CLKFX, CLKFX180 CLKDV CLK2X, CLK2X180 CLK0, CLK90, CLK180, CLK270 32.00 150.00 64.00 300.00 2.0 100.00 32.00 180.00 32.00 135.00 64.00 270.00 2.0 90.00 32.00 160.00 32.00 120.00 64.00 240.00 2.0 80.00 32.00 140.00 MHz MHz MHz MHz MHz MHz MHz MHz
Description
-3
-2
-1
Units
Notes: 1. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input frequency. 4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45).
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 47
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 50: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode Speed Grade Symbol
Outputs Clocks (Low Frequency Mode) F1XMRMIN F1XMRMAX F2XMRMIN F2XMRMAX FDLLMRMIN FDLLMRMAX FFXMRMIN FFXMRMAX Input Clocks (Low Frequency Mode) FCLKINDLLMRMIN FCLKINDLLMRMAX FCLKINFXMRMIN FCLKINFXMRMAX FPSCLKMRMIN FPSCLKMRMAX PSCLK CLKIN (using DFS outputs only)(2, 3, 4) CLKIN (using DLL outputs)(1, 3, 4) CLKFX, CLKFX180 CLKDV CLK2X, CLK2X180 CLK0, CLK90, CLK180, CLK270
Description
-3
-2
-1
Units
19.00 32.00 38.00 64.00 1.19 21.34 19.00 40.00
19.00 32.00 38.00 64.00 1.19 21.34 19.00 40.00
19.00 32.00 38.00 64.00 1.19 21.34 19.00 40.00
MHz MHz MHz MHz MHz MHz MHz MHz
19.00 32.00 1.00 40.00 1.00 300.00
19.00 32.00 1.00 40.00 1.00 270.00
19.00 32.00 1.00 40.00 1.00 240.00
MHz MHz MHz MHz KHz MHz
Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input frequency. 4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45).
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 48
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 51: Input Clock Tolerances Symbol
Duty Cycle Input Tolerance (in %) TDUTYCYCRANGE_1 TDUTYCYCRANGE_1_50 TDUTYCYCRANGE_50_100 TDUTYCYCRANGE_100_200 TDUTYCYCRANGE_200_400 TDUTYCYCRANGE_400 PSCLK and CLKIN PSCLK only < 1 MHz 1 - 50 MHz 50 - 100 MHz 100 - 200 MHz 200 - 400 MHz(4) > 400 MHz Speed Grade Input Clock Cycle-Cycle Jitter (Low Frequency Mode) TCYCLFDLL TCYCLFFX CLKIN (using DLL outputs)(1) CLKIN (using DFS outputs)(2) -3 300.00 300.00 -2 300.00 300.00 -1 345.00 345.00 Units ps ps 25 - 75 25 - 75 30 - 70 40 - 60 45 - 55 45 - 55 % % % % % %
Description
Frequency Range
Value
Units
Input Clock Cycle-Cycle Jitter (High Frequency Mode) TCYCHFDLL TCYCHFFX Input Clock Period Jitter (Low Frequency Mode) TPERLFDLL TPERLFFX CLKIN (using DLL outputs)(1) CLKIN (using DFS outputs)(2) 1.00 1.00 1.00 1.00 1.15 1.15 ns ns CLKIN (using DLL outputs)(1) CLKIN (using DFS outputs)(2) 150.00 150.00 150.00 150.00 173.00 173.00 ps ps
Input Clock Period Jitter (High Frequency Mode) TPERHFDLL TPERHFFX Feedback Clock Path Delay Variation TCLKFB_DELAY_VAR CLKFB off-chip feedback 1.00 1.00 1.15 ns CLKIN (using DLL outputs)(1) CLKIN (using DFS outputs)(2) 1.00 1.00 1.00 1.00 1.15 1.15 ns ns
Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. If both DLL and DFS outputs are used, follow the more restrictive specifications. 4. This duty cycle specification does not apply to the GTP_DUAL to DCM connection. The GTP transceivers drive the DCMs at the following frequencies: 320 MHz for -1 speed grade devices, 375 MHz for -2 speed grade devices, or 375 MHz for -3 speed grade devices.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 49
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Output Clock Jitter
Table 52: Output Clock Jitter Speed Grade Symbol
Clock Synthesis Period Jitter TPERJITT_0 TPERJITT_90 TPERJITT_180 TPERJITT_270 TPERJITT_2X TPERJITT_DV1 TPERJITT_DV2 TPERJITT_FX CLK0 CLK90 CLK180 CLK270 CLK2X, CLK2X180 CLKDV (integer division) CLKDV (non-integer division) CLKFX, CLKFX180 120 120 120 120 200 150 300 Note 1 120 120 120 120 200 150 300 Note 1 120 120 120 120 230 180 345 Note 1 ps ps ps ps ps ps ps ps
Description
Constraints
-3
-2
-1
Units
Notes: 1. Values for this parameter are available in the Architecture Wizard.
Output Clock Phase Alignment
Table 53: Output Clock Phase Alignment Speed Grade Symbol
Phase Offset Between CLKIN and CLKFB TIN_FB_OFFSET CLKIN/CLKFB 50 50 60 ps
Description
Constraints -3 -2 -1
Units
Phase Offset Between Any DCM Outputs(4) TOUT_OFFSET_1X TOUT_OFFSET_2X TOUT_OFFSET_FX Duty Cycle Precision TDUTY_CYC_DLL(3) TDUTY_CYC_FX DLL outputs(1) DFS outputs(2) 150 150 150 150 180 180 ps ps CLK0, CLK90, CLK180, CLK270 CLK2X, CLK2X180, CLKDV CLKFX, CLKFX180 140 150 160 140 150 160 160 200 220 ps ps ps
Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION = TRUE. 4. All phase offsets are in respect to group CLK1X.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 50
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 54: Miscellaneous Timing Parameters Speed Grade Symbol
Time Required to Achieve LOCK TDLL_240 TDLL_120_240 TDLL_60_120 TDLL_50_60 TDLL_40_50 TDLL_30_40 TDLL_24_30 TDLL_30 TFX_MIN TFX_MAX TDLL_FINE_SHIFT Fine Phase Shifting TRANGE_MS TRANGE_MR Delay Lines TTAP_MS_MIN TTAP_MS_MAX TTAP_MR_MIN TTAP_MR_MAX Tap delay resolution (Min) in maximum speed mode Tap delay resolution (Max) in maximum speed mode Tap delay resolution (Min) in maximum range mode Tap delay resolution (Max) in maximum range mode 7.00 30.00 10.00 40.00 7.00 30.00 10.00 40.00 7.00 30.00 10.00 40.00 ps ps ps ps Absolute shifting range in maximum speed mode Absolute shifting range in maximum range mode 7.00 10.00 7.00 10.00 7.00 10.00 ns ns Multiplication factor for DLL lock time with Fine Shift DLL output - Frequency range > 240 MHz (1) DLL output - Frequency range 120 - 240 MHz (1) DLL output - Frequency range 60 - 120 MHz (1) DLL output - Frequency range 50 - 60 MHz(1)
(1)
Description
-3
-2
-1
Units
80.00 250.00 900.00 1300.00 2000.00 3600.00 5000.00 5000.00 10.00 10.00 2.00
80.00 250.00 900.00 1300.00 2000.00 3600.00 5000.00 5000.00 10.00 10.00 2.00
80.00 250.00 900.00 1300.00 2000.00 3600.00 5000.00 5000.00 10.00 10.00 2.00
s s s s s s s s ms ms
DLL output - Frequency range 40 - 50 MHz
DLL output - Frequency range 30 - 40 MHz (1) DLL output - Frequency range 24 - 30 MHz(1) DLL output - Frequency range < 30 MHz (1) DFS outputs(2)
Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Table 55: Frequency Synthesis Attribute
CLKFX_MULTIPLY CLKFX_DIVIDE
Min
2 1
Max
33 32
Table 56: DCM Switching Characteristics Symbol
TDMCCK_PSEN/ TDMCKC_PSEN TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC TDMCKO_PSDONE
Description
PSEN Setup/Hold PSINCDEC Setup/Hold Clock to out of PSDONE
Speed Grade -3
1.20 0.00 1.20 0.00 1.00
-2
1.35 0.00 1.35 0.00 1.12
-1
1.56 0.00 1.56 0.00 1.30
Units
ns ns ns
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 51
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
VIRTEX-5 Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 57. Values are expressed in nanoseconds unless otherwise noted. Table 57: Global Clock Input to Output Delay Without DCM or PLL Symbol Description Device Speed Grade -3 -2 -1 Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL TICKOF Global Clock and OUTFF without DCM or PLL XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 5.54 5.54 5.59 5.59 5.78 5.78 5.84 5.84 N/A N/A N/A N/A 5.72 5.77 N/A 6.04 6.04 6.09 6.09 6.28 6.28 6.35 6.35 6.99 6.99 7.17 7.17 6.22 6.27 6.59 6.73 6.73 6.79 6.79 6.99 6.99 7.06 7.06 7.71 7.71 7.91 7.91 6.92 6.97 7.30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 52
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 58: Global Clock Input to Output Delay With DCM in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode. TICKOFDCM Global Clock and OUTFF with DCM XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 2.33 2.33 2.35 2.35 2.41 2.41 2.46 2.46 N/A N/A N/A N/A 2.44 2.46 N/A 2.56 2.56 2.58 2.58 2.63 2.63 2.69 2.69 2.83 2.83 3.00 3.00 2.67 2.69 2.64 2.93 2.93 2.95 2.95 3.00 3.00 3.06 3.06 3.18 3.18 3.37 3.37 3.03 3.05 3.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 53
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 59: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode. TICKOFDCM_0 Global Clock and OUTFF with DCM XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 3.45 3.45 3.47 3.47 3.60 3.60 3.65 3.65 N/A N/A N/A N/A 3.63 3.65 N/A 3.71 3.71 3.73 3.73 3.86 3.86 3.92 3.92 4.41 4.41 4.58 4.58 3.89 3.91 4.16 4.15 4.15 4.17 4.17 4.29 4.29 4.36 4.36 4.85 4.85 5.04 5.04 4.33 4.35 4.59 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 54
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 60: Global Clock Input to Output Delay With PLL in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode. TICKOFPLL Global Clock and OUTFF with PLL XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 2.03 2.03 2.05 2.05 2.10 2.10 2.16 2.16 N/A N/A N/A N/A 2.14 2.16 N/A 2.12 2.12 2.14 2.14 2.18 2.18 2.24 2.24 2.58 2.58 2.75 2.75 2.22 2.24 2.32 2.41 2.41 2.43 2.43 2.47 2.47 2.54 2.54 2.86 2.86 3.05 3.05 2.51 2.53 2.60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is included in the timing calculation.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 55
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 61: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode. TICKOFPLL_0 Global Clock and OUTFF with PLL XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 3.98 3.98 4.01 4.01 4.13 4.13 4.19 4.19 N/A N/A N/A N/A 4.16 4.19 N/A 4.33 4.33 4.35 4.35 4.47 4.47 4.53 4.53 5.03 5.03 5.20 5.20 4.51 4.53 4.77 4.82 4.82 4.84 4.84 4.96 4.96 5.03 5.03 5.53 5.53 5.71 5.71 5.00 5.02 5.27 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is included in the timing calculation.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 56
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 62: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL in System-Synchronous Mode. TICKOFDCM_PLL Global Clock and OUTFF with DCM and PLL XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 2.47 2.47 2.49 2.49 2.55 2.55 2.60 2.60 N/A N/A N/A N/A 2.58 2.60 N/A 2.70 2.70 2.72 2.72 2.77 2.77 2.83 2.83 2.97 2.97 3.14 3.14 2.81 2.83 2.78 3.06 3.06 3.08 3.08 3.13 3.13 3.19 3.19 3.31 3.31 3.49 3.49 3.16 3.18 3.13 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM and PLL output jitter are already included in the timing calculation.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 57
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 63: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL in Source-Synchronous Mode. TICKOFDCM0_PLL Global Clock and OUTFF with DCM and PLL XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 3.59 3.59 3.61 3.61 3.74 3.74 3.79 3.79 N/A N/A N/A N/A 3.77 3.79 N/A 3.85 3.85 3.87 3.87 4.00 4.00 4.06 4.06 4.55 4.55 4.72 4.72 4.03 4.05 4.30 4.27 4.27 4.29 4.29 4.42 4.42 4.48 4.48 4.98 4.98 5.17 5.17 4.45 4.48 4.72 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM and PLL output jitter are already included in the timing calculation.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 58
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
VIRTEX-5 Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 65. Values are expressed in nanoseconds unless otherwise noted. Table 64: Global Clock Setup and Hold Without DCM or PLL Symbol Description Device Speed Grade -3 -2 -1 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay) Global Clock and IFF(2) without DCM or PLL XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 1.49 -0.35 1.49 -0.35 1.48 -0.30 1.48 -0.30 1.75 -0.49 1.75 -0.49 1.74 -0.43 1.73 -0.43 N/A N/A N/A N/A 1.47 -0.16 1.62 -0.31 N/A 1.60 -0.35 1.60 -0.35 1.59 -0.30 1.59 -0.30 1.89 -0.49 1.89 -0.49 1.88 -0.43 1.88 -0.43 2.57 -0.74 2.57 -0.74 2.55 -0.56 2.57 -0.56 1.59 -0.16 1.74 -0.31 2.10 -0.44 1.77 -0.35 1.76 -0.35 1.76 -0.30 1.76 -0.30 2.09 -0.49 2.09 -0.49 2.09 -0.43 2.09 -0.43 2.86 -0.74 2.86 -0.74 2.85 -0.56 2.86 -0.56 1.76 -0.16 1.93 -0.31 2.32 -0.44 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input Flip-Flop or Latch 3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 59
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 65: Global Clock Setup and Hold With DCM in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCM/ TPHDCM No Delay Global Clock and IFF(2) with DCM in System-Synchronous Mode XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 1.53 -0.50 1.53 -0.50 1.52 -0.48 1.52 -0.48 1.58 -0.43 1.57 -0.43 1.58 -0.37 1.58 -0.37 N/A N/A N/A N/A 1.60 -0.39 1.58 -0.37 N/A 1.70 -0.50 1.70 -0.50 1.68 -0.48 1.68 -0.48 1.76 -0.43 1.76 -0.43 1.76 -0.37 1.76 -0.37 2.17 -0.27 2.17 -0.27 2.17 -0.10 2.17 -0.10 1.78 -0.39 1.76 -0.37 2.10 -0.41 1.88 -0.50 1.88 -0.50 1.86 -0.48 1.86 -0.48 1.95 -0.43 1.95 -0.43 1.95 -0.37 1.95 -0.37 2.44 -0.27 2.44 -0.27 2.44 -0.10 2.44 -0.10 1.98 -0.39 1.95 -0.37 2.35 -0.41 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CLK0, DCM, and jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 60
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 66: Global Clock Setup and Hold With DCM in Source-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM in Source-Synchronous Mode XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 0.27 0.62 0.27 0.62 0.26 0.64 0.25 0.64 0.23 0.76 0.23 0.76 0.23 0.82 0.23 0.82 N/A N/A N/A N/A 0.25 0.80 0.24 0.82 N/A 0.27 0.62 0.27 0.62 0.26 0.64 0.26 0.64 0.24 0.76 0.24 0.76 0.24 0.82 0.24 0.82 0.21 1.31 0.21 1.31 0.21 1.48 0.21 1.48 0.27 0.80 0.25 0.82 0.24 1.06 0.27 0.66 0.27 0.66 0.26 0.68 0.26 0.68 0.24 0.80 0.24 0.80 0.24 0.87 0.24 0.87 0.22 1.36 0.22 1.36 0.22 1.55 0.22 1.55 0.27 0.84 0.25 0.86 0.24 1.11 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CLK0, DCM, and jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 61
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 67: Global Clock Setup and Hold With PLL in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSPLL/ TPHPLL No Delay Global Clock and IFF(2) with PLL in System-Synchronous Mode XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 1.51 -0.81 1.51 -0.81 1.49 -0.79 1.49 -0.79 1.52 -0.74 1.52 -0.74 1.51 -0.68 1.51 -0.68 N/A N/A N/A N/A 1.56 -0.70 1.54 -0.68 N/A 1.67 -0.81 1.67 -0.81 1.65 -0.79 1.65 -0.79 1.70 -0.74 1.70 -0.74 1.69 -0.68 1.69 -0.68 1.77 -0.52 1.77 -0.52 1.75 -0.35 1.77 -0.35 1.73 -0.70 1.71 -0.68 1.83 -0.58 1.91 -0.81 1.91 -0.81 1.88 -0.79 1.88 -0.79 1.95 -0.74 1.95 -0.74 1.95 -0.68 1.95 -0.68 2.08 -0.52 2.08 -0.52 2.07 -0.35 2.08 -0.35 1.98 -0.70 1.96 -0.68 2.11 -0.58 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CLKOUT0, PLL, and jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 62
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 68: Global Clock Setup and Hold With PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSPLL0/ TPHPLL0 No Delay Global Clock and IFF(2) with PLL in Source-Synchronous Mode XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T -0.21 1.15 -0.21 1.15 -0.22 1.17 -0.22 1.17 -0.24 1.29 -0.24 1.29 -0.24 1.35 -0.24 1.35 N/A N/A N/A N/A -0.22 1.33 -0.24 1.35 N/A -0.21 1.23 -0.21 1.23 -0.22 1.25 -0.22 1.25 -0.24 1.37 -0.24 1.37 -0.24 1.43 -0.24 1.43 -0.31 1.93 -0.32 1.93 -0.31 2.10 -0.32 2.10 -0.22 1.41 -0.24 1.43 -0.26 1.67 -0.21 1.33 -0.21 1.33 -0.22 1.35 -0.22 1.35 -0.24 1.48 -0.24 1.48 -0.24 1.54 -0.24 1.54 -0.31 2.04 -0.32 2.04 -0.31 2.22 -0.32 2.22 -0.22 1.51 -0.24 1.53 -0.26 1.78 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CLKOUT0, PLL, and jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 63
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 69: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCMPLL/ TPHDCMPLL No Delay Global Clock and IFF(2) with DCM and PLL in System-Synchronous Mode XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T 1.66 -0.37 1.65 -0.37 1.63 -0.34 1.63 -0.34 1.68 -0.29 1.68 -0.29 1.67 -0.23 1.66 -0.23 N/A N/A N/A N/A 1.72 -0.26 1.70 -0.23 N/A 1.83 -0.37 1.83 -0.37 1.80 -0.34 1.80 -0.34 1.87 -0.29 1.87 -0.29 1.87 -0.23 1.86 -0.23 2.26 -0.13 2.25 -0.13 2.23 0.04 2.25 0.04 1.91 -0.26 1.88 -0.23 2.22 -0.27 2.00 -0.37 2.00 -0.37 1.98 -0.34 1.98 -0.34 2.07 -0.29 2.07 -0.29 2.07 -0.23 2.06 -0.23 2.55 -0.13 2.55 -0.13 2.53 0.04 2.54 0.04 2.10 -0.26 2.07 -0.23 2.47 -0.27 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CLK0, DCM, CLKOUT0, PLL, and jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 64
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 70: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode Speed Grade Symbol Description Device
-3 -2 -1
Units
Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM, PLL, and Global Clock Buffer. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in IOB Switching Characteristics, page 23.
TPSDCMPLL_0/ TPHDCMPLL_0
No Delay Global Clock and IFF (2) with DCM and PLL in Source-Synchronous Mode
XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T
0.39 0.75 0.39 0.75 0.37 0.78 0.37 0.78 0.34 0.90 0.33 0.90 0.32 0.96 0.32 0.96 N/A N/A N/A N/A 0.38 0.93 0.35 0.96 N/A
0.40 0.75 0.40 0.75 0.38 0.78 0.38 0.78 0.36 0.90 0.36 0.90 0.35 0.96 0.35 0.96 0.30 1.45 0.30 1.45 0.28 1.62 0.30 1.62 0.39 0.93 0.37 0.96 0.35 1.20
0.40 0.79 0.40 0.79 0.38 0.81 0.38 0.81 0.36 0.93 0.36 0.93 0.35 1.00 0.35 1.00 0.32 1.49 0.32 1.49 0.31 1.68 0.32 1.68 0.39 0.97 0.37 0.99 0.35 1.24
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CLK0, DCM, CLKOUT0, PLL, and jitter. Package skew is not included in these measurements. 2. IFF = Input Flip-Flop
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 65
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
ChipSyncTM Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for VIRTEX-5 source-synchronous transmitter and receiver data-valid windows. Table 71: Duty Cycle Distortion and Clock-Tree Skew Symbol
TDCD_CLK TCKSKEW
Description
Global Clock Tree Duty Cycle Distortion (1) Global Clock Tree Skew (2)
Device
All XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T
Speed Grade -3
0.12 0.21 0.21 0.26 0.26 0.42 0.42 0.48 0.48 N/A N/A N/A N/A 0.38 0.43 N/A 0.10 0.07 0.25
-2
0.12 0.22 0.22 0.27 0.27 0.43 0.43 0.50 0.50 1.07 1.07 1.25 1.25 0.39 0.44 0.72 0.10 0.07 0.25
-1
0.12 0.22 0.22 0.28 0.28 0.45 0.45 0.51 0.51 1.10 1.10 1.29 1.29 0.39 0.45 0.74 0.10 0.08 0.25
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TDCD_BUFIO TBUFIOSKEW TDCD_BUFR
I/O clock tree duty cycle distortion I/O clock tree skew across one clock region Regional clock tree duty cycle distortion
All All All
Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 66
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 72: Package Skew Symbol Description Device
XC5VLX30 FF676 XC5VLX30T FF665 FF324 XC5VLX50 FF676 FF1153 FF665 XC5VLX50T FF1136 FF676 XC5VLX85 FF1153 XC5VLX85T TPKGSKEW Package Skew(1) XC5VLX110 FF1136 FF676 FF1153 FF1760 FF1136 XC5VLX110T FF1738 XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T FF1136 XC5VSX95T FF1136 157 176 ps ps FF1760 FF1738 FF1760 FF1738 FF665 FF665 171 178 156 177 155 103 103 ps ps ps ps ps ps ps 174 164 142 173 190 163 ps ps ps ps ps ps 162 142 ps ps 142 93 80 142 175 93 ps ps ps ps ps ps
Package
FF324
Value
80
Units
ps
Notes: 1. These values represent the worst-case skew between any two SelectMap I/Os in the package: shortest flight time to longest flight time from Pad to Ball (7.0 ps per mm). 2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
Table 73: Sample Window Symbol
TSAMP TSAMP_BUFIO
Description
Sampling Error at Receiver Pins(1) Sampling Error at Receiver Pins using BUFIO(2)
Device
All All
Speed Grade -3
450 350
-2
500 400
-1
550 450
Units
ps ps
Notes: 1. This parameter indicates the total sampling error of VIRTEX-5 DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew. 2. This parameter indicates the total sampling error of VIRTEX-5 DDR input registers across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers' edges of operation. These measurements do not include package or clock tree skew.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 67
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Table 74: ChipSync Pin-to-Pin Setup/Hold and Clock-to-Out Symbol Description Speed Grade -3 -2 -1 Units
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO TPSCS/TPHCS Setup/Hold of I/O clock -0.56 1.59 -0.54 1.72 -0.54 1.91 ns
Pin-to-Pin Clock-to-Out Using BUFIO TICKOFCS Clock-to-Out of I/O clock 4.42 4.82 5.40 ns
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 68
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Revision History
The following table shows the revision history for this document. Date 04/14/06 05/12/06 Version 1.0 1.1 Initial Xilinx release. * * 05/24/06 08/04/06 1.2 1.3 * * * * * * * * * * * * First version posted to the Xilinx website. Minor typograpical edits. Revised design software version on page 21. Revised TIDELAYRESOLUTION in Table 38, page 35. Revised TDSPCKO in Table 43, page 40. Added register-to-register parameters to Table 26. Added VDRINT, VDRI, and CIN values to Table 3. Added HSTL_I_12 and LVCMOS12 to Table 7 and renumbered the notes. Removed pin-to-pin performance (Table 12). Updated and added values to register-register performance Table 26 (was Table 13). Added values to Table 27. Updated the speed specification version above Table 28. Added to Table 30 the I/O standards: HSTL_II_T_DCI, HSTL_II_T_DCI_18, SSTL2_II_T_DCI, and SSTL18_II_T_DCI. Revised FMAX values in Table 42, and RDWR_B Setup/Hold values in Table 44. In Table 48, changed FVCOMAX, removed TLOCKMIN, and revised TLOCKMAX values, also removed note pointing to Architecture Wizard. Removed Note 2 on Table 61. Added new sections for LXT devices and added LXT devices to the appropriate tables. The addition of the RocketIO GTP Transceiver Specifications required the tables to be renumbered. Changed maximum VIN values in Table 1 and Table 2. Updated values and added Tj = 85C to Table 4, page 3. Revised the cascade block RAM Memory, page 19 section in Table 26 to 64K with new I/O delays. Revised the setup and hold times in Table 34, page 31. Added FMAX_CASCADE to Table 42, page 38. Revised FFXLFMSMAX and FCLKINLFFXMSMAX in Table 49, page 47. Added System Monitor parameters. Added XC5VLX85T to appropriate tables. Revised Table 16 including notes. Added Table 17, and Figure 3 and Figure 4. Added Table 19, page 14: RocketIO CRC block. Revised design software version and Table 28 on page 21. Updated ILOGIC Switching Characteristics, page 31 Updated FMAX_ECC in Table 42, page 38. Changed hold times for TSMDCCK/ TSMCCKD and TBPIDCC/TBPICCD in Table 44, page 43. Revised TFBDELAY, FOUTMIN, FOUTMAX, and FINJITTER Table 48, page 46. Revised Table 49, page 47. Revision
09/06/06
2.0
* * * * * * 10/13/06 2.1 * * * * * * * * *
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 69
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Date 01/05/07
Version 2.2 * * * * * * * * * * * * * * * * * *
Revision Added IIN to Table 2. Added XC5VLX220T to appropriate tables. Added LVDCI33, LVDCI25, LVDCI18, LVDCI15 to Table 7. Update the symbols in the GTP Transceiver Table 12, Table 13, and Table 14. Add values for -1 speed grade in Table 18, page 14. Added SFI-4.1 values to Table 27, page 20. Removed -3 speed grade from available LX220 device list in Table 28, page 21. Added maximum frequency to Table 46 and Table 47, page 45. In Table 49, page 47 changed the all the CLKDV, CLKFX, and CLKFX180 Min values and the CLKIN Min values in the Input Clocks (High Frequency Mode) section. Added values to Table 52 and Table 53, page 50. Added XC5VSX35T, XC5VSX50T, and SX5VSX95T devices to appropriate tables. Revised the IRPU values in Table 3, page 2. Revised the ICCAUXQ values in Table 4, page 3. Added values to Table 5, page 4. Minor added notes and changed descriptions in Table 13, page 9 and Table 14, page 9. Revised the SFI-4.1 (SDR LVDS Interface) -1 values in Table 27, page 20. Revised gain error, bipolar gain error, and event conversion time in Table 25, page 17 Changed the design software version that matches this datasheet above Table 28 on page 21. In Switching Characteristics, the following values are revised: - LVCMOS25, Fast, 12 mA in Table 30, page 23. - Setup and Hold and TICKQ in Table 34, page 31. - TOCKQ in Table 35, page 32. - Sequential delay values in Table 37, page 34. - TCXB, TCEO, and TDICK in Table 39, page 35. - TRCKO_DO, TRCKO_POINTERS, TRCKO_ECCR, TRCKO_ECC, TRCCK_ADDR, TRDCK_DI, TRDCK_DI_ECC, TRCCK_WREN, and TRCO_FLAGS in Table 42, page 38. - TDSPDCK_CC, TDSPCCK_{RSTAA, RSTBB}, TDSPCKO_{PP, CRYOUTP}, FMAX_MULT_NOMREG and FMAX_MULT_NOMREG_PATDET in Table 43, page 40. - TBCCKO_O, and TBGCKO_O in Table 45, page 45. - TBUFIOCKO_O and FMAX in Table 46, page 45. - TBRCKO_O and TBRCKO_O_BYP in Table 47, page 45. - Parameters in Table 48, page 46 including notes. In VIRTEX-5 Pin-to-Pin Output Parameter Guidelines: - Revised values in Table 57, Table 58, and Table 59. In VIRTEX-5 Pin-to-Pin Input Parameter Guidelines: - Clarified description in Table 64, page 59. - Revised values in Table 64, Table 65, and Table 66. - Removed duplicate TBUFR_MAX_FREQ and TBUFIO_MAX_FREQ from Table 71. Revised values in Table 74, page 68.
02/02/07
3.0
* *
*
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 70
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Date 05/18/07
Version 3.1 * * * * * * * *
Revision Added typical values for n and r in Table 3. Revised and added values to Table 4. Revised standard I/O levels in Table 7. Additions and updates to Table 14, Table 16, Table 17, Table 18, Table 19, Table 20, Table 21, Table 22, and Table 23. Added Ethernet MAC Switching Characteristics, page 16. Changed the design software version that matches this datasheet above Table 28 on page 21. Added new section: I/O Standard Adjustment Measurement Methodology, page 28. In Switching Characteristics, the following values are revised: - LVTTL, Slow and Fast, 2 mA, 4 mA, and 6 mA (Table 30). - LVCMOS33, Slow and Fast, 2 mA, 4 mA, and 6 mA (Table 30). - LVCMOS25, Slow and Fast, 2 mA and 4 mA, and Fast 12 mA (Table 30). - LVCMOS18, Slow and Fast, 2 mA, 4 mA, and 6 mA (Table 30). - LVCMOS15 and LVCMOS12, Slow and Fast, 2 mA (Table 30). - TIDOCK and TIDOCKD in Table 34. - Setup/Hold for Control Lines and Data Lines in Table 36. - Add TIDELAYPAT_JIT and revised TIDELAYRESOLUTION in Table 38, page 35 and added Notes 1 and 2. - Revised TRCK page 36 and removed TCKSR Table 39, page 35. - Replaced TTWC with TMCP symbol in Table 40, page 37. - Revised TCECK in Table 41. - Revised TRCKO_FLAGS and TRDCK_DI_ECC encode only in Table 42. - Revised Hold Times of Data/Control Pins to the Input Register Clock. Setup/Hold times of {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK. Hold times of some of the CE pins. Hold times of some of the RST pins. Hold times of {A, B} input to {P, CARRYOUT} output using multiplier and {ACIN, BCIN} input to {P, CARRYOUT} output using multiplier, CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier, in Table 43. - Updated and added values to Table 44, page 43. Revised -1 speed FMAX value in Table 46, page 45. Added Note 4 to TLOCKMAX and revised FINDUTY, FINMAX,and FVCOMAX in Table 48, page 46. Added values to Table 52 and Table 53. Changed TOUT_OFFSET in Table 53. In VIRTEX-5 Pin-to-Pin Output Parameter Guidelines: - Revised values in Table 57 through Table 63. In VIRTEX-5 Pin-to-Pin Input Parameter Guidelines: - Revised values in Table 64 through Table 70. In ChipSyncTM Source-Synchronous Switching Characteristics: - Revised values in Table 71, page 66. - Added package skew values to Table 72, page 67. - Revised values in Table 74, page 68.
* * * * * *
DS202 (v3.6) November 5, 2007 Advance Product Specification
www.xilinx.com 71
R
VIRTEX-5 Data Sheet: DC and Switching Characteristics
Date 06/15/07
Version 3.2 * * * * * * * * * * * * * * * * Updated TSTG in Table 1.
Revision Corrected VOH/VOL in Table 9 and Table 10, page 7. Changed the design software version that matches this data sheet above Table 28 on page 21. Added "Production Silicon and ISE Software Status," page 22. Added TIODELAY_CLK_MAX and revised TCKSR in Table 38, page 35. In VIRTEX-5 Pin-to-Pin Output Parameter Guidelines: Revised values in Table 58 through Table 63. In VIRTEX-5 Pin-to-Pin Input Parameter Guidelines: Revised values in Table 65 through Table 70. Corrected units to ns in Table 71, page 66. Added conditions to DVPPIN in Table 16, page 12. Changed the FGTXMAX symbol name to FGTPMAX. Updated GTP maximum line rates to 3.75 Gb/s in Table 18, page 14. Updated maximum frequencies in Table 21, page 15. Added 3.75 Gb/s condition and changed maximum value of FGTX in Table 22, page 15. Added 3.75 Gb/s sinusoidal jitter specification and changed maximum value of FGRX in Table 23, page 16. Changed analog input common mode ranges in Table 25, page 17. Changed TPKGSKEW values in Table 72, page 67. Added maximum value of IREF to Table 3, page 2. Revised Table 28 and changed the design software version in Table 29 for production devices. In Table 38, page 35, added High Performance Mode to Note 2. In Table 44, page 43, revised description of TSMDCCK/TSMCCKD. Added Note 4 to TDUTYCYCRANGE_200_400 frequency range in Table 51, page 49. In VIRTEX-5 Pin-to-Pin Input Parameter Guidelines: Revised note 1 in Table 64 through Table 69. Added IBATT value and Note 2 to Table 3. Added DRP Clock Frequency and Note 4 to Table 25. Revised the typical and maximum values and units for gain error and bipolar gain error. Removed unsupported XC5VSX95T -3 speed grade from Table 28 and Table 29. Removed unsupported I/O standards (LVDS_33, LVDSEXT_33, and ULVDS_25) from Table 25. Also updated LVDSEXT, 2.5V in Table 33. Added values to Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK in Table 44. In VIRTEX-5 Pin-to-Pin Input Parameter Guidelines: Revised note 1 in Table 64 through Table 70. Removed note 1 from Table 26, page 19. FMAX of clock is not an applicable limitation. Revised DDR2 memory interface performance in Table 27, page 20. Revised Table 29 to add ISE 9.2i SP3 where applicable. Removed XC5VSX95T -3 speed grade support from applicable tables. Removed unsupported I/O standard (LVPECL_33) from Table 32 and added LVPECL_25. Added TSMCO and TSMCKBY to Table 44, page 43. Revised note 3 in Table 49, page 47 and Table 50, page 48. Clarified notes in Table 60 to Table 63, and Table 67 to Table 70. Revised note 1 in Table 72.
www.xilinx.com 72
06/26/07
3.3
07/26/07
3.4
* * * * * *
09/27/07
3.5
* * * * * *
11/05/07
3.6
* * * * * * * * *
DS202 (v3.6) November 5, 2007 Advance Product Specification

▲Up To Search▲

Price & Availability of VIRTEX-5

	To Download VIRTEX-5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .