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STOTG04E
USB-OTG Full-speed Transceiver
Feature summary

Meets USB specification Rev. 2.0 And on-thego supplement to the USB 2.0 specification Analog car kit-compatible Four operating modes: USB, I2C, UART and Audio Configurable using I2C serial interface Capable of 12Mbit/s full-speed and 1.5Mbit/s low-speed modes of operation Standard digital interface compliant with the OTG transceiver specification Supports the session request protocol (SRP) and host negotiation protocol (HNP) 35mA typical VBUS charge pump output current for 3.3V supply voltage Ability to control external charge pump for higher VBUS currents Integrated pull-up/-down resistors 6kV ESD Protection on all USB pins (contact discharge) +1.6V to +3.6V Digital power supply and +2.7V to +5.5V analog supply voltage range Power-down mode with very low power consumption for battery powered devices
QFN24 (4mmx4mm)

Description
The STOTG04 is a USB On-The-Go full-speed transceiver. It provides complete physical layer (PHY) solution for any USB-OTG device. It contains VBUS charge pump and comparators, ID line detector and interrupt generator, and the USB differential driver and receivers. The STOTG04 transceiver is suitable for mobile and battery powered devices because of its low power consumption and power-down operating mode. The transceiver is capable of operation in several different modes. It can operate in basic USB-OTG mode, as an I2C and UART transceiver, or in audio mode. Behavior of the transceiver is fully configurable through the two-wire I2C serial bus. The transceiver supports session request protocol and host negotiation protocol. The applications are mobile phones, PDAs, MP3 players, printers and digital cameras.
Applications

Mobile phones PDAs MP3 players Digital cameras Printers
Order code
Part number STOTG04EQTR October 2006 Package QFN24 (4mm x 4mm) Rev. 3 Packaging 4000 parts per reel 1/26
www.st.com
26
Contents
STOTG04E
Contents
1 2 3 4 5 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Charge pump characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 6.2 6.3 6.4 6.5 6.6 6.7 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VBUS Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ID Line detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Driver and receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7.1 6.7.2 6.7.3 6.7.4 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 USB Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 UART and I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Audio mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.8 6.9 6.10 6.11 6.12
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I2C Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 External charge pump switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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STOTG04E
Pin configuration
1
Figure 1.
Pin configuration
Pin connections (Bottom View )
Table 1.
PlN N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Pin description
SYMBOL ADR_PSW SDA SCL RESET/ INT/ SPEED VTRM SUSPEND OE_TP_INT/ VM VP RCV ExpPad SE0_VM DAT_VP DD+ GND ID VBUS I/O I/O I/O I I O I NAME AND FUNCTION Least significant bit of the I address of the transceiver input latched on reset; PSW output enabling or disabling an external charge pump I2C serial data (1)
2C
I2C clock Active low logic reset Active low interrupt signal (open-drain) Mode of the transceiver (0 = low-speed, 1 = full-speed) (2) Internal voltage regulator output; an external decoupling capacitor should be Power connected (3) I Power down input (0 = active mode, 1 = power down) (See Table 8) I/O O O O I/O I/O I/O I/O Output enable of the differential driver in the USB mode, I2C data enable in the I2C mode or interrupt output D- single-ended receiver output D+ single-ended receiver output Differential receiver output Not Connected Single-ended zero input/output in the DAT_SE0 transmit mode, negative data input/output in the single-ended transmit mode or TXD in the UART mode Data input/output in the DAT_SE0 transmit mode, positive data input/output in the single-ended transmit mode or RXD in the UART mode Negative data line in the USB mode, I2C clock output in the I2C mode or serial data output in the UART mode
Positive data line in the USB mode, I2C serial data in the I2C mode or serial data input in the UART mode Power Common analog and digital ground I/O ID pin of the USB connector used for protocol identification VBUS line of the USB interface - it needs an external capacitor of 4.7F I/O 3/26
Pin configuration
STOTG04E
I/O Power I/O I/O Power Power NAME AND FUNCTION Analog power supply voltage (+2.7V to +5.5V) External capacitor pin for the charge pump External capacitor pin for the charge pump Ground for the charge pump Logic power supply (+1.6V to 3.6V)
PlN N 20 21 22 23 24
SYMBOL VBAT CAP1 CAP2 CGND VIF
(1) Input and open-drain output (2) Input with internal pull-up resistor (3) Internal regulator can be bypassed by connecting VBAT to this pin when the VBAT is in range of 2.7V to 3.6V
Figure 2.
Functional diagram
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STOTG04E
Maximum ratings
2
Table 2.
Symbol VIF VBAT VDCDIG TSTG VESD
Maximum ratings
Absolute maximum ratings
Parameter Logic Supply Voltage Analog Supply Voltage DC Input Voltage on any logic interface pin Storage Temperature Range Electrostatic discharge voltage on USB pins Human Body Model Contact Discharge (*) Value -0.5 to + 4.5 -0.5 to + 6.5 -0.5 to + 4.5 -65 to + 150 8 6 Unit V V V C kV
(*) In accordance to IEC61000-4-2, level 3. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional Operation under these conditions is not implied.
Table 3.
Symbol RthJA
Thermal data
Parameter Thermal Resistance Junction-Ambient Value 59 Unit C/W
Table 4.
Symbol VIF VBAT TA CEXT CT CTRM RS
Recommended operating condition
Parameter Logic Supply Voltage Analog Supply Voltage Operating Temperature Range Charge pump external capacitor Charge pump tank capacitor Voltage regulator external capacitor Data lines impedance matching resistor Min. 1.6 2.7 -40 100 1 220 4.7 1 20 Typ. 1.8 3.3 Max. 3.6 5.5 +85 470 6.5 Unit V V C nF F F
Table 5.
Symbol
ESD Performance
Parameter IEC-61000-4-2 (D+, D-, VBUS, ID) Air discharge (10 pulses) Contact discharge (10 pulses) Air discharge (10 pulses) Contact discharge (10 pulses) Value 8 6 2 2 Unit
ESD IEC-61000-4-2 (other pins)
kV
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Electrical characteristics
STOTG04E
3
Table 6.
Electrical characteristics
Electrical characteristics Characteristics measured over recommended operating conditions unless otherwise is noted. All typical values are referred to TA = 25C, VIF = 1.8V, VBAT = 3.3V, RS = 20, CEXT = 220nF, CT = 4.7F and CTRM = 1F
Parameter Digital Part Supply Current Test Conditions Active mode (1,2) Power down mode Transceiver current while transmitting and receiving (1, 2) Charge pump current, ILOAD = 8mA Power down mode (4) Min. Typ. 0.6 4.5 17 Max. 1.6 1 7 25 1 Unit mA A mA A V V 0.15 0.40 0.7VIF 0.3VIF -1 -5 ILOAD = 8mA No Load ILOAD = 8mA, CT = 4.7F 0.5 40 Low to high transition High to low transition Low to high transition High to low transition 20 4.40 4.40 0.8 0.8 281 656 640 1260 1 5 V V V V A A
Symbol IIF
IBAT
Operating Supply Current
LOGIC INPUTS AND OUTPUTS VOH VOL VIH VIL ILKG IOZ VBUS VBUS VBUS output voltage 4.4 4.9 3 30 0.8 76 35 5.25 200 60 1.5 100 V mV mV MHz k mA V 2.0 2.0 V VBUS_LKG VBUS leakage voltage VBUS_RIP VBUS output ripple fCP RVBUS IVBUS VBUS_VLD Charge-pump switching frequency (2) VBUS input impedance Maximum VBUS source current CEXT = 220 nF, VBUS > 4.4V HIGH level output voltage LOW level output voltage HIGH level input voltage LOW level input voltage Input leakage current Off-state output current IOH = -100A IOH = -2mA IOL = 100A IOL = 2mA VIF-0.15 VIF-0.40
VBUS valid comparator threshold Session valid comparator VSES_VLD threshold for both A and B devices RVBUS_PU VBUS charge pull-up resistance V discharge pull-down RVBUS_PD BUS resistance ID VID_BIAS RID_PU RID_GND ID pin bias voltage ID pin pull-up resistance
RCP_ID = 140k, VBAT 5V
1.3 70 800
1.9 105
3.0 130 10
V k k
ID line short resistance to detect id_gnd state
RID_FLOAT ID line short resistance to detect id_float state
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STOTG04E
Symbol ZDRV VOH_DRV VOL_DRV VCRS Parameter Test Conditions Excluding external RS RLH = 14.25k, VTRM = 3.3V RLH = 14.25k, VTRM = 2.7V RLL = 1.425k CLOAD = 50 to 600pF Min.
Electrical characteristics
Typ.
Max.
Unit V V V V
DIFFERENTIAL DRIVER Output Impedance HIGH level output voltage LOW level output voltage Driver crossover voltage Differential receiver input sensitivity (VD+ - VD-) SE receivers switching threshold Input resistance 8 2.8 2.6 0 1.3 1.67 16 24 3.6 3.0 0.3 2.0
DIFFERENTIAL AND SINGLE-ENDED RECEIVERS VDI VSE-TH RIN CIN RPU_D+ RPU_DRPD VDT_LKG VCM = 0.8 to 2.5V Low to high transition High to low transition PU/PD resistor deactivated -200 0.8 0.8 1.5 900 1425 900 14.25 1.6 1.1 10 1300 2200 1300 17.0 200 0.4 200 2.0 2.0 30 1575 3090 1575 24.8 342 0.6 mV V M pF k mV V
Input capacitance Data line pull-up resistance on Bus Idle pin D+ Receiving mode Data line pull-up resistance on pin DData line pull-down resistance RPU_EXT = 300k Data line leakage voltage
CAR KIT INTERRUPT DETECTOR VCR_INT_TH Car kit Interrupt threshold I
2C
AND UART MODES - D+ AND D- PINS VOH VOL VIH VIL HIGH level output voltage (3) LOW level output voltage HIGH level input voltage LOW level input voltage SDA line internal pull-up resist. VBAT = 3.3 to 5V, no load; 2V7en=0 VBAT = 2.8 to 5V, no load; 2V7en=1 VBAT = 3.6V, VTRM > 3V; 2V7en=0 VBAT = 3.0V, VTRM >2.6V; 2V7en=1 1425 3.0 2.6 2200 3.3 2.75 IOH= -2mA IOL = 2mA 2.4 0 2.0 0.8 3090 3.6 2.9 20 10 3.6 0.4 V V V V V V mA mA
RDP_I2C
VOLTAGE REGULATOR VTRM ITRM Internal power supply voltage Voltage regulator output current
(1) Transmitting and receiving at 12Mbit/s, loads of 50pF on D+ and D- pins, no capacitive loads on VP and VM pins (2) Not tested in production; characterization only (3) Except D+ pin in the I2C mode where this pin is open-drain with internal pull-up resistor (4) See paragraph 6.7.1
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Electrical characteristics
STOTG04E
Table 7.
Switching characteristics Over recommended operating conditions unless otherwise is noted. All the typical values are referred to TA = 25C, VIF = 1.8V, VBAT = 3.3V, RS = 20, CEXT = 220nF, CT = 4.7F, and CTRM = 1F
Parameter Test Conditions ILOAD = 8mA, CT = 10F Full-speed mode, CLOAD = 50pF Low-speed mode, CLOAD = 600pF Full-speed mode, CLOAD = 50pF Low-speed mode, CLOAD = 600pF Full-speed mode, CLOAD = 50pF Low-speed mode, CLOAD = 600pF Full-speed mode, CLOAD = 50pF Low-speed mode, CLOAD = 600pF Full-speed mode, CLOAD = 50pF Low-speed mode, CLOAD = 600pF Full-speed mode, CLOAD = 50pF Low-speed mode, CLOAD = 600pF Full-speed mode Low-speed mode 90 80 4 75 4 75 Min. Typ. 1 8.5 110 8.5 110 Max. 100 20 300 20 300 38 280 55 300 38 280 55 300 111.11 125 Unit ms
Symbol
TVBUS_RISE VBUS rise time DIFFERENTIAL DRIVER tR tF Data signal rise time Data signal rise time Propagation delay of the driver, rising edge; DAT_SE0 mode Propagation delay of the driver, rising edge; VP_VM mode Propagation delay of the driver, falling edge; DAT_SE0 mode Propagation delay of the driver, rising edge; VP_VM mode Rise and fall time matching (tR/ tF) excluding the first transition from the idle state
ns ns ns ns ns ns
tP_DRV_R
tP_DRV_F
tRFM
%
SINGLE-ENDED RECEIVERS tP_SE_R Propagation delay of the SE receiver, rising edge Propagation delay of the SE receiver, falling edge Full-speed mode, input slope 15ns Low-speed mode, input slope 150ns Full-speed mode, input slope 15ns Low-speed mode, input slope 150ns Full-speed mode, input slope 15ns Low-speed mode, input slope 150ns Full-speed mode, input slope 15ns Low-speed mode, input slope 150ns 50 0 0 5 5 18 18 18 18 ns ns
tP_SE_F
DIFFERENTIAL RECEIVER tP_DIF_R Propagation delay of the SE receiver, rising edge Propagation delay of the SE receiver, falling edge 24 24 24 24 ns ns
tP_DIF_F
DIGITAL INTERFACE tSET_OE tTA_OI tTA_IO I2C BUS (3) fSCL tLOW tHIGH tIICR SCL clock frequency Low period of the SCL clock High period of the SCL clock Rise time of both SDA and SCL signals 4.7 4.0 1000 100 kHz s s ns Output enable setup time Output to input bus turnaround time (1, 2) Output to input bus turnaround time (1, 2) ns ns ns
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STOTG04E
Symbol tIICF tSU_STA tHD_STA tSU_DAT tHD_DAT tSU_STO tBUF Parameter Fall time of both SDA and SCL signals Setup time for a repeated START condition Hold time for the START and repeated START conditions Data setup time Data hold time Setup time for the STOP condition Bus free time between a STOP and START condition Test Conditions Min.
Electrical characteristics
Typ.
Max. 300
Unit ns s s ns s s s
4.7 4.0 250 0 4.0 4.7
NOTE 1: Parameter applies to the OE_TP_INT/, DAT_VP, and SE0_VM signals NOTE 2: Not tested in production; characterization only NOTE 3: Requirements defined by the I2C-Bus Specification, version 2.1
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Charge pump characteristics
STOTG04E
4
Charge pump characteristics
Output characteristics Figure 4. Output ripple
Figure 3.
10/26
STOTG04E
Timing diagrams
5
Figure 5.
Timing diagrams
Rise and fall times
Figure 6.
Differential driver propagation delay
Figure 7.
Differential receiver propagation delay
11/26
Timing diagrams
STOTG04E
Figure 8.
Output enable setup time
V IH OE_TP_INT/ V IL V IH DAT_VP SE0_VM V IL
t SET_OE
USB Idle State
Data to Transmit
Figure 9.
Bus turnaround time
VIH OE_TP_INT/
tTA_OI
tTA_IO VIL VIH DAT_VP SE0_VM VIL
Figure 10. I2C BUS timing
output
input
output
tLOW
tIIC_F
tHIGH
tIIC_R
tHD_STA
tSU_STO
SCL
S Sr P S
SDA
tIIC_F tHD_STA tSU_DAT tHD_DAT tSU_STA tIIC_R tBUF
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STOTG04E
Figure 11. Block diagram
VBAT
Timing diagrams
SCL SDA
I2 C In te r fa c e
ADR_PSW
CAP1
CAP2 VBUS
O s c illa to r
C h a rg e Pum p
VBAT
SPEED SUSPEND Bandgap R e fe re n c e
VTRM
O E _ T P _ IN T /
DAT_VP SE0_VM R e g is te r S e t and C o n tr o l L o g ic
D+ D-
RCV
VP
VBAT
VM
VBAT
V o lt a g e R e g u la to r
VTRM
ID IN T / RESET/
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Block description
STOTG04E
6
Block description
The STOTG04 integrates a charge pump and comparators for the VBUS, ID line detector and interrupt switch, differential data driver, differential and single-ended receivers, low dropout voltage regulator and control logic. The STOTG04 provides a complete solution for connection of a digital USB OTG controller to the physical Universal Serial Bus.
6.1
Charge pump
The VBUS line voltage is provided using the internal charge pump. It is capable of sourcing up to 35mA load current. The charge pump can be powered by voltage from 2.7V to 5.5V. It needs two capacitors for its operation: an external capacitor of 220nF connected between the CAP1 and CAP2 pins and a 4.7F decoupling tank capacitor on the VBUS. If an application needs current that is higher than 35mA, an external charge pump or a switch controlled by the ADR_PSW pin may be used.
6.2
VBUS Comparators
These comparators monitor the VBUS voltage. They provide current status information for the VBUS line. VBUS valid status means that the voltage is above VBUS_VLD. Session valid status means that the VBUS voltage is above VSES_VLD level.
6.3
Voltage regulator
An internal low-dropout voltage regulator provides power for the bus drivers and receivers. The regulator needs an external capacitor of 1F on the VTRM pin for proper operation. The regulator can provide 3.3V or 2.75V output voltages according to 2V7_en bit in Control Register 3. The regulator can be bypassed by tying the VTRM pin to the VBAT power supply voltage when the analog supply voltage is in the range of 3.0V (or 2.7V) to 3.6V.
6.4
ID Line detector
This block senses ID line status. It is capable of detecting three different line states: * pin floating; * pin tied to ground; * pin grounded via a 140k resistor. The ID detector can also generate an interrupt by shorting the pin to ground.
6.5
Driver and receivers
The driver can operate in several different modes. It can act as a simple low-speed and full-speed differential USB driver, as two independent single-ended drivers in the UART mode, or as an open-drain driver in the I2C mode. This block contains one differential receiver for the USB operation mode and two single-ended receivers for USB signaling as well as UART and I2C receivers.
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STOTG04E
Block description
6.6
Control logic
This block controls the behavior of whole chip. It communicates with the external environment via the I2C serial bus. The control logic block consists of I2C slave interface, configuration and status registers, and some glue logic.
6.7
Modes of operation
The STOTG04 can operate in two different power modes and in three operating modes. They can be controlled by logic signals and control registers.
6.7.1
Power modes
When there is no need for the USB function, the STOTG04 reduces power consumption by implementing the Power-down mode. The power modes can be controlled by the Suspend Bit of Control Register 1 or/ and the SUSPEND pin (see Table 8). Table 8. Power modes
SUSPEND BIT 0 X 1 SUSPEND PIN X 0 1 Power Mode normal operation power-down
Although in power down mode all analog blocks should be switched off, some of them could be turned on by bits in the control registers having higher priority than suspend bit. In order to obtain minimum power consumption in power down mode the device must be configured has shown in Table 9. The digital part is fully static so that it almost does not consume power. All of the interrupts (except BDIS_ACON) are fully operational in Power-down mode, as is the I2C interface. Table 9.
1
X = Don't care - = Reserved Bit order: 0...7
Power down mode setup
SUSPEND PIN 1 Control register 1 X1X0XX0Control register 2 00XX00X0 Control register 3 -XXXX0XX
SUSPEND BIT
6.7.2
USB Modes
The STOTG04 transceiver has two basic USB operational modes. These modes define how the digital IO pins of the transceiver will be used. Independently of USB operating mode, some signals always have the same function (see Table 10). Table 10. Digital interface signals
Signal RCV VP VM OE_TP_INT/ Function Differential receiver output D+ single-ended receiver output D- single-ended receiver output Output enable signal of the differential driver
The RCV signal is active in the VP_VM mode only. Its output driver is controlled by the OE_TP_INT/ signal. Operating modes are described below. The meanings of the DAT_VP and SE0_VM signals depend on the mode of operation. Both of these signals can be bidirectional or unidirectional. The
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Block description
STOTG04E
direction is controlled by bidi_en Bit of Control Register 3 (described later). When these signals are bidirectional, the direction is controlled by the OE_TP_INT/ signal (see Tables 11 and 12). The actual mode of operation is controlled by the dat_se0 Bit of Control Register 1 (see Tables 11 and 12) Table 11. DAT_SE0 (dat_se0 = 1)
OE/* 0 1 X DAT_VP Differential driver input Differential receiver output Differential driver input SE0_VM SE0 driver input SE0 detector output SE0 driver input
bidi_en 1 0
Table 12.
VP_VM (dat_se0 = 0)
OE/* 0 1 X DAT_VP D+ driver input D+ receiver output D+ driver input SE0_VM D- driver input D- receiver output D- driver input
bidi_en 1 0
* State of the OE_TP_INT/ signal.
In the USB mode of operation it is necessary to control the rise and fall times of the transmission driver. These times are different for low-speed and full-speed USB settings. Selection of actual USB speed can be done using the bit speed of Control Register 1 or/and the SPEED pin (see table 13). Table 13. USB Speed selection
speed bit 0 X 1 SPEED Pin X 0 1 USB Mode low-speed full-speed
6.7.3
UART and I2C modes
The actual mode of operation is selectable by the transp_en and uart_en Bits of Control Register 1 (see table 14). Table 14. Transceiver modes
transp_en 0 0 1 1 uart_en 0 1 0 1 STOTG04 Mode USB UART I2C UART (1)
OE_TP_INT/ signal is low. The transceiver automatically enables the pull-up resistor on the SDA line in this mode. The internal I2C slave interface of the transceiver does not react to commands from the master. Communication addressed to the STOTG04 device is mirrored to the D+ pin and responses from this pin are mirrored back to the SDA pin. The D- pin mirrors the SCL clock. In the UART mode it is possible to select driver direction on both the D+ and D- pins. The selection is done using the bdir[1] and bdir[0] Bits of Control Register 3 (see table 15).
(1) In reality, it is not possible to set both these bits at the same time. In this case, only uart_en bit will remain set. In the I2C mode the D+ and D- lines act respectively as I2C SDA and SCL signals when the
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STOTG04E
Table 15.
0 0 1 1
Block description
UART Drivers direction
bdir[0] 0 1 0 1 DAT_VP D+ SE0_VM D
bdir[1]
6.7.4
Audio mode
In this mode the transceiver has to release all of its drivers and pull-up/pull-down resistors on the D+, Dand ID pins, leaving them in a high impedance state. This allows these lines to be used for transmission of audio signals. The transceiver should not provide voltage on its VBUS output in this mode. Conditions described in Table 16 force the transceiver into the audio mode. Table 16. Audio mode setup
uart_en bit 0 OE_TP_INT/ signal 1 Control Register 2 00000000 0
transp_en bit
6.8
Registers
The STOTG04 transceiver device is controlled using register settings (see Table 17). These registers can be set and read via the I2C bus. Table 17. Register set
Size (bits) 16 16 8 8 8 8 8 8 8 Acc (1) r r r/s/c r/s/c r/s/c r r/s/c r/s/c r/s/c Addr (2) 00h 02h 04h 05h 06h 07h 12h 13h 08h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Description STMicroelectronics ID (0483h) - LSB first ID of the STOTG04 (A0C4h) - LSB first First Control Register Second Control Register Third Control Register Current state of signals generating interrupts Latched source that generated interrupt Enables interrupts on falling edge Enables interrupts on rising edge
Register Vendor ID Product ID Control 1 Control 2 Control 3 Interrupt Source Interrupt Latch Interrupt Mask False Interrupt Mask True
(1) Access type can be: read (r), set (s), clear (c). (2) The first address is to set, the second one to clear bits.
When writing to the set address, any "1" will set the associated Bit to logic "1". When writing to the clear address, any "1" will set the associated Bit to logic "0". It is possible to read from any address, whether it is a set or clear address. See Tables 18, 19, 20, 21 for bit setting details.
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Block description
STOTG04E
Table 18.
Control register 1
Name Speed Suspend dat_se0 Bit 0 1 2 3 4 5 6 7 R(1) 1 1 0 0 0 0 0 0 = low-speed mode 1 = full-speed mode 0 = normal operation 1 = power-down mode 0 = VP_VM mode 1 = DAT_SE0 mode Enable transparent I2C mode Enable A-device to connect if B-device disconnect detected When set and suspend = 1, then OE_TP_INT/ becomes interrupt output Enable UART mode (higher priority than transp_en bit) Reserved Description
transp_en bdis_acon_en oe_int_en uart_en
(1) State of the bit after reset.
Setting the bdis_acon_en bit enables automatic switching of the D+ pull-up resistor when the device receives an SE0 longer than half of the bit period. This function should not be used in low-speed operation. Table 19. Control register 2
Name dp_pull-up dm_pull-up dp_pull-down dm_pull-down id_gnd_drv vbus_drv vbus_dischrg vbus_chrg Bit 0 1 2 3 4 5 6 7 R 0 0 1 1 0 0 0 0 Description Connect D+ pull-up Connect D- pull-up Connect D+ pull-down Connect D- pull-down Connect ID pin to ground Provide power to VBUS Discharge VBUS through a resistor to ground Charge VBUS through a resistor
It is not possible to set vbus_drv, vbus_dischrg and vbus_chrg at the same time; the bit having higher priority will remain set while the others will be cleared. Vbus_drv has higher priority than vbus_dischrg which has higher priority than vbus_chrg. Table 20. Control register 3
Name rec_bias_en bidi_en bdir[0] bdir[1] audio_en psw_en 2V7_en Bit 0 1 2 3 4 5 6 7 R 0 0 1 0 1 0 0 0 Description Reserved Enables transmitter bias even during USB receive When set, then DAT_VP and SE0_VM pins become bidirectional otherwise they are inputs only Direction of the drivers between DAT_VPDP and SE0_VMDM in the UART mode Enables car-kit interrupt detector Enables external charge pump control on the ADR_PSW pin. Disables internal charge pump. Enables 2.7V voltage regulation instead of 3.3V
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STOTG04E
Table 21. Interrupt registers (*)
Bit 0 1 2 3 4 5 6 7 R 0 0 0 0 0 0 0 0 Description A-device VBUS valid comparator
Block description
Name vbus_vld sess_vld dp_hi id_gnd dm_hi id_float bdis_acon cr_int
Session valid comparator D+ pin is asserted high during SRP ID pin grounded D- pin is asserted high ID pin floating Set when bdis_acon_en bit is set and transceiver asserts dp_pull-up after detecting B-device disconnect Car-kit interrupt
(*) Bit order is the same for all four interrupt related registers. Meaning of each register is described in Table 17.
6.9
I2C Bus interface
All of the STOTG04 transceiver registers are accessible through the I2C bus (see Figure 12). The device contains a slave controller which provides communication with an external master. The I2C interface consists of three pins: * SDA (Serial Data); * SCL (Serial Clock); * ADR_PSW (is the LSB of the device address).
6.10
0
Device address
1 0 1 1 0 adr
The USB-OTG transceiver has following 7-bit I2C device address:
The adr bit represents current state of the ADR_PSW device pin. It means that the address can be either 2Ch or 2Dh according to the ADR_PSW pin.
6.11
Bus protocol
Any device that sends data to the bus is defined as the transmitter. Any device that reads the data is the receiver. The device that controls data transfers is the bus master, while the transmitter or receiver is the slave device. The master initiates data transfers and provides the serial clock. The STOTG04 is always the slave device. Operation of the I2C bus is described by following figure 12.
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Block description
STOTG04E
Figure 12. Basic operation of the I2C Bus
Start condition is identified by a falling edge of the SDA signal while the SCL is stable at high level. The start condition must precede any data transfer on the bus. Stop condition is identified by a rising edge of the SDA signal while the SCL is stable at high level. The stop condition terminates any communication between device and master. The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDA line after sending eight data bits. During the ninth clock period the receiver pulls the SDA line low to acknowledge the receipt of the eight data bits. If the receiver is a slave device and it does not generate acknowledge bit then the bus master can generate the stop condition in order to abort the transfer. Below is described format of I2C commands. All tables use common format and symbols. Every data word consists of eight bits with most significant bit first and least significant bit last. Symbols used in the tables are: * S - start condition * P - stop condition * A - acknowledge bit * N - negative acknowledge WRITE Command to the transceiver device is described by following table. It is possible to write into several consecutive registers during one write command.
S Data (K) Device address A Data (K+1) 0 A A .. Reg. address K Data (K+N) A A P
READ command consists of dummy write to set proper address of a register followed by real read sequence.
S S Data (K+1) Device address Device address A Data (K+2) 0 1 A A A ... Reg. address K Data (K) Data (K+N) N A P A P
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Block description
6.12
External charge pump switch
The ADR_PSW pin has two functions. State of this pin is always latched into a register on the rising edge of the RESET/ signal. The latched value is used as a least significant bit of the I2C address. After the address is latched, this pin can be set as an output by setting the PSW_EN bit of the Control Register 3. Output value of the pin can be controlled by the VBUS_DRV bit of the Control Register 2. The output is active low when the pin is high during reset; otherwise the output is active high. When the PSW_EN bit is set the internal charge pump is switched off. Example connection of an external charge pump is shown in following figure. When the charge pump control signal would be active high, the ADR_PSW pin should be pulled down instead of high. Figure 13. External charge pump application
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Package mechanical data
STOTG04E
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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STOTG04E
Package mechanical data
QFN24 (4x4) MECHANICAL DATA
mm. DIM. MIN. A A1 b D D2 E E2 e L 0.40 0.00 0.18 3.9 1.95 3.9 1.95 0.50 0.60 15.7 TYP MAX. 1.00 0.05 0.30 4.1 2.25 4.1 2.25 0.0 7.1 153.5 76.8 153.5 76.8 19.7 23.6 MIN. TYP. MAX. 39.4 2.0 11.8 161.4 88.6 161.4 88.6 mils
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Package mechanical data
STOTG04E
Tape & Reel QFNxx/DFNxx (4x4) MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 4.35 4.35 1.1 4 8 12.8 20.2 99 101 14.4 0.171 0.171 0.043 0.157 0.315 TYP MAX. 330 13.2 0.504 0.795 3.898 3.976 0.567 MIN. TYP. MAX. 12.992 0.519 inch
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STOTG04E
Revision history
8
Table 22.
Revision history
Revision history
Revision 1 2 3 First Release. Mistake on Table 1. Added details in paragraph 6.7.1, comments to table 19 and description in paragraph 6.12. Changes
Date 13-Jan-2006 01-Feb-2006 17-Oct-2006
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STOTG04E
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