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| (R) DEVICE SPECIFICATION SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER BiCMOS PECL CLOCK GENERATORTRANSCEIVER SONET/SDH/ATM 155 MBIT/S QUAD GENERAL DESCRIPTION S3029 S3029 FEATURES * * * * * * * * * * Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter generation Five on-chip high frequency PLLs with internal loop filters for clock recovery Supports clock recovery for STS-3/STM-1 (155.52 Mbit/s) NRZ data Clock Multiplier PLL for transmit clock generation 19.44 or 51.84 MHz reference frequency Lock detect--monitors run length and frequency Low-jitter differential interface 3.3V supply Available in a 64-pin TQFP package Compatible with IgT WAC-413 ATM QuadUNI processor The function of the S3029 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment. The S3029 is implemented using AMCC's proven Phase Locked Loop (PLL) technology. The S3029 receives four STS-3/STM-1 scrambled NRZ signals and recovers the clock from the data and generates a 155 MHz transmit clock. The chip outputs a differential PECL bit clock and retimed data. Figure 1 shows a typical network application. The S3029 utilizes five on-chip PLLs which consist of a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the serial data input. A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage. A block diagram is shown in Figure 2. There is a single clock multiplier PLL which generates a 155 MHz transmit clock from a 19.44 or 51.84 MHz input. Figure 1. System Block Diagram 155 Mbp/s Network Interface Processor 155 Mbp/s Network Interface Processor 155 Mbp/s Network Interface Processor 155 Mbp/s Network Interface Processor TXCLK TXDATA RXDATA RXCLK TXCLK TXDATA RXDATA RXCLK TXCLK TXDATA RXDATA RXCLK TXCLK TXDATA RXDATA RXCLK RX Optical Transceiver Optical Transceiver RX TXCLK TXDATA RXDATA RXCLK TXCLK TXDATA RXDATA RXCLK 155 Mbp/s Network Interface Processor 155 Mbp/s Network Interface Processor 155 Mbp/s Network Interface Processor 155 Mbp/s Network Interface Processor RX Optical Transceiver Optical Transceiver RX S3029 Optical Transceiver Optical Transceiver S3029 RX RX TXCLK TXDATA RXDATA RXCLK TXCLK TXDATA RXDATA RXCLK RX Optical Transceiver Optical Transceiver RX February 19, 1999 / Revision B 1 S3029 Figure 2. Functional Block Diagram REFSEL REFCKINP REFCKINN TSTCLKEN SD0 LCKREFN0 REFCLK SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER PLL CLOCK MULTIPLIER 155 MHz CLK TXCLKOP TXCLKON LOCKDET0 SERDATIP0 SERDATIN0 PLL CLOCK RECOVERY BITCLK D Q QN SERDATOP0 SERDATON0 SD1 LCKREFN1 REFCLK SERCLKOP0 SERCLKON0 LOCKDET1 SERDATIP1 SERDATIN1 PLL CLOCK RECOVERY BITCLK D Q QN SERDATOP1 SERDATON1 SD2 LCKREFN2 REFCLK SERCLKOP1 SERCLKON1 LOCKDET2 SERDATIP2 SERDATIN2 PLL CLOCK RECOVERY BITCLK D Q QN SERDATOP2 SERDATON2 SD3 LCKREFN3 REFCLK SERCLKOP2 SERCLKON2 LOCKDET3 SERDATIP3 SERDATIN3 PLL CLOCK RECOVERY BITCLK D Q QN SERDATOP3 SERDATON3 SERCLKOP3 SERCLKON3 2 February 19, 1999 / Revision B SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER S3029 OVERVIEW The S3029 supports clock recovery for the STS-3/ STM-1 data rate. The LVPECL differential serial data is input to the chip and clock recovery is performed on the incoming data stream. An external reference clock is required to minimize the PLL lock time and provide a stable output clock source in the absence of serial input data. Retimed data and clock are output from the S3029. S3029 Figure 3. Input Jitter Tolerance Specification Sinusodal Input Jitter Amplitude (UI p-p) 15 1.5 0.15 f0 f1 f2 f3 ft CHARACTERISTICS Performance The S3029 PLL complies with the minimum jitter tolerance for clock recovery proposed for SONET/SDH equipment defined by the T1X1.6/91-022 document, when used with differential inputs and outputs as shown in Figure 3. Input Jitter Tolerance Input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1 dB optical/electrical power penalty. SONET input jitter tolerance requirements are shown in Figure 3. The measurement condition is the input jitter amplitude which causes an equivalent of 1 dB power penalty. Serial Data Output Set-up and Hold Time The output set-up and hold times are represented by the waveforms shown in Figure 4. OC/STS Level 3 Frequency f0 (Hz) 10 f1 (Hz) 30 f2 (Hz) 300 f3 (kHz) 6.5 ft (kHz) 75 Figure 4. Clock Output to Data Transition Delay SERCLKOP/N SERDATOP/N t su th Output Frequency 155.52 MHz SERDATOP/N Setup Time SERDATOP/N Hold Time 2.5 ns 2.5 ns Table 1. REFSEL 0 1 Reference Clock Frequency (MHz) 19.44 MHz 51.84 MHz February 19, 1999 / Revision B 3 S3029 SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER S3029 Transceiver Pin Assignment and Descriptions Pin Name REFCKINP/N Level Diff. LVPECL I/O I Pin # 53,54 Description Reference Clock. 19.44 or 51.84 MHz input used to generate the 155 MHz transmit clock. This input is also used as the reference for the internal bit clock in the absence of serial data or during reset in clock recovery mode. Serial Data In. Clock is recovered from the transitions on these inputs. SERDATIP/N0 SERDATIP/N1 SERDATIP/N2 SERDATIP/N3 TSTCLKEN Diff. LVPECL I 1,2 7,8 15,16 22,21 3 LVTTL I Test Clock Enable. Active High. Used during production test to bypass the VCO in the PLL. Tie to ground for normal operation. Signal Detect. Active High. A single-ended 10K ECL input to be driven by the external optical receiver module to indicate detection of received optical power. When SD is inactive, the data on the Serial Data In (SERDATIP/N) pins will be internally forced to a constant zero, LOCKDET forced low, and the PLL forced to lock to the REFCK input. When SD is active, data on the SERDATIP/N pins will be processed normally. This pin has an internal 1K pull-down. Lock to Reference. Active Low. When active, this input will force the CRU to lock to the local reference clock. This input has an internal 1K pull-up and may be left unconnected if not used. Reference Select. This input selects the frequency of the REFCKIN/P. (See Table 1). Lock Detect. Active High. Clock recovery indicator. Set high when the internal clock recovery has locked onto the incoming datastream. LOCKDET is an asynchronous output. This output is deasserted when LCKREFN is low, or when SD is low; in which case the PLL locks to the reference clock. When the data rate of the SERDATIP/N input is not within the capture range of the PLL, the LOCKDET output will toggle until proper data is restored. Serial Data Out. This signal is the delayed version of the incoming data stream (SERDATI) updated on the falling edge of Serial Clock Out (SERCLKOP). Serial Clock Out. This signal is phase aligned with Serial Data Out (SERDATO) when Lock Detect (LOCKDET) is High. When Lock Detect is Low, Serial Clock Out is synchronous with Reference Clock (REFCKIN). Transmit Clock Out. This is a 155 MHz clock which can be used by the controller as a clock source for the transmitter logic. SD0 SD1 SD2 SD3 LVPECL I 56 55 52 51 LCKREFN0 LCKREFN1 LCKREFN2 LCKREFN3 REFSEL LVTTL I 64 63 60 59 6 LVTTL I LOCKDET0 LOCKDET1 LOCKDET2 LOCKDET3 LVTTL O 9 14 17 20 SERDATOP/N0 Diff. SERDATOP/N1 LVPECL SERDATOP/N2 SERDATOP/N3 SERCLKOP/N0 SERCLKOP/N1 SERCLKOP/N2 SERCLKOP/N3 TXCLKOP/N Diff. LVPECL O 44,43 40,39 30,29 26,25 46,45 38,37 32,31 24,23 50,49 O Diff. LVPECL O 4 February 19, 1999 / Revision B SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER S3029 Transceiver Pin Assignment and Descriptions (continued) Pin Name TXoPOW CRUoPOW0 CRUoPOW1 CRUoPOW2 CRUoPOW3 TXoGRD CRUoGRD0 CRUoGRD1 CRUoGRD2 CRUoGRD3 VCOVCC OPAVCC ACRUPOW0 ACRUPOW1 ACRUPOW2 ACRUPOW3 VCOGRD OPAGRD ACRUGRD0 ACRUGRD1 ACRUGRD2 ACRUGRD3 Level Digital Power I/O -- Pin # 48 42 36 34 28 47 41 35 33 27 58 62 4 10 12 18 57 61 5 11 13 19 Description +3.3V (individual decoupling) S3029 Digital Ground -- 0V (ground) Analog Power -- +3.3V via individual Ferrite bead (e.g. Murata BLM32A06) and individual decoupling. Analog Ground -- 0V (ground) February 19, 1999 / Revision B 5 S3029 Figure 5. S3029 64 TQFP Package SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER 6 February 19, 1999 / Revision B SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER Figure 6. S3029 64 TQFP Pinout LCKREFN0 LCKREFN1 OPAVCC OPAGRD LCKREFN2 LCKREFN3 VCOVCC VCOGRD SD0 SD1 REFCKINN REFCKINP SD2 SD3 TXCLKOP TXCLKON S3029 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 February 19, 1999 / Revision B LOCKDET2 ACRUPOW3 ACRUGRD3 LOCKDET3 SERDATIN3 SERDATIP3 SERCLKON3 SERCLKoP3 SERDATON3 SERDATOP3 CRUoGRD3 CRUoPOW3 SERDATON2 SERDATOP2 SERCLKON2 SERCLKOP2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SERDATIP0 SERDATIN0 TSTCLKEN ACRUPOW0 ACRUGRD0 REFSEL SERDATIP1 SERDATIN1 LOCKDET0 ACRUPOW1 ACRUGRD1 ACRUPOW2 ACRUGRD2 LOCKDET1 SERDATIP2 SERDATIN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3029 TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TXoPOW TXoGRD SERCLKOP0 SERCLKON0 SERDATOP0 SERDATON0 CRUoPOW0 CRUoGRD0 SERDATOP1 SERDATON1 SERCLKOP1 SERCLKON1 CRUoPOW1 CRUoGRD1 CRUoPOW2 CRUoGRD2 7 S3029 Performance Specifications SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER Parameter Nominal VCO Center Frequency Min Typ 155.52 Max Units MHz Condition -20 Reference Clock Frequency Tolerance -100 +20 ppm For SONET OC-3 Transmit Frequency Tolerance For 155 Mbit/s ATM Transmit Frequency Tolerance +100 ppm OC-3/STS-3 Capture Range1 Lock Range Clock Output Duty Cycle Acquisition Lock Time1 OC-3/STS-3 Reference Clock Input Duty Cycle Reference Clock Rise & Fall Times PECL Output Rise & Fall Times TXCLKOP/N Jitter Generation 1 Guaranteed but not tested. 200ppm +8,-12% 40 60 64 30 70 2.0 1.5 .045 .07 % of UI sec % of period ns ns U.I.pp 10% to 90% of amplitude 10% to 90%, 50 to VCC-2V equivalent load, 5 pf cap STM-1: F3=65 KHz, F4=1.3 MHz SONET/SDH spec limit = 0.15 U.I. With device already powered up and valid REFCLK. With respect to fixed reference frequency 8 February 19, 1999 / Revision B SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER Recommended Operating Conditions Parameter Ambient Temperature under Bias (industrial) Ambient Temperature under Bias (commercial) Junction Temperature under Bias Voltage on VCC with Respect to GND Voltage on Any TTL Input Pin Voltage on Any PECL Input Pin PECL Output Source Current (50 to Vcc-2V) ICC Supply Current S3029 Min -40 0 -10 3.14 0.0 VCC -2 Typ Max +85 +70 +130 Unit C C C V V V mA mA 3.3 3.46 VCC VCC 14 225 25 276 Absolute Maximum Ratings Parameter Case Temperature under Bias Junction Temperature under Bias Storage Temperature Voltage on VCC with Respect to GND Voltage on any TTL Input Pin Voltage on any PECL Input Pin TTL Output Sink Current TTL Output Source Current High Speed PECL Output Source Current Static Discharge Voltage 500 Min -55 -55 -65 -0.5 -0.5 VCC -2.0 Typ Max +125 +150 +150 +7.0 +5.5 VCC 20 10 50 Unit C C C V V V mA mA mA V February 19, 1999 / Revision B 9 S3029 TTL Input/Output DC Characteristics1 (TA = -40C to +85C, VCC = 3.3 V 5%) SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER Symbol VIL2 VIH2 IIL IIH II IOS VIK VOL VOH Parameter Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Test Conditions Guaranteed Input LOW Voltage for all inputs Guaranteed Input HIGH Voltage for all inputs VCC = MAX, VIN = 0.5V VCC = MAX, VIN = 2.7V Min 2.0 -400.0 Max 0.8 Unit Volts Volts uA 50.0 1.0 -50.0 -1.2 0.5 2.2 -5.0 uA mA mA Volts Volts Volts Input HIGH Current at Max VCC VCC = MAX, VIN = 3.5V Output Short Circuit Current Input Clamp Diode Voltage TTL Output LOW Voltage TTL Output HIGH Voltage VCC = MAX, VOUT = 0.5V VCC = MIN, IIN = -18.0mA VCC = MIN, IOL = 2mA VCC = MIN, IOH = -.10mA 2. These input levels provide a zero-noise immunity and should only be tested in a static, noise-free environment. PECL Input/Output DC Characteristics1,2 (TA = -40C to +85C, VCC = 3.3V 5%) Symbol VIL VIH VIL VIH VID IIHD IILD IIH IIL VOL VOH VOD Parameter Input LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Input Diff. Voltage Diff. Input High Current Diff. Input Low Current Single-ended input High Current Single-ended input LOW Current Min VCC -2.000 VCC -1.225 VCC -2.000 VCC -1.750 0.200 -0.500 -0.500 Typ Max VCC -1.441 VCC -0.570 VCC -0.700 VCC -0.450 Unit Volts Volts Volts Volts Volts A A mA mA Volts Volts Volts Conditions Guaranteed Input LOW Voltage for single-ended inputs Guaranteed Input HIGH Voltage for single-ended inputs Guaranteed Input LOW Voltage for differential inputs Guaranteed Input HIGH Voltage for differential inputs Differential Input Voltage VID = 500mV VID = 500mV SD Inputs have internal 1K to GND load resistor. SD Inputs have internal 1K to GND load resistor. 400 ohm termination to GND 400 ohm termination to GND Differential Output Voltage 0.500 1.400 20.000 20.000 4 4 Output LOW Voltage Output HIGH Voltage Output Diff. Voltage VCC -2.000 VCC -1.110 0.390 VCC -1.300 VCC -0.670 1.000 1. These conditions will be met with no airflow. 2. When not used, tie the positive differential PECL pin to VCC and the negative differential PECL pin to ground via a 3.9K resistor. PECL Output Loading Recommended Termination of Differential PECL Signals 400 400 400 100 10 February 19, 1999 / Revision B SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER Ordering Information PREFIX DEVICE PACKAGE S3029 S- Integrated Circuit 3029 A - 64 TQFP X Prefix XXXX Device XX Package IS O 90 0 RT IFI Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (619) 450-9333 * (800) 755-2622 * Fax: (619) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation February 19, 1999 / Revision B E D 1 CE 11 |
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