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| EM640FP16 Series Low Power, 256Kx16 SRAM Document Title 256K x16 bit Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. 0.0 0.1 0.2 History Initial Draft 2'nd Draft 3'rd Draft Changed Icc, Icc1 value Changed ISB1 test conditions, Changed VDR & IDR measurement condition Draft Date October 24 , 2002 November 11 , 2002 December 23 , 2002 Remark Preliminary 0.3 0.4 4'th Draft 5'th Draft Add Pb-free part number EM640FP16: Changed Icc2 value Changed Package Dimension February 13 , 2004 April 11 , 2006 Emerging Memory & Logic Solutions Inc. IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160 Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM640FP16 Series Low Power, 256Kx16 SRAM FEATURES * * * * * * Process Technology : 0.18m Full CMOS Organization : 256K x 16 bit Power Supply Voltage : 1.65V ~ 2.2V Low Data Retention Voltage : 1.0V(Min.) Three state outputs Package Type : 48-FPBGA 6.0x7.0 GENERAL DESCRIPTION The EM640FP16 families are fabricated by EMLSI's advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Typ.) 1 A Operating (ICC1.Max) 2 mA PKG Type 48-FPBGA (6.0x7.0) EM640FP16 Industrial (-40 ~ 85oC) 1.65~2.2V 70ns1) 1. The parameter is measured with 30pF test load. PIN DESCRIPTION 1 A B C D E F G H 2 3 4 5 6 FUNCTIONAL BLOCK DIAGRAM Pre-charge Circuit LB I/O9 OE UB A0 A3 A5 A17 DNU A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CS1 I/O2 I/O4 I/O5 I/O6 WE A11 CS2 I/O1 I/O3 VCC VSS I/O7 I/O8 DNU A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 VCC Row Select VSS I/O10 I/O 11 VSS V CC I/O 12 I/O 13 Memory Array 2048 x 2048 I/O1 ~ I/O8 I/O9 ~ I/O16 Data Cont I/O15 I/O 14 I/O16 DNU DNU A8 Data Cont I/O Circuit Column Select 48-FPBGA : Top view (ball down) WE OE UB LB Control Logic Name CS1,CS2 OE WE A 0~A17 Function Chip select inputs Output Enable input Write Enable input Address Inputs Name Vcc Vss UB LB DNU Function Power Supply Ground Upper Byte (I/O9~16) Lower Byte (I/O1~8) Do Not Use CS1 CS2 I/O 1~I/O16 Data Inputs/outputs 2 EM640FP16 Series Low Power, 256Kx16 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature Symbol VIN, VOUT VCC PD TA Minimum -0.5 to 2.5V -0.3 to 2.5V 1.0 -40 to 85 Unit V V W oC * Stresses greater than those listed above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS1 H X X L L L L L L L L CS2 X L X H H H H H H H H OE X X X H H L L L X X X WE X X X H H H H H L L L LB X X H L X L H L L H L UB X X H X L H L L H L L I/O1-8 High-Z High-Z High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Stand by Stand by Active Active Active Active Active Active Active Active Note: X means don't care. (Must be low or high state) 3 EM640FP16 Series Low Power, 256Kx16 SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage 1. 2. 3. 4. Symbol VCC VSS VIH VIL Min 1.65 0 1.4 -0.33) Typ 1.8 0 - Max 2.2 0 VCC + 0.32) 0.4 Unit V V V V TA= -40 to 85oC, otherwise specified Overshoot: VCC +1.0 V in case of pulse width < 20ns Undershoot: -1.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Input capacitance Input/Ouput capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO ICC ICC1 Average operating current ICC2 Output low voltage Output high voltage VOL VOH Cycle time = Min, IIO=0mA, 100% duty, CS1=VIL, CS2=V IH , LB=V IL or/and UB=VIL VIN =V IL or VIH IOL = 0.1mA IOH = -0.1mA CS1>V CC-0.2V, CS2>VCC-0.2V (CS 1 controlled) or 0V Test Conditions Min -1 -1 - Typ - Max 1 1 2 2 Unit uA uA mA mA 1.4 - 15 0.2 - mA V V Standby Current (CMOS) ISB1 LL LF - 1 5 uA 4 EM640FP16 Series Low Power, 256Kx16 SRAM VTM3) R12) AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.2 to VCC-0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 0.9V Output Load (See right) : CL = 100pF+ 1 TTL CL1) = 30pF + 1 TTL 1. Including scope and Jig capacitance R2=3150 ohm 2. R 1=3070 ohm, 3. VTM =1.8V CL1) R22) READ CYCLE (Vcc =1.65 to 2.2V, Gnd = 0V, TA = -40oC to +85oC) Parameter Read Cycle Time Address Access Time Chip Select to output Output Enable to valid output UB, LB Acess time Chip select to low-Z output UB, LB enable to low-Z output Output Enable to Low-Z output Chip disable to high-Z output UB, LB disable to high-Z output Output disable to high-Z output Output hold from address change Symbol tRC tAA tco1, tco2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH 70ns Min 70 Max 70 70 35 70 10 10 5 0 0 0 10 25 25 25 - Unit ns ns ns ns ns ns ns ns ns ns ns ns WRITE CYCLE (Vcc =1.65 to 2.2V, Gnd = 0V, TA = -40oC to +85oC) Parameter Write Cycle Time Chip Select to end of write Address Setup time Address valid to end of write UB, LB valid to end of write Write pulse width Write recovery time Write to ouput high-Z Data to write time overlap Data hold from write time End write to output low-Z Symbol tWC tCW1, tCW2 tAs tAW tBW tWP tWR tWHZ tDW tDH tOW 70ns Min 70 60 0 60 60 55 0 0 30 0 5 Max 25 Unit ns ns ns ns ns ns ns ns ns ns ns 5 EM640FP16 Series Low Power, 256Kx16 SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) tRC Address tAA CS1 tCO tOH CS2 tBA UB,LB tOE OE tOLZ Data Out High-Z tBLZ tLZ tWHZ Data Valid tHZ tBHZ tOHZ NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 EM640FP16 Series Low Power, 256Kx16 SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED) tWC Address tCW(2) CS1 tWR(4) CS2 tAW tBW UB,LB tWP(1) WE tAS(3) Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tDH High-Z tOW TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED) tWC Address tAS(3) CS1 tCW(2) tWR(4) CS2 tAW tBW UB,LB tWP(1) WE tDW Data in Data Valid tDH Data out High-Z High-Z 7 EM640FP16 Series Low Power, 256Kx16 SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED) tWC Address tCW(2) CS1 tWR(4) CS2 tAW tBW UB,LB tAS(3) WE tDW Data in Data out High-Z Data Valid tWP(1) tDH High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high. 8 EM640FP16 Series Low Power, 256Kx16 SRAM DATA RETENTION CHARACTERISTICS Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time NOTES Symbol V DR IDR tSDR Test Condition ISB1 Test Condition (Chip Disabled) 1) VCC=1.2V, ISB1 Test Condition (Chip Disabled) 1) See data retention wave form Min 1.0 Typ - Max 2.2 Unit V 0 tRC 0.5 - 2 - uA ns - tRDR 1. See the ISB1 measurement condition of datasheet page 4. DATA RETENTION WAVE FORM tSDR Vcc 1.65V Data Retention Mode tRDR 1.4V VDR CS1 GND Vcc 1.65V CS2 tSDR CS1 > Vcc-0.2V Data Retention Mode tRDR VDR 0.4V GND CS 2 < 0.2V 9 EM640FP16 Series Low Power, 256Kx16 SRAM Unit: millimeters PACKAGE DIMENSION 48 Ball Fine Pitch BGA (0.75mm ball pitch) Top View B Bottom View A1 index Mark B B1 0.4 0.4 6 A #A1 B C C 5 4 3 2 1 E C1/2 F G H B/2 Side View 0.26 E2 D 0.27Typ. Detail A A Y E E1 Min A B B1 C C1 D E E1 E2 Y 5.95 6.95 0.30 - Typ 0.75 6.00 3.75 7.00 5.25 0.35 0.85 0.58 0.27 - Max 6.05 7.05 0.40 0.90 0.08 NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75x0.75) (typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) 10 0.58Typ. C C1 C D EM640FP16 Series Low Power, 256Kx16 SRAM MEMORY FUNCTION GUIDE EM X XX X X X XX X X - XX XX 1. EMLSI Memory 2. Device Type 3. Density 4. Option 5. Technology 6. Operating Voltage 1. Memory Component 2. Device Type 6 ------------------------ Low Power SRAM 7 ------------------------ Pseudo SRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 16 ----------------------- 16M 32 ----------------------- 32M 64 ----------------------- 64M 4. Option 0 ----------------------- Dual CS 1 ----------------------- Single CS 5. Technology Blank ------------------ CMOS F ------------------------ Full CMOS 6. Operating Voltage Blank ------------------- 5V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 7. Orginzation 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 11 11. Power 10. Speed 9. Packages 8. Version 7. Orgainzation 8. Version Blank ----------------- Mother die A ----------------------- First version B ----------------------- Second version C ----------------------- Third version D ----------------------- Fourth version E ----------------------- Fifth version 9. Package Blank ---------------------- Package W --------------------- Wafer 10. Speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 10 --------------------- 100ns 12 --------------------- 120ns 11. Power LL ------------ Low Low Power LF ------------ Low Low Power(Pb-Free & Green) L ------------- Low Power S ------------- Standard Power |
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