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PI2EQX3232B
3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver
Features
* * * * * * * * * * * Supports data rates up to 3.2Gbps on each lane Adjustable Transmiter De-Emphasis & Amplitude Adjustable Receiver Equalization Spectrum Reference Clock Buffer Output Optimized for SATAi/m applications Input signal level detection & output squelch on all channels 100-Ohm Differential CML I/O's Low Power (100mW per Channel) Standby Mode - Power Down State VDD Operating Range: 1.8V +/-0.1V Packaging (Pb-free & Green):48-contact TQFN
Description
Pericom Semiconductor's PI2EQX3232B is a low power, signal Re-Driver. The device provides programmable equalization, amplification, and de-emphasis, to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference (ISI). PI2EQX3232B supports four 100-Ohm Differential CML data I/O's between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user's platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the Re-Driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the signal after the Re-Driver. A low-level input signal detection and output squelch function is provided for all four channels. Each channel operates fully independantly. When a channel is enabled (EN_x=1) and operating, that channels input signal level (on xI+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the output driver switches off, and the pin is pulled to VDD via a high impedance resistor. If the input level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to providing signal re-conditioning, Pericom's PI2EQX3232B also provides power management Stand-by mode operated by an Enable pin.
Block Diagram
Signal Detect
Pin Description
Sel_EQ_A
Sel_EQ_B
Sel_DE_A
Sel_DE_B
Sel_OL_A Sel_OL_B
EN_C
39
EN_D
38
EN_A
EN_B
VDD
48
47
46
45
44
43
42
41
40
CML CML xI+ Equalizer xISEL_EQ _x EN_x Power Management SEL_OL_x SEL_DE_ x Limiting Amp xOxO+
AI+ AIVDD BO + BOVDD CI+ CIVDD DO + DOVDD
1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31
37
VDD
AO + AO VDD BI+ BIVDD CO + CO VDD DI+ DIGND
GND
30 29 28 27 26 25
-- Repeated 4 times --
CKINCKIN+
Buffer
EN_ CLK
13
OUTOUT+
14
15
16
17
18
19
20
21
22
23
CKINSel_EQ_C
Sel_EQ_D
OUT+
Sel_OL_C Sel_OL_D
Sel_DE_C
EN_CLK
CKIN+
Sel_DE_D
IREF
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OUT-
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IREF
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PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver Pin Description
Pin # 1 2 36 Pin Name AI+ AIAO+ I/O I I O Description Positive CML Input Channel A with internal 50 pull down Negative CML Input Channel A with internal 50 pull down Positive CML Output Channel A internal 50 pull up to VDD during normal operation and 2k when EN_A=0. Drives to output common mode voltage when input is 35 33 32 4
AOBI+ BIBO+
O I I O
5 7 8 14 15 30
BOCI+ CICKIN+ CKINCO+
O I I I I O
29 27 26 10
CODI+ DIDO+
O I I O
11
DOEN_ [A,B,C,D] EN_CLK GND IREF OUT0+ OUT1SEL_EQ_A SEL_EQ_B SEL_EQ_C SEL_EQ_D
O
41, 40, 39, 38 13 25, Center Pad 24 22 23 47 46 16 17
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I I PWR O O O I I I I
Selection pins for equalizer (see Amplifier Configuration Table) w/ 50k internal pull up
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PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver Pin Description (Continued)
Pin # 45 44 18 19 43 42 20 21 3,6,9,12,28, 31,34,37,38 Pin Name SEL_OL_A SEL_OL_B SEL_OL_C SEL_OL_D SEL_DE_A SEL_DE_B SEL_DE_C SEL_DE_D VDD I/O I I I I I I I I PWR Description Selection pins for amplifier (see Amplifier Configuration Table) w/ 50k internal pull up
Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 50k internal pull up
1.8V Supply Voltage
Output Swing Control
SEL3_[A:D] 0 1 Swing 1x 1.2x
Output De-emphasis Adjustment
SEL5_[A:D] 0 1 De-emphasis 0dB -3.5dB
Equalizer Selection
SEL0_[A:D] 0 1 Compliance Channel [0:3.5dB] @ 1.6 GHz [0:7.5dB] @ 1.6 GHz
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ -65C to +150C Supply Voltage to Ground Potential ................................... -0.5V to +2.5V DC SIG Voltage ..........................................................-0.5V to VDD +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 800mW Operating Temperature .............................................................. 0 to +70C
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver AC/DC Electrical Characteristics (VDD = 1.8 0.1V)
Symbol Ps Parameter Supply Power Latency CML Receiver Input RLRX Return Loss Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage VTHSignal Detect Threshold DC Differential Input ZRX-DIFF-DC Impedance DC Input Impedance ZRX-DC Equalization JRS JRM Residual Jitter(1,2) Random Jitter(1,2) Total Jitter Deterministic jitter 1.5 0.3 0.2 Ulp-p psrms Conditions EN = LVCMOS Low EN = LVCMOS High From input to output Min. Typ. Max. 0.1 0.6 Units W ns
2.0
50 MHz to 1.25 GHz 0.200
12
dB V 150 mV mVp-p
EN_X = High
50 80 40 100 50
200 120 60
Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 x RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of Figure 1.
FR4
Signal Source A B Pericom Re-Driver SmA Connector 30IN SmA Connector In Out C
Figure 1. Test Condition Referenced in the Electrical Characteristic Table
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PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver AC/DC Electrical Characteristics (TA = 0 to 70C)
Symbol Parameter Conditions Min. Typ. Max. Units CML Transmitter Output (100 differential) VDIFFP VTX-DIFFP-P tF, tR ZOUT ZTX-DIFF-DC CTX Output Voltage Swing; | VTX-D+ - VTX-D- | Differential Peak-to-peak Ouput Voltage; VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | Transition Time Output resistance DC Differential TX Impedance AC Coupling Capacitor Differential Swing Swing = 1.0x Swing = 1.2x 20% to 80% (1) Single ended 40 80 75 50 100 Swing = 1.0x Swing = 1.2x 200 250 400 500 375 450 750 900 150 60 120 200 mV ps nF mVp-p
LVCMOS Control Pins VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current 0.65 x VDD VDD 0.35 x VDD 250 500 V
A
Note: 1. Using K28.7 (0011111000) pattern) 2. When 1.0x swing selected 3. When 1.2x swing selected
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PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver AC Switching Characteristics for Clock Buffer (VDD = 1.8 0.1V) (3)
Symbol Trise / Tfall Trise / Tfall VHIGH VLOW VCROSS VCROSS TDC Parameters Rise and Fall Time (measured between 0.175V to 0.525V) Rise and Fall Time Variation Voltage High including overshoot Voltage Low including undershoot Absolute crossing point voltages Total Variation of Vcross over all edges Duty Cycle (input duty cycle = 50%)
(2) (1)
Min 125
Max. 525 75
Units ps
Notes 1 1 1
660 -150 -200 200 45
900 550 250 55 % mV
1 1 1 2
Notes: 1. Measurement taken from Single Ended waveform. 2. Measurement taken from Differential waveform. 3. Test configuration is RS = 33.2, Rp = 49.9, and 2pF.
Configuration Test Load Board Termination
Rs 33 5% TLA CLKBUF Rs 33 5% TLB Rp 49.9 1% Rp 49.9 1% 2pF 5%
Clock
Clock#
2pF 5%
475 1%
Figure 2. Configuration test load board termination
Note: * TLA and TLB are 3" transmission lines.
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PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver Packaging Mechanical: 48-Contact TQFN (ZD48)
DATE: 03/10/06
DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZD (ZD48) DOCUMENT CONTROL #: PD-2045
06-0252
REVISION: A
Ordering Information
Ordering Number PI2EQX3232BZDE Package Code ZD Package Description Pb-free & Green 48-Contact TQFN
Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free and Green * X suffix = Tape/Reel
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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