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P4C164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) - 8/10/12/15/20/25/35/70/100 ns (Commercial) - 10/12/15/20/25/35/70/100 ns(Industrial) - 12/15/20/25/35/45/70/100 ns (Military) Low Power Operation Output Enable and Dual Chip Enable Control Functions Single 5V10% Power Supply Data Retention with 2.0V Supply, 10 A Typical Current (P4C164L Military) Common Data I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) - 28-Pin 300 mil Plastic DIP, SOJ - 28-Pin 600 mil Plastic DIP (70 & 100ns) - 28-Pin 300 mil SOP (70 & 100ns) - 28-Pin 300 mil Ceramic DIP - 28-Pin 600 mil Ceramic DIP - 28-Pin 350 x 550 mil LCC - 32-Pin 450 x 550 mil LCC - 28-Pin CERPACK
DESCRIPTION
The P4C164 is a 65,536-bit ultra high-speed static RAM organized as 8K x 8. The CMOS memory requires no clocks or refreshing and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V10% tolerance power supply. With battery backup, data integrity is maintained with supply voltages down to 2.0V. Current drain is typically 10 A from a 2.0V supply. Access times as fast as 8 nanoseconds are available, permitting greatly enhanced system operating speeds. The P4C164 is available in 28-pin 300 mil DIP and SOJ, 28pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK. The 70ns and 100ns P4C164s are available in the 600 mil plastic DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, P6, C5, C5-1, D5-1, D5-2), SOJ (J5), CERPACK (F4), SOP(S6) SEE PAGE 7 FOR LCC PIN CONFIGURATIONS
1519B
Document # SRAM115 REV F Revised June 2007 1
P4C164
MAXIMUM RATINGS(1)
Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value -0.5 to +7 -0.5 to VCC +0.5 -55 to +125 Unit V Symbol TBIAS TSTG V C PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -55 to +125 -65 to +150 1.0 50 Unit C C W mA
VTERM TA
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade(2) Military Industrial Commercial Ambient Temperature -55C to +125C -40C to +85C 0C to +70C GND 0V 0V 0V VCC 5.0V 10% 5.0V 10% 5.0V 10%
CAPACITANCES(4)
VCC = 5.0V, TA = 25C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF
Output Capacitance VOUT = 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2) Symbol VIH VIL V HC VLC V CD VOL VOH ILI ILO Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage VCC = Min., IIN = -18 mA Output Low Voltage IOL = +8 mA, VCC = Min. (TTL Load) Output High Voltage IOH = -4 mA, VCC = Min. (TTL Load) VCC = Max. Mil. Input Leakage Current VIN = GND to VCC Ind./Com'l. Output Leakage Current VCC = Max., CE = VIH, VOUT = GND to VCC Mil. Ind./Com'l. Test Conditions P4C164 Min Max 2.2 VCC +0.5 -0.5(3) -0.5
(3)
P4C164L Unit Min Max 2.2 VCC +0.5 V -0.5(3) -0.5
(3)
0.8 0.2 -1.2 0.4
0.8 0.2 -1.2 0.4
V V V V V V
VCC -0.2 VCC +0.5 VCC -0.2 VCC +0.5
2.4 -10 -5 -10 -5 ___ ___ +10 +5 +10 +5 40 30
2.4 -5 n/a -5 n/a ___ ___ +5 n/a +5 n/a 40 n/a
A A mA
ISB
Standby Power Supply Current (TTL Input Levels)
CE1 VIH or Mil. CE2 VIL, Ind./Com'l. VCC= Max, f = Max., Outputs Open CE1 VHC or Mil. CE2 VLC, Ind./Com'l. VCC= Max, f = 0, Outputs Open VIN VLC or VIN VHC
ISB1
Standby Power Supply Current (CMOS Input Levels)
___ ___
25 15
___ ___
1 n/a
mA
Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested.
Document # SRAM115 REV F
Page 2 of 16
P4C164
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter Temperature Range Commercial ICC Dynamic Operating Current* Industrial Military -8 -10 -12 -15 -20 -25 -35 45 -70 -100 Unit mA mA mA
200 180 170 160 155 150 145 N/A 130 125 N/A 190 180 170 160 155 150 N/A 145 140 N/A N/A 180 170 160 155 150 145 145 145
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH
DATA RETENTION CHARACTERISTICS (P4C164L, Military Temperature Only)
Symbol V DR ICCDR t CDR tR

Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Test Condition
Min 2.0
Typ.* VCC = 2.0V 3.0V 10 15
Max VCC = 2.0V 3.0V 200 300
Unit V A ns ns
CE1 VCC - 0.2V or CE2 0.2V, VIN VCC - 0.2V or VIN 0.2V tRC 0
*TA = +25C
tRC = Read Cycle Time This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM115 REV F
Page 3 of 16
P4C164
AC ELECTRICAL CHARACTERISTICS--READ CYCLE
(VCC = 5V 10%, All Temperature Ranges)(2)
Symbol tRC tAA tAC Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 2 5 3 -8 -10 -12 -15 -20 -25 -35 -45 -70 -100 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit 8 8 8 10 10 10 12 12 12 15 15 15 20 20 20 25 25 25 35 35 35 45 45 45 70 70 70 100 100 100 ns ns ns
tOH
3
3
3
3
3
3
3
3
3
ns
tLZ
2
2
2
2
2
2
2
2
2
2
ns
tHZ
5
6
7
8
8
10
15
20
35
45
ns
tOE
5
6
7
9
10
13
18
20
35
45
ns
tOLZ tOHZ
2 6
2 7
2 9
2 9
2 12
2 15
2 20
2 35
2 45
ns ns
tPU
0
0
0
0
0
0
0
0
0
ns
tPD
8
10
12
15
20
20
20
25
35
45
ns
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) OE
Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH.
8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested.
Document # SRAM115 REV F
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P4C164
TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10) CE
Notes: 9. READ Cycle Time is measured from the last valid address to the first transitioning address.
10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them.
AC CHARACTERISTICS--WRITE CYCLE
(VCC = 5V 10%, All Temperature Ranges)(2)
Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Date Hold Time Write Enable to Output in High Z Output Active from End of Write 3 -8 -10 -12 -15 -20 -25 -35 -45 -70 -100 Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 8 6 10 7 12 8 15 12 20 15 25 18 35 25 45 33 70 50 100 70 ns ns
7 0 7 0 6 0 6
8 0 8 0 7 0 7
10 0 9 0 8 0 7
12 0 12 0 9 0 7
15 0 15 0 11 0 8
18 0 18 0 13 0 10
25 0 20 0 15 0 14
33 0 25 0 20 0 18
50 0 40 0 30 0 30
70 0 50 0 40 0 40
ns ns ns ns ns ns ns
3
3
3
3
3
3
3
3
3
ns
Document # SRAM115 REV F
Page 5 of 16
P4C164
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(11) WE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(11) CE
Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a high impedance state.
14. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document # SRAM115 REV F
Page 6 of 16
P4C164
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
TRUTH TABLE
Mode Standby Standby DOUT Disabled Read Write CE1 H X L L L CE2 X L H H H OE X X H L X WE X X H H L I/O High Z High Z High Z DOUT High Z Power Standby Standby Active Active Active
Figure 1. Output Load
* including scope and test fixture. Note: Because of the high speed of the P4C164/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal reflections,
Figure 2. Thevenin Equivalent
proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with DOUT to match 166 (Thevenin Resistance).
LCC PIN CONFIGURATIONS
LCC (L5) "L" - STANDARD PIN-OUT
LCC (L5) "LS" - SPECIAL PIN-OUT
LCC (L6)
Document # SRAM115 REV F
Page 7 of 16
P4C164
ORDERING INFORMATION
SELECTION GUIDE
The P4C164 is available in the following temperature, speed and package options. The P4C164L is available only over the military temperature range.
Te m pe ra ture Ra nge Commercial Spe e d (ns) Pa cka ge Plastic DIP (300 mil) Plastic DIP (600 mil) Plastic SOJ Plastic SOP Industrial Plastic DIP (300 mil) Plastic DIP (600 mil) Plastic SOJ Plastic SOP 8 -8PC N/A -8JC N/A N/A N/A N/A N/A 10 -10PC N/A -10JC N/A -10PI N/A -10JI N/A 12 -12PC N/A -12JC N/A -12PI N/A -12JI N/A 15 -15PC N/A -15JC N/A -15PI N/A -15JI N/A 20 -20PC N/A -20JC N/A -20PI N/A -20JI N/A 25 -25PC N/A -25JC N/A -25PI N/A -25JI N/A 35 -35PC N/A -35JC N/A -35PI N/A -35JI N/A 45 N/A N/A N/A N/A N/A N/A N/A N/A 70 N/A -70P6C N/A -70SNC N/A -70P6I N/A -70SNI 100 N/A -100P6C N/A -100SNC N/A -100P6I N/A -100SNI
N/A = Not available
Document # SRAM115 REV F
Page 8 of 16
P4C164
SELECTION GUIDE (continued)
Temperature Range Military Temperature Package Side Brazed DIP CERDIP (300 mil) CERDIP (600 mil) CERPACK 28-Pin LCC 28-Pin LCC ** 32-Pin LCC Military Processed * Side Brazed DIP CERDIP (300 mil) CERDIP (600 mil) CERPACK 28-Pin LCC 28-Pin LCC ** 32-Pin LCC Speed (ns) 8 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 10 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 12 -12CM -12DM -12DWM -12FM -12LM -12LSM -12L32M -12CMB -12DMB -12DWMB -12FMB -12LMB -12LSMB -12L32MB 15 -15CM -15DM -15DWM -15FM -15LM -15LSM -15L32M -15CMB -15DMB -15DWMB -15FMB -15LMB -15LSMB -15L32MB 20 -20CM -20DM -20DWM -20FM -20LM -20LSM -20L32M -20CMB -20DMB -20DWMB -20FMB -20LMB -20LSMB -20L32MB 25 -25CM -25DM -25DWM -25FM -25LM -25LSM -25L32M -25CMB -25DMB -25DWMB -25FMB -25LMB -25LSMB -25L32MB 35 -35CM -35DM -35DWM -35FM -35LM -35LSM -35L32M -35CMB -35DMB -35DWMB -35FMB -35LMB -35LSMB -35L32MB 45 -45CM -45DM -45DWM -45FM -45LM -45LSM -45L32M -45CMB -45DMB -45DWMB -45FMB -45LMB -45LSMB -45L32MB 70 -70CM -70DM -70DWM -70FM -70LM -70LSM -70L32M -70CMB -70DMB -70FMB -70LMB 100 -100CM -100DM -100DWM -100FM -100LM -100LSM -100L32M -100CMB -100DMB -100FMB -100LMB
-70DWMB -100DWMB
-70LSMB -100LSMB -70L32MB -100L32MB
* Military temperature range with MIL-STD-883, Class B processing. ** SPECIAL PINOUT N/A = Not available
Document # SRAM115 REV F
Page 9 of 16
P4C164
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2
C5
28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 -
SIDE BRAZED DUAL IN-LINE PACKAGE (300 mils)
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2
C5-1
28 (600 mil) Min Max 0.232 0.014 0.026 0.045 0.065 0.008 0.018 1.490 0.500 0.610 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 -
SIDE BRAZED DUAL IN-LINE PACKAGE (600 mils)
Document # SRAM115 REV F
Page 10 of 16
P4C164
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1
D5-1
28 (600 mil) Min Max 0.232 0.014 0.026 0.045 0.065 0.008 0.018 1.490 0.500 0.610 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0 15
CERDIP DUAL IN-LINE PACKAGE
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1
D5-2
28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0 15
CERDIP DUAL IN-LINE PACKAGE
Document # SRAM115 REV F
Page 11 of 16
P4C164
Pkg # # Pins Symbol A b c D E e k L Q S S1
F4
28 Min Max 0.060 0.090 0.015 0.022 0.004 0.009 0.730 0.330 0.380 0.050 BSC 0.005 0.018 0.250 0.370 0.026 0.045 0.085 0.005 -
CERPACK CERAMIC FLAT PACKAGE
Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q
J5
28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 -
SOJ SMALL OUTLINE IC PACKAGE
Document # SRAM115 REV F
Page 12 of 16
P4C164
Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE
L5
28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9
RECTANGULAR LEADLESS CHIP CARRIER
Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE
L6
32 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.442 0.458 0.300 BSC 0.150 BSC 0.458 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 7 9
RECTANGULAR LEADLESS CHIP CARRIER
Document # SRAM115 REV F
Page 13 of 16
P4C164
Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L
P5
28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0 15
PLASTIC DUAL IN-LINE PACKAGE (300 mils)
Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L
P6
28 (600 mil) Min Max 0.090 0.200 0.000 0.070 0.014 0.020 0.015 0.065 0.008 0.012 1.380 1.480 0.485 0.550 0.600 0.625 0.100 BSC 0.600 TYP 0.100 0.200 0 15
PLASTIC DUAL IN-LINE PACKAGE (600 mils)
Document # SRAM115 REV F
Page 14 of 16
P4C164
Pkg # # Pins Symbol A A1 B C D e E H L
S6
28 (300 mil) Min Max 0.090 0.110 0.003 0.010 0.012 0.020 0.004 0.012 0.700 0.716 0.050 BSC 0.290 0.300 0.465 0.485 0.016 0.050 0 9
SOIC/SOP SMALL OUTLINE IC PACKAGE (SN)
Document # SRAM115 REV F
Page 15 of 16
P4C164
REVISIONS
DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B C D E F ISSUE DATE 1997 Oct-05 Jun-06 Aug-06 Aug-06 Aug-06 Jun-07 SRAM115
P4C164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS
ORIG. OF CHANGE DAB JDB JDB JDB JDB JDB JDB
DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Added 28-pin ceramic DIP Added Lead Free Designation Added "LS" - SPECIAL PIN-OUT Updated SOJ package information Corrected SOP package details
Document # SRAM115 REV F
Page 16 of 16

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