View ICS843242AG_4145127.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843242
GENERAL DESCRIPTION
The ICS843242 is a 2 differential output LVPECL Synthesizer designed to generate Ether net HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. Using a 31.25MHz or 26.041666MHz, 18pF parallel resonant crystal, the follow-ing frequencies can be generated based on the settings of 4 frequency select pins (SEL[A1:A0], SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and 125MHz.
FEATURES
* Two 3.3V differential LVPECL output pairs * Using a 31.25MHz or 26.041666 crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz * Crystal oscillator interface * VCO range: 560MHz to 700MHz * RMS phase jitter @ 625MHz (1.875MHz - 20MHz): 0.4ps (typical) * Full 3.3V supply mode * 0C to 70C ambient operating temperature * Industrial temperature available upon request * Available in both standard (RoHS 5) and lead-free (RoHS 6) compliant packages
IC S
The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS843242 IDT's 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843242 is packaged in a small 16-pin TSSOP package.
BLOCK DIAGRAM
0=Pullup
PIN ASSIGNMENT
00 01 10 11 00 01 10 11 /1 /2 (default) /4 /5 /1 /2 /4 (default) /5
SELA[0:1} 1=Pulldown 2 QA nQA nQB QB VCCO_B SELB1 SELB2 VCCO_A QA nQA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XTAL_IN XTAL_OUT VEE SELA1 SELA0 VCC VCCA FB_SEL
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
560MHz - 700MHz
QB nQB
Feedback Divider 0 = /20 (default) 1 = /24
ICS843242
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
FB_SEL Pulldown SELB[0:1} 1=Pullup
0=Pulldown
2
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
1, 2 3 4 5 6 7, 8 9 10 11 12 13 14 nQB, QB VCCO_B SELB1 SELB0 VCCO_A QA, nQA FB_SEL VCCA VCC SELA0 SELA1 Power Input Input Power Output Input Power Power Input Input Pulldown Output Differential clock outputs. LVPECL interface levels. Output supply pin for QB, nQB outputs. Division select pin for Bank B. Default = High. Pullup LVCMOS/LVTTL interface levels. Division select pin for Bank B. Default = Low. Pulldown LVCMOS/LVTTL interface levels. Output supply pin for QA, nQA outputs. Differential clock outputs. LVPECL interface levels. Feedback divide select. When Low (default), the feedback divider is set for /20. When HIGH, the feedback divider is set for /24. LVCMOS/LVTTL interface levels. Analog supply pin.
Power VEE XTAL_OUT, Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 15, 1 6 Input XTAL_IN NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Core supply pin. Division select pin for Bank A. Default = HIGH. Pullup LVCMOS/LVTTL interface levels. Division select pin for Bank A. Default = Low. Pulldown LVCMOS/LVTTL interface levels. Negative supply pin.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 3A. BANK A FREQUENCY TABLE
Inputs Crystal Frequency 31.25 31.25 31.25 31.25 26.041666 26.041666 26.041666 26.041666 SELA1 0 0 1 1 0 0 1 1 SELA0 0 1 0 1 0 1 0 1 FB_SEL 0 0 0 0 1 1 1 1 Feedback Divider 20 20 20 20 24 24 24 24 Bank A Output Divider 1 2 4 5 1 2 4 5 M/N Multiplication Factor 20 10 5 4 24 12 6 4.8 QA/nQA Output Frequency 625 312.5 156.25 125 625 312.5 156.25 125
TABLE 3B. BANK B FREQUENCY TABLE
Inputs Crystal Frequency 31.25 31.25 31.25 31.25 26.041666 26.041666 26.041666 26.041666 SELA1 0 0 1 1 0 0 1 1 SELA0 0 1 0 1 0 1 0 1 FB_SEL 0 0 0 0 1 1 1 1 Feedback Divider 20 20 20 20 24 24 24 24 Bank B Output Divider 1 2 4 5 1 2 4 5 M/N Multiplication Factor 20 10 5 4 24 12 6 4.8 QB/nQB Output Frequency 625 312.5 156.25 125 625 312.5 156.25 125
TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs SELA1 0 0 1 1 SELA0 0 1 0 1 Outputs QA /1 /2 (default) /4 /5 SELB1 0 0 1 1 Inputs SELB0 0 1 0 1 Outputs QB /1 /2 /4 (default) /5
TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE
Inputs FB_DIV 0 1 Feedback Divide /20 (default) /24
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 92.4C/W (0 mps)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_A, VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO_A, VCCO_B IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VCC - 0.12 3.135 Typical 3.3 3.3 3.3 125 12 Maximum 3.465 VCC 3.465 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current FB_SEL, SELA1, SELB0 SELA0, SELB1 FB_SEL, SELA1, SELB0 SELA0, SELB1 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO_X - 1.4 VCCO_X - 2.0 0.6 Typical Maximum VCCO_X - 0.9 VCCO_X - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO_X - 2V.
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency FB_SEL = /20 FB_SEL = /24 28 23.33 Test Conditions Minimum Typical Fundamental 31.25 26.04166 35 29.167 50 7 1 MHz MHz pF mW Maximum Units
Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCO_A, VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions Output Divider = /1 fOUT Output Frequency Range Output Divider = /2 Output Divider = /4 Output Divider = /5 tsk(o) Output Skew; NOTE 1, 3 Outputs @ Same Frequency Outputs @ Different Frequencies 625MHz (1.875MHz - 20MHz) tjit(O) RMS Phase Jitter (Random); NOTE 2 Output Rise/Fall Time 312.5MHz (1.875MHz - 20MHz) 156.25MHz (1.875MHz - 20MHz) 125MHz (1.875MHz - 20MHz) t R / tF 20% to 80% Minimum 490 245 122.5 98 20 30 0.4 0.5 0.5 0.6 300 Typical Maximum 680 340 170 136 Units MHz MHz MHz MH z ps ps ps ps ps ps ps % %
SELx[1:0] = 00 50 odc Output Duty Cycle SELx[1:0] 00 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 2: Please refer to the Phase Noise Plots. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
5
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TYPICAL PHASE NOISE AT 625MHZ
625MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.4ps (typical)
Ethernet Filter
NOISE POWER dBc Hz
Raw Phase Noise Data
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER 6
Phase Noise Result by adding an Ethernet Filter to raw data OFFSET FREQUENCY (HZ)
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V 2V nQx Qx nQy
nQx VEE
VCC, VCCO_A. _B VCCA
Qx
SCOPE
LVPECL
Qy
tsk(o)
-1.3V0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
Noise Power
Phase Noise Mask
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQA, nQB QA, QB
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
7
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843242 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, VCCO_A and VCCO_B should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843242 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 31.25MHz or 26.041666MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
8
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
9
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
RTT =
1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
Zo = 50 84 84
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
10
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843242. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843242 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 125mA = 433mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 433mW + 60mW = 493mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92.4C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.493W * 92.4C/W = 115.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA
FOR
16-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 92.4C/W
1
88.0C/W
2.5
85.9C/W
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
11
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination
voltage of V * - 2V.
CCO
For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (VCCO_MAX - VOH_MAX) = 0.9V
*
For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) =
L L
[(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
L L
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
12
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 92.4C/W
1
88.0C/W
2.5
85.9C/W
TRANSISTOR COUNT
The transistor count for ICS843242 is: 3751
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
13
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
14
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS843242AG 843242AG 16 Lead TSSOP tube 0C to 70C ICS843242AGT 843242AG 16 Lead TSSOP 2500 tape & reel 0C to 70C ICS843242AGLF TBD 16 Lead "Lead-Free" TSSOP tube 0C to 70C ICS843242AGLFT TB D 16 Lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT TM / ICSTM 3.3V LVPECL FREQUENCY SYNTHESIZER
15
ICS843242AG REV. A OCTOBER 2, 2007
ICS843242 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
netcom@idt.com 480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851
(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

▲Up To Search▲

Price & Availability of ICS843242AG

	To Download ICS843242AG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .