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ASAHI KASEI
[AK8856VN ]
AK8856VN
NTSC/PAL Video Decoder
General Description
The AK8856 decodes NTSC or PAL composite video signals into digital video data. The outputs are ITU-R BT. 601 level compatible Y, Cb and Cr signals. The decoded result is scaled to 601, VGA (interlaced output), CIF, QVGA, QCIF, rotated QVGA , or rotated CIF(progressive). Information including closed caption, VBID, and WSS are encoded in the video signal can be read out externally. The AK8856 is controlled by through an I2C interface.
Features
* * * * * * * * NTSC-M, NTSC-4.43 / PAL- B, D, G, H, I, N, Nc, M, 60 composite signal decoding process 10 Bit ADC (sampling at 24.5454MHz or 27MHz) Integrated PGA (0dB ~ 12dB) Automatic color control (ACC) function Adaptive automatic gain control (AGC) function 1D or 2D YC separation Phase compensation for PAL Output interface - ITU-R BT.656 output format (4:2:2 8-bit parallel output with EAV / SAV) - Camera interface - Interface with HD / VD / DVALID signals Closed caption decoding function (read by register setting) VBID (CGMS-A) decoding function (CRCC decode) (read by register setting) WSS decoding function (read by register setting) Macrovision signal detect function Power-down function 2-channel analog input selector I2C control compatible Core voltage (AVDD, DVDD) 1.65 - 1.8V I/O voltage (PVDD) 1.65 - 3.3V Package: 48 QFN or 41 BGA (see VG datasheet)
* * * * * * * * * *
* The output that meets the ITU-R BT.656 standard according to the fineness of the input signal might not be available.
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Block Diagram
XTI XTO LPF SCL SDA PDN RSTN OE
27MHz Clock GEN PLL 27MHz -> 27.0000MHz or 24.5454MHz 27 or 24.5454MHz I2C bus uC Interface Register DATA[7:0] HD/HV Output Buffer VD/VAF/FIELD DVALID NSIG DTCLK AIN1 AIN2 MUX CLAMP PGA
10-bit ADC
CLKMOD
Decimation Filter
SYNC-Separation AGC Ctrl VBI Info Timing Controller Timing
Y Cb Cr
YC Sep 2D/1D
Y
Luminance Processor
Y Scaling (640 -> 320) (720 -> 58) U Decimation Filter Pixel Interpolator
C
Chrominance Processor
V
VREF
VRP VCOM VRN IREF
AVDD
AVSS
PVDD
PVSS
DVDD
DVSS
TEST0 TEST1 TEST2
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ASAHI KASEI
[AK8856VN]
Ordering Guide
AK8856VN 48-pin QFN
Pin Layout Drawing
CLKMOD
VCOM
DVSS
IREF
AIN1
VRN
XTO
VRP
LPF
XTI
NC
NC NC AVDD AVSS AIN2 DVSS DVDD NSIG MACDET DVALID NC NC
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 3 4 5 6 7 8 9 10 11 48 QFN (TOP VIEW) 35 34 33 32 31 30 29 28 27 26
25 12 13 14 15 16 17 18 19 20 21 22 23 24 NC VD/VAF/FIELD HD/HV DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 NC
NC
NC TEST0 PDN DVDD RSTN OE SCL PVDD SDA DTCLK TEST1 NC
Bottom View
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[AK8856VN]
Pin Description
Pin Name
NC NC AVDD AVSS AIN2 DVSS DVDD NSIG TEST2 DVALID NC NC NC A A A D D P P P P G I G P O I/O O
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13
A/D/P
I/O
Functional Outline
No connection - leave floating - Reserved for AKM testing No connection - leave floating - Reserved for AKM testing Analog power supply Analog ground Analog input pin (2) ; if not used, leave floating Digital ground pins Digital power supply Indicates synchronization condition with input signal - L : synchronized with input signal - H : no signal input or out of synchronization - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1 Reserved - leave floating Valid video interval - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1) No connection - leave floating - Reserved for AKM testing No connection - leave floating - Reserved for AKM testing No connection - leave floating - Reserved for AKM testing VD/VAF/FIELD timing signal output - selection of VD/VAF signal output and FIELD signal output is determined by register setting - in camera I/F mode, VAF signal is always output - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1) - this pin is used as an I/O pin in test mode HD/HV timing signal output - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1) Data output (MSB) - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1) - this pin is used as an I/O pin in test mode Data output - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1) Data output - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1) - this pin is used as an I/O pin in test mode Data output pin - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1) Data output - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1) - this pin is used as an I/O pin in test mode Data output pin - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1)
14
VD/VAF /FIELD
P
I/O
15 16 17 18 19 20 21
HD/HV DATA7 DATA6 DATA5 DATA4 DATA3 DATA2
P P P P P P P
O I/O O I/O O I/O O
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[AK8856VN]
22 23 24 25 26
DATA1 DATA0 NC NC TEST1
P P
I/O O
P
I
27
DTCLK
P
I/O
28
SDA
P
I/O
29
PVDD
P
P
30
SCL
P
I
31
OE
P
I
32 33 34
RSTN DVDD PDN
P D P
I P I
35 36 37
TEST0 NC NC
P
I
38
XTO
D
O
39 40
DVSS XTI
D D
G I
Data output - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1) - this pin is used as an I/O pin in test mode Data output pin ( LSB ) - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1) No connection - leave floating - Reserved for AKM testing No connection - leave floating - Reserved for AKM testing Test mode 1 - connect this pin to DVSS (internally pulled-down) Data clock for output interface - output state is separately controlled by combinations of RSTN/PDN/OE pin settings (note 1) - this pin is used as an I/O pin in test mode I2C data - this pin is pulled-up to PVDD - Hi-Z input is allowed when PDN is low - SDA input is not accepted during reset operation Power supply for interface - interface power supply for DTCLK, OE, PDN, RSTN, DATA[7:0], HD/HV, VD/VAF/FIELD, NSIG, DVALID, SDA, SCL. I2C clock input - an input level below PVDD should be input - Hi-Z input is allowed when PDN is low - SCL input is not accepted during reset operation Output enable - L : digital output pins are at high-Z - H : data is available for output - Hi-Z input on OE pin is prohibited Reset signal input - Hi-Z input to this pin is prohibited - L: reset - H: normal operation Digital power supply Power-down control - Hi-Z input to this pin is prohibited - L: power-down - H: normal operation Test mode 0 - connect this pin to DVSS (internally pulled-down) No connection - leave floating - Reserved for AKM testing No connection - leave floating - Reserved for AKM testing Quartz crystal oscillator connection (tie to digital ground via a 22pF capacitor) - 27.00 MHz crystal oscillator should be used. - this pin outputs DVSS level when PDN = L. - when a crystal oscillator is not used, this pin can either be left open (NC) or connected to DVSS Digital ground pins Quartz crystal oscillator connection (tie to digital ground via a 22pF capacitor) - 27.00 MHz crystal oscillator should be used
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[AK8856VN]
41
CLKMOD
D
I
42
VRN
A
I/O
43
VRP
A
I/O
44
IREF
A
I/O
45
VCOM
A
I/O
46 47 48
LPF AIN1 NC
A A
I/O I
- input from 27.00 MHz crystal oscillator is connected to this pin Clock mode set: connect to either DVDD (high) or DVSS (low) - Low setting: crystal oscillator is used - High setting: external clock source is used Internal negative reference voltage for ADC - connect this pin to analog ground through a 0.1uF or larger capacitor - this pin may go to high-Z in power-down mode (no high-Z test is performed in production test) - do not use this as a reference voltage source for external circuitry Internal positive reference voltage for ADC - connect this pin to analog ground through a 0.1uF or larger capacitor - there is a case when this pin becomes Hi-Z output at power-down ( no Hi-Z test is performed in mass-production test ) - do not use this pin as a reference voltage source for external circuit. Reference current setting - connect this pin to analog ground through a 6.8k resistor (1% accuracy) - this pin goes to high-Z in power-down mode (no high-Z test is performed in production test) Internal common voltage for AD converter - connect this pin to analog ground via a 0.1 uF or larger capacitor. - there is case when this pin becomes Hi-Z output at power-down (no Hi-Z test is performed in mass-production test ). - do not use this pin as a reference voltage source for external circuit. I/O for analog test - connect this pin to AVSS for normal operation Analog input pin (1) ; if not used, leave floating No connection - leave floating - Reserved for AKM testing
A/D/P A: AVDD, D: DVDD, P: PVDD I/O I: Input pin, O: Output pin, I/O Input/Output pin Note 1 ) Output pin conditions are determined by setting PDN and OE pins
OE PDN RSTN Output1* Output2*
L H H
x L H
x x L
Hi-Z output L output L output
L output L output L output
H Dataout(*1) Dataout(*1) Output1*: DATA[7:0], HD/HV, VD/VAF/FIELD, DVALID, DTCLK Output2*: NSIG, MACDET Output pin conditions immediately following power-on are indeterminate, except at OE = "L" (*1 ) With no analog input signal, black level data (Y = 0x10, Cb/Cr = 0x80) is output in decoder mode operation
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[AK8856VN]
Electrical Characteristics
(1) Absolute Maximum Ratings Parameter Supply voltage DVDD, AVDD PVDD Analog input voltage (VinA) Clock input voltage (Vckin) Digital Input voltage 1 (VinD) Digital input voltage 2 (VinP) Input current (Iin) Storage temperature Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -10 -40 Max 2.3 4.3 AVDD + 0.3 DVDD + 0.3 DVDD + 0.3 PVDD + 0.3 10 125 Units V V V V V V mA C XTI CLKMOD OE,PDN,RSTN, SDA, SCL Note
Power supply voltages are values where each ground pin (DVSS = AVSS = PVSS) is at 0V All power supply ground pins (DVSS, AVSS and PVSS) should be at the same potential When connecting digital output pins (DTCLK,DATA[7:0], HD/HV,VD/VAF/FIELD, NSIG, DVALID) to the data bus, the data bus operating voltage must be within the input pin voltage range as described above
(2) Recommended Operating Conditions Parameter
Supply voltage * AVDD,DVDD Interface power supply PVDD Operating temperature (Ta)
Min
1.65 1.65 -30
Typ.
1.8 1.8
Max
2.0 3.3 85
Units
V V C
Conditions
AVDD=DVDD PVDD>=DVDD
* Power supply voltages are values where each ground pin (PVSS = AVSS = PVSS) is at 0 V (voltage reference ) All power supply ground pins (DVSS, AVSS and PVSS) should be at the same potential
(3) DC Characteristics operating voltage: PVDD =DVDD1.65~2.0V, temperature -30~+85C Parameter
Digital input H voltage (VIH) Digital input1 L voltage (VIL) Digital input leak current Digital output H voltage (VOH) Digital output L voltage (VOL) I2C (SDA) L output
Symbol
VIH VIL IL VOH VOL VOLC
Min
0.8PVDD
Typ
Max
Units
V
Conditions
0.2PVDD 10 0.7PVDD 0.3PVDD 0.3PVDD
V uA IOH = -600uA IOL = 1mA V IOLC = 3mA
Digital output pins refer to DTCLK, DATA[7:0], HD/HV, VD/VAF/FIELD, NSIG, DVALID pin outputs in general terms Digital input pins refer to OE, PDN, RSTN, SCL, SDA pin outputs in general terms SDA output is not included as a digital output pin unless otherwise noted
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ASAHI KASEI
[AK8856VN]
(4) Analog Characteristics (AVDD = 1.8 V, temperature 25C)
Selector Clamp Parameter
Maximum input range Clamp current
Symbol
VIMX CLPI UDCLP
Min
0
Typ
0.64 120 40
Max
0.75
Units
VPP uA
Conditions
PGA_GAIN (minimum setting) FINE clamp (default) UP/DN clamp (default)
PGA Parameter
Resolution Minimum gain Maximum gain Gain step
Symbol
GMN GMX GST
Min
Typ
7 0 12 0.094
Max
Units
bit dB dB dB
Conditions
0.235
A/D Converter Parameter
Resolution Operating clock frequency Integral non-linearity error Differential non-linearity error S/N S/(N+D) ADC internal common voltage ADC internal positive-side VREF voltage ADC internal negative-side VREF voltage
Symbol
RES FS INL DNL SN SND VCOM VRP VRN
Min
10
Typ
24.5454 27 2.0 1.0 50 48 0.8 1.0 0.6
Max
Units
bits MHz
Conditions
4.0 2.0
LSB LSB dB dB V V V
fs=27MHz, PGA_GAIN (default) fs=27MHz, PGA_GAIN (default) fin=1MHz, fs=27MHz PGA_GAIN (default) fin=1MHz, fs=27MHz PGA_GAIN (default)
AAF (Anti Aliasing Filter) Parameter
Passband ripple Stopband attenuation
Symbol
Gp Gs
Min
-1
Typ
Max
1
Units
dB dB 6MHz 27MHz
Conditions
-24
-12
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[AK8856VN]
(5) Current consumption (DVDD = AVDD = PVDD = 1.8V, Ta = -30 ~ +85C) Parameter
Operating power supply current Total current consumption Analog section: Digital section: Interface section: Power-down current (digital + analog) Analog section: Digital section: Interface section:
Symb ol
Min
Typ
33 17 12 4 <=1 <=1 <=1 <=1
Max
43
Units
mA mA mA mA uA uA uA uA Note1)
Conditions
Crystal oscillator connection Load capacitor CL=15pF
20
Note 1) Input / Output signal : Measured with 100 % Color Bar signal. Decoder power supply current is measured in 601 output mode (internal clock operation at 27MHz) and 2D YC Separation Mode
( 6 ) Quartz Crystal Oscillator circuit Quartz crystal resonator and externally connecting load capacitance < Ta = -30 ~ +85C > Parameter
Oscillating frequency Frequency accuracy Load capacitance Effective equivalent resistance Parallel capacitance
Symbol
f0 Delta f / f CL Re C0
Min
Typ
27.000
Max
Units
MHz
Conditions
+/-100 15 100 0.85
ppm pF pF note1
XTI pin externally connecting CXI 22 pF load capacitance XTO pin externally connecting CXO 22 pF load capacitance 2 note 1) effective equivalent resistance is generally given as: Re = R1 x ( 1 + CO / CL ) ,where R1 = serial equivalent resistance of crystal oscillator and CO = parallel capacitance of crystal oscillator
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ASAHI KASEI
[AK8856VN]
Circuit connection example
AK8856
XTI
XTO Rd
External connection circuit
CXI =22pF
CXO =22pF
Note) Refer to the quartz crystal oscillator section for the value of the limiting resistor Rd
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ASAHI KASEI
[AK8856VN]
AC Timing
(DVDD = PVDD = 1.65V, Ta at -30 ~ +85C) Load condition: CL = 15pF
(1) CLK Clock conditions (CLKMOD = 1: external clock mode)
fC L K tC L K L tC L K H 0 .8 D V D D 1 /2 L e ve l o f 0 .8 P V D D a n d 0 .2 P V D D 0 .2 D V D D
Parameter
CLK CLK duty ratio Frequency stability
Symbol
fCLK pCLKD
Min
Typ
27.00
Max
Unit
MHz
40
60 100
% ppm
(2) Clock specification (DTCLK output) Operating mode
QVGA / Rotate QVGA / Rotated CIF MHz CIF(PAL), QCIF VGA CIF(NTSC)/601
Parameter
Symbol
Min.
Typ.
12.2727
Max
Unit
DTCLK
fDTCLK
13.5 24.5454 27
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[AK8856VN]
(3) Output Data Timing All output signals except for NSIG and TESTFLG, and MACFLG outputs
CLKINV-bit = 0(Register Setting) DTCLK tDS tDH 1/2PVDD
Output signal
0.7PVDD 0.3PVDD
CLKINV-bit=1(Register Setting) DTCLK tDS tDH 1/2PVDD
Output signal
0.7PVDD 0.3PVDD
Parameter
Output Data Setup Time Output Data Hold Time
Symbol
tDS tDH
Min
10 10
Typ
Max
Unit
nsec nsec
Conditions
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[AK8856VN]
(4) Reset Timing (Register reset)
RSTN
VIL
pRES
CLK
Parameter
RSTN pulse width
Symbol
pRES
Min
100
Typ
Max
Unit
CLK
Conditions
Rising Clock Edge
Note) clock input is required for reset. Set RSTN pin low after the clock is present.
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ASAHI KASEI
[AK8856VN]
(5) Power-down sequence and reset sequence after power-down release Activate reset for longer than 1024 clock cycles before setting PDN (PDN to low) Activate reset after PDN release (PDN to high)
CLKIN
***********
sRES
RSTN
hRES
VIH VIL
PDN GND
VIH
Parameter
RSTN pulse width Time from PDN to high to RSTN to high
Symbol
sRES hRES
Min
1024 10
Typ
Max
Unit
SYSCLK msec
During power-down, all control signals must be connected to either the selected power supply or ground, and not to ViH / ViL levels. When turning off power supplies (AVDD / DVDD) other than PVDD, place the AK8856 into power down mode. Note ) Clock input is required for reset operation
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ASAHI KASEI
[AK8856VN]
(6) Power-On-Reset At power-on, reset must be enabled until the analog reference voltage and current are stabilized. Power-on operation must be initiated with either simultaneous power-on of PVDD / AVDD / DVDD or PVDD first and then AVDD / DVDD
AVDD DVDD PVDD RSTN
1.65V
0.2PVDD VREF
raise RSTN to high after VREF voltage is stabilized >= 10 mS (min.)
Parameter
RESETN pulse width
Symbol
pRES_PON
Min
10
Typ
Max
Unit
msec
Conditions
Note) clock input is required for reset operation
(7) I2C bus input / output timing (DVDD = PVDD 1.65 V ~ 2.0V, Ta = -30 ~ +85C) (7-1) Timing 1
tBUF SDA tF SCL tLOW tSU:STA tHD:STA tR tF tSU:STO 0.8PVDD 0.2PVDD
tR
0.8PVDD 0.2PVDD
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[AK8856VN]
Parameter
Bus free time Hold time (start condition) Clock pulse low time Input signal rise time Input signal fall time Setup time (start condition) Setup time (stop condition)
2 2
Symbol
tBUF tHD:STA tLOW tR tF tSU:STA tSU:STO
Min
1.3 0.6 1.3
Max
Unit
usec usec usec
300 300 0.6 0.6
nsec nsec usec usec
I C bus related timing is established by the I C Bus Specification, and it is not limited by the device performance. For details, please refer to the I C Bus Specification.
2
(7-2) Timing 2
tHD:DAT
SDA tHIGH
0.8PVDD 0.2PVDD
SCL tSU:DAT
0.8PVDD 0.2PVDD
Parameter
Data Setup Time Data Hold Time Clock Pulse High Time
2
Symbol
tSU:DAT tHD:DAT tHIGH
Min
100 (note1) 0.0 0.6
Max
0.9 (note2)
Unit
nsec usec usec
note 1) when operating in I C Bus Standard mode, tSU:DAT 250 ns must be met note 2) when the AK8856 is used in a bus interface where tLOW is not extended (at minimum specification of tLOW), this condition must be met.
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[AK8856VN]
Functional Outline
(1) Clock Connect a 27MHz crystal or a 27MHz clock source. Internal operating clock rates are: 24.5454 MHz for VGA / QVGA / rotated QVGA size / rotated CIF size outputs 27 MHz for 601 pixel mode, CIF / QCIF 24.5454 MHz clock is generated by an internal PLL. Although the clock is asynchronous with the input signal, vertical position is aligned since the Digital Pixel Interpolator is integrated. (2) Analog Interface The AK8856 accepts composite video signals. (3) Input Signal NTSC-M, PAL-B, -D, -G, -H, -I compatible composite video signals are accepted as input signals. (4) Analog Input Signal Processing An anti-aliasing filter is integrated. PGA 0 dB ~ 12 dB (approximately 0.1 dB / step) ADC operates at either 24.5454 MHz or 27.00 MHz (5) Clamp Processing Sync-tip clamping is processed in the analog block and digital pedestal clamping is processed in the digital signal processing block. (6) Adaptive AGC Function Based on the difference between the sync-tip level and the pedestal level, the input signal value is corrected to a proper level. A video signal level gain adjust function is applied if only the video signal is larger. (7) ACC Function Based on the color burst level, the input color signal level is corrected to a proper level. (8) Y / C Separation Function Choice of either primary Y / C separation or two dimensional Y / C separation is available. Mode setting of Y / C separation is done through register settings. (9) Pixel Interpolator The AK8856 has an integrated Digital Pixel Interpolator to align the output pixels' vertical position. No line-synchronized clock is required. (10) Picture Quality Adjustment Function Adjustments of contrast, brightness, color hue and color saturation levels are available. (11) Output Interface Outputs are ITU-R BT.601 compatible signal levels (with limit ON / OFF) Output formats include: - Camera interface - ITU-R BT.656-like output* - Active video region is indicated by HD / VD (FIELD) / DVALID
* With SAV/EAV, 27MHz The number of clocks from EAV to SAV becomes irregular.
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[AK8856VN]
(12) Variable Frame-Rate Function * Frame rates of 30 / 15 / 7.5 frames per second are selectable for NTSC video * Frame rates of 25 / 12.5 / 6.75 frames per second are selectable for PAL video (13) Output Picture Size - VGA (640 X 480 - interlaced output) - QVGA (320 X 240) - CIF (352 X 288) - QCIF (176 X 144) - 601 (NTSC: 720 X 480 / PAL: 720 X 576 - interlaced output) - rotated QVGA (240 X 180) - rotated CIF (288 X 216) (14) Other Functions - Black level signal (Y = 16, Cb / Cr = 128) is output in self-operating mode when no input signal is present (Blue back output is also possible) - No signal input detection function - I2C host interface - Power-down function - Decoding function for closed caption, VBID (CGMS-A 525 line), WSS signal (625 line signal). CRCC added to CGMS-A is decoded by the AK8856.
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[AK8856VN]
Input Signal
The AK8856 is designed to decode the following video signals: - NTSC - PAL-B, -D, -G, -H, -I.
Those input signal types are set by Input Video Standard Register (R/W) [ Sub Address 0x00].
The input signal is converted into digital code as follows: Clamp Block ---- Anti-aliasing Filter ---- PGA Block ---- ADC Block Then the digitized signal is processed in digital block.
Settings of the Input Video Standard Register ( R/W ) [ Sub Address 0x00 ] is described here. This register sets the input signal attributes. Sub Address 0x00
bit 7 Reserved 0 bit 6 Reserved 0 bit 5 Reserved 0 bit 4 bit 3 AINSEL VLF Default Value 0 0 bit 2 VCEN 0
Default Value : 0x00
bit 1 VSCF1 0 bit 0 VSCF0 0
[VSCF1 : VSCF0]-bit The input signal sub-carrier frequency is set by the [VSCF1 : VSCF0] bits. [VSCF1:VSCF0]-bit Sub-carrier frequency (MHz)
[00] [01] [10] [11] 3.57954545 3.57561188 3.582054 4.43361875
Conditions
NTSC PAL-B,D,G,H,I
[VCEN]-bit The input signal Color Encoding system is set by the [VCEN]-bit. [VCEN]-bit Color Encoding system
0 1 NTSC PAL
Conditions
[VLF]-bit The number of lines per each Frame of the input signal is set by the [VLF] bit. [VLF]-bit Number of lines Conditions 0 525 lines 1 625 lines [AINSEL]-bit The input signal is selected by the [AINSEL] bit. [AINSEL]-bit Input signal 0 AIN1 input is selected 1 AIN2 input is selected
Conditions
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ASAHI KASEI
[AK8856VN]
PGA ( Programmable Gain Amp )
A PGA (Programmable Gain Amp) is integrated into the input stage of the AK8856. The PGA is adjustable from 0 dB to 12 dB, with gain steps of 0.1 dB / step. The input signal is attenuated by 50% by a resistor divider. The PGA setting is determined by PGA Control Register (R/W) [Sub Address 0x05]. By writing a "1" to the Control 2 Register (R/W) [Sub Address 0x04] AGC-bit, the AGC function is enabled. Since the setting of the AGC is written by the PGA Control Register (R/W) [Sub Address 0x05], the AGC value can be read through this register (manual setting of the PGA is invalid). When the AGC function is disabled, manual setting of the PGA gain is allowed. Bit allocation of PGA Control Register is as follows: [PGA Control Register] Sub Address 0x05 bit 7 bit 6
Reserved 0 PGA6 0
bit 5
PGA5 0
bit 4
bit 3
bit 2
PGA2 1
Default Value: 0x15 bit 1 bit 0
PGA1 0 PGA0 1
PGA4 PGA3 Default Value 1 0
AGC
The AK8856 has an adaptive AGC function. When AGC is enabled, the input signal is controlled to an optimized level by the PGA. When AGC is turned off, manual gain setting of PGA by is allowed. Enable / disable setting of the AGC is done by Control 2 Register (R/W) [Sub Address 0x04]. Sub Address 0x04 bit 7 bit 6
CNTSEL 0 NSIGDEF 0
bit 5
ODEV 0
bit 4
bit 3
bit 2
COLKIL 0
Default Value: 0x00 bit 1 bit 0
ACC 0 AGC 0
FRMRT1 FRMRT0 Default Value 0 0
[AGC]-bit The [AGC] bit sets the mode of for the AGC. [AGC]-bit Function
0 1 Disable Enable
Condition
note ) writing into the PGA register is possible while the AGC is enabled, but the written result is not valid to register. The written result becomes valid to the register when the AGC is disabled. There are two types of AGC-bits - one is AGCC-bit to set coring level, and the other is AGCTR-bit to control transition speed between Peak AGC and Sync AGC operations. AGCC [1:0]-bit [AGCC]-bit setting
00 01 10 11
Function
+/- 2 LSB coring level +/- 3 LSB coring level +/- 4 LSB coring level no coring
Note
MS0522-E-00
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2006/Dec
ASAHI KASEI
[AK8856VN]
AGCCTR-bit [AGCTR]-bit setting
0 1
Function
Slow transition speed from Peak AGC to Sync AGC is fast
Note
same as AK8855
Clamp
The input signal is Analog Sync-Tip clamped. The Sync-Tip clamped input signal is then clamped to the Pedestal level after A/D conversion.
Anti-Aliasing Filter
An Analog Band Limit Filter is integrated before the ADC input in the AK8856. The Anti-Aliasing Filter has following characteristics:
1.0dB (~ 6.0MHz) 27MHz -24dB (typ)
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2006/Dec
ASAHI KASEI
[AK8856VN]
Clock
Sampling is controlled by a fixed clock in the AK8856. A PLL to synchronize the sampling clock with analog input signal is not built-in. The clock rate differs depending on the selected output picture sizes and types of input signal. The internal operating clock is either 27MHz or 24.5454MHz, which is generated from the input clock by the PLL. The internal clock rate is automatically determined by the output picture size. Operation clock
VGA QVGA CIF QCIF 601 QVGA CIF 24.5454MHz 24.5454MHz 27MHz 27MHz 27MHz 27MHz 24.5454MHz 24.5454MHz
Size
640 x 480 320 x 240 352 x 288 176 x 144 720 x 480 720 x 576 240 x 180 288 x 216
Signal
NTSC/PAL NTSC/PAL NTSC/PAL NTSC/PAL NTSC PAL NTSC/PAL NTSC/PAL
Note
Interlace output Progressive output
Rotated size Rotated size
note) For rotated CIF size, both the left-end and right-end 16 pixels are omitted and 288 X 216 picture size is output (90% area of the effective picture is output). When decoding CIF (NTSC), output rate is 2X speed of input HD.
Output Picture Size
The output picture size is set by the [OFORM2 : OFORM0] bits of Output Control 1 Register (R/W) [Sub Address 0x01].
[OFORM2:OFORM0]-bit [OFORM2:OFROM0]-bit
000 001 010 011 100 101 110
Function
QVGA VGA CIF QCIF Rotated QVGA Rotated CIF 601
Condition
MS0522-E-00
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2006/Dec
ASAHI KASEI
[AK8856VN]
Decimation Filter
Typical characteristic of the decimation filter is shown here (27 MHz sampling).
Frequency [MHz] 5.0 6.0 7.0 8.0
0.0 10.0 0.0 -10.0 Gain [dB] -20.0 -30.0 -40.0 -50.0 -60.0
1.0
2.0
3.0
4.0
9.0 10.0 11.0 12.0 13.0
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2006/Dec
ASAHI KASEI
[AK8856VN]
Sync-Separation, Sync-Detection
Sync-Detection and Separation are executed from the digitized input signal. The recognized Sync-signal is used as reference timing for decoding process.
Digital Pedestal Clamp
The pedestal is clamped in the digital domain. The internal clamp level differs according to the type of input signal (286mV Sync signal or 300 mV Sync signal), but the output is fixes the pedestal position at code 16 (8-bit Rec. 601 level) for either condition.
YC Separation
YC separation can be either 1D or 2D. The filter characteristic for YC separation is shown here (27 MHz sampling):
10 0 -10 Gain[dB] -20 -30 -40 -50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
frequency[MHz]
YC separation is set by the YCSEP-bit of the Control 1 Register (R/W) [Sub Address 0x03] Sub Address 0x03 bit 7 bit 6
Reserved 0 VDFLD 0
bit 5
AGCTR 0
bit 4
bit 3
bit 2
CKILSEL1 0
Default Value: 0x00 bit 1 bit 0
CKILSEL0 0 YCSEP 0
AGCC1 AGCC0 Default Value 0 0
YCSEP-bit setting results in the following conditions: YCSEP-bit
0 1
QVGA, QCIF, QVGAL, CIFL
Y: 1DYC-filter C: 1DYC-filter AK8855 compatible Y: 1DYC-filter C: 2DYC-filter
NTSC CIF
Y: 1DYC-filter C: 1DYC-filter AK8855 compatible
VGA, 601
Y: 1DYC-filter C: 1DYC-filter AK8855 compatible Y : 2DYC-filter C : 2DYC-filter
PAL DPAL* switch is turned ON / OFF by the YCSEP-bit (DPAL switch is always OFF in VGA mode (YCSEP-bit has no effect )). DPAL*: process of averaging Color phases between Lines.
MS0522-E-00
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2006/Dec
ASAHI KASEI
[AK8856VN]
Auto Color Control (ACC)
This function is used to adjust the Color Burst level of the input signal to a proper level (NTSC : 286mV / PAL: 300mV). The Input Color signal level is determined by the Color Burst signal. ACC gain is 20dB maximum. ACC is turned ON / OFF by setting the ACC-bit of Control 2 Register (R/W) [Sub Address 0x04] . Sub Address 0x04 bit 7 bit 6
CNTSEL 0 NSIGDEF 0
bit 5
ODEV 0
bit 4
bit 3
bit 2
COLKIL 0
Default Value: 0x00 bit 1 bit 0
ACC 0 AGC 0
FRMRT1 FRMRT0 Default Value 0 0
[ACC] bit The [ACC] bit selects enable / disable of ACC and time constant. [ACC]-bit ACC Setting
0 1 Disable Enable
Condition
The ACC function operates independently from the Color Saturation Adjust function (when ACC is enabled, Color Saturation adjustment is performed on the signal, which is adjusted to a proper level by ACC).
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2006/Dec
ASAHI KASEI
[AK8856VN]
Color Killer
The Chroma Signal Quality is determined by the Color Burst level of the input signal. When the Chroma Signal level is lower than a threshold level, it is regarded as an improper signal, and the input signal is processed as strictly a luminance signal. In this case, Cb / Cr data from the AK8856 is fixed at 0x80 in 601 level. Color Killer operation is selectable from the following 3 conditions, and it is set by the CKILSEL 1:0 bits: (1) When the Color Burst level is lower than approximately - 23 dB. (2) When the PLL for Color decoding cannot be locked. (3) When either condition (1) or (2) is met. Color Killer is set ON or OFF by the Control 2 Register (R/W) [Sub Address 0x04]. Color Killer operating conditions are set by the CKILSEL[1:0] bit of the Control 1 Register (R/W) [Sub Address 0x03]. Sub Address 0x04
bit 7 CNTSEL 0 bit 6 NSIGDEF 0 bit 5 ODEV 0 bit 4 bit 3 FRMRT1 FRMRT0 Default Value 0 0 bit 2 COLKIL 0
Default Value: 0x00
bit 1 ACC 0 bit 0 AGC 0
[COLKILL]-bit This bit enables or disables the Color Killer function. COLKILL-bit Color Killer Function
0 1 Enable Disable
Condition
Sub Address 0x03 bit 7 bit 6
Reserved 0 VDFLD 0
bit 5
AGCTR 0
bit 4
bit 3
bit 2
CKILSEL1 0
Default Value: 0x00 bit 1 bit 0
CKILSEL0 0 YCSEP 0
AGCC1 AGCC0 Default Value 0 0
[CKILSEL 1:0]-bit CKILSEL1:0-bit
00 01 10 11
Color Killer Operation
when either Color Burst level is lower than -23 dB or when PLL for Color decoding cannot be locked. when PLL for Color decoding cannot be locked. when Color Burst level is lower than approximately - 23 dB. Reserved
Note
AK8855 compatible
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2006/Dec
ASAHI KASEI
[AK8856VN]
Frame Rate Setting
The Frame Rate is set by the [FRMRT1 : FRMRT0] bits of the Control 2 Register (R/W) [Sub Address 0x04]. [FRMRT1:FRMRT0]-bit
00 01 10 11
Frame Rate
30/25(525/625) 15/12.25(525/625) 7.5/6.25(525/625) Reserved
Condition
Even / Odd Field Selection
Even or Odd Field setting is used for QVGA / CIF / QCIF output modes, selected by the [ODEV] bit of the Control 2 Register (R/W) [Sub Address 0x04].
ODEV-bit 0 1 Condition ODD Field EVEN Field
UV Filter
The UV Filter characteristic is shown here:
MS0522-E-00
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2006/Dec
ASAHI KASEI
[AK8856VN]
Picture Quality Adjust Process Function
Picture Quality Adjustments such as contrast, brightness, color saturation and color hue are integrated in the AK8856. (1) Contrast Contrast is adjusted by multiplying the Luminance signal (Y) by a gain value which is set by Contrast Control Register ( R/W ) [ Sub Address 0x06]. CNTSEL bit = 0 YOUT = CONT* (YIN - 128) + 125 YOUT : contrast arithmetic operation result YIN : before contrast arithmetic operation CONT : contrast coefficient (register value)
It is also possible to define the equation by setting the register: CNTSEL bit = 1 YOUT = CONT* (YIN - 128) + 16 YOUT : contrast arithmetic operation result YIN : before contrast arithmetic operation CONT : contrast coefficient (register set value) Setting is done with the [CNTSEL] bit of Control 2 Register (R/W) [Sub Address 0x04] The range of the contrast gain coefficient varies from 0 to 1.99 (1/128 step), and when the arithmetic operation result exceeds this range, it is clipped to the upper-limit of 254, or the lower-limit of 1 (the output result ranges from 16 to 235 when the 601 limit-bit is 1). Bit allocation of Contrast Control Register: Sub Address 0x06 bit 7 bit 6
CONT7 1 CONT6 0
bit 5
CONT5 0
bit 4
bit 3
bit 2
CONT2 0
Default Value: 0x80 bit 1 bit 0
CONT1 0 CONT0 0
CONT4 CONT3 Default Value 0 0
Sub Address 0x04 bit 7 bit 6
CNTSEL 0 NSIGDEF 0
bit 5
ODEV 0
bit 4
bit 3
bit 2
COLKIL 0
Default Value: 0x00 bit 1 bit 0
ACC 0 AGC 0
FRMRT1 FRMRT0 Default Value 0 0
[CNTSEL] bit This bit sets the changeover point of the contrast adjustment. [CNTSEL]-bit Function
0 1 To be adjusted at Luminance 125 as a center point To be adjusted at Luminance 16 as a center point.
Condition
MS0522-E-00
28
2006/Dec
ASAHI KASEI
[AK8856VN]
(2) Brightness Brightness is adjusted by adding a value which is set by Brightness Control Register (R/W) [Sub Address 0x07] to the luminance (Y) signal. YOUT = YIN + BR YOUT : brightness arithmetic operation result YIN : before brightness arithmetic operation BR : brightness coefficient (register value)
The brightness coefficient varies from -127 to +127, and the value is in 2's complement format. When the arithmetic operation result exceeds this range, it is clamped to the upper-limit of 254 or the lower-limit of 1 (output result ranges from 16 to 235 when the 601 limit-bit is 1). Bit allocation of Brightness Control Register: Sub Address 0x07 bit 7 bit 6
BR7 0 BR6 0
bit 5
BR5 0
bit 4
bit 3
bit 2
BR2 0
Default Value: 0x00 bit 1 bit 0
BR1 0 BR0 0
BR4 BR3 Default Value 0 0
(3) Color Saturation Color Saturation is adjusted by multiplying the Color Signal (C) by a value which is set by the Saturation Control Register (R/W) [Sub Address 0x08]. The arithmetic result is U / V de-modulated. The Saturation coefficient varies from 0 to 255 in 1/128 programmable steps. The default value of the register is a nonadjusted value (0x80). Bit allocation of Saturation Control Register: Sub Address 0x08 bit 7 bit 6
SAT7 1 SAT6 0
bit 5
SAT5 0
bit 4
bit 3
bit 2
SAT2 0
Default Value: 0x80 bit 1 bit 0
SAT1 0 SAT0 0
SAT4 SAT3 Default Value 0 0
(4) Color Hue Color Hue can be rotated in the AK8856. The rotation amount of Color Hue is determined by a value which is set by the HUE Control Register (R/W) [Sub Address 0x09]. Rotation phase varies from 45 degrees (0.35 degrees per step). The default value of the register is a non-adjusted value (0x00). The register value is in 2's complement format. Bit allocation of Hue Control Register: Sub Address 0x09 bit 7 bit 6
HUE7 0 HUE6 0
bit 5
HUE5 0
bit 4
bit 3
bit 2
HUE2 0
Default Value: 0x00 bit 1 bit 0
HUE1 0 HUE0 0
HUE4 HUE3 Default Value 0 0
MS0522-E-00
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2006/Dec
ASAHI KASEI
[AK8856VN]
Input Video Decoding Period
The number of lines used for video decoding varies according to the output mode. Refer to the figure on thr next page which shows "Input Video Signal vs. Output Data relationship". Active Video Period: 525 line system: line 22 ~ line 261 & line 285 ~ line 524 625 line system: line 23 ~ line 310 & line 336 ~ line 623 Vertical Blanking Period: 525 line system: line 525 ~ line 1 ~ line 21 & line 262 ~ line 284 625 line system: line 624 ~ line 625 - line1 ~ line 22 & line 311 ~ line 335 The default value for the output during the Vertical Blanking period is Black level (Y = 0x10, Cb/Cr = 0x80)
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2006/Dec
ASAHI KASEI
[AK8856VN]
NTSC
Line # QVGA)
( Low logic indicates Active lines. )
3 4 5 6 7 ... 21 22 23 24 25 26 27 28 29 30 31 ... 258 259 260 261 262 263 264 265
VGA
CIF
QCIF
QVGAL
CIFL
601
Line # QVGA)
266
267
268
269
270
...
284
285
286
287
288
289
290
291
292
293
294
...
521
522
523
524
525
1
2
3
VGA
CIF
QCIF
QVGAL
CIFL
601
Input Video Signal vs Output Data Relationship (NTSC)
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2006/Dec
ASAHI KASEI
[AK8856VN]
PAL ( Low logic indicates Active lines. )
Line # QVGA VGA CIF QCIF QVGAL CIFL 601 625 1 2 3 4 ... 22 23 24 25 26 27 28 29 30 31 32 ... 307 308 309 310 311 312 313 314
Line # QVGA VGA CIF QCIF QVGAL CIFL 601
313
314
315
316
317
...
335
336
337
338
339
340
341
342
343
344
345
...
620
621
622
623
624
625
1
2
Input Video Signal vs Output Data Relationship (PAL)
MS0522-E-00
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2006/Dec
ASAHI KASEI
[AK8856VN]
Closed Caption / Closed Caption Extended Data / VBID (CGMS) / WSS
Closed Caption data, Closed Caption Extended data, VBID (CGMS) and WSS signals that are super-imposed during the VBI interval are decoded in the AK8856. The decoded data is written into a register. When the request bits [bit3 : bit 0] of the Request VBI Info Register ( W ) [ Sub Address 0x0A] are set, the AK8856 acknowledges that a decode request of the data has been made, and it is placed into a data wait condition. After data is detected and decoded, the host is notified, using [bit7 : bit 5] of the Status Register (R/W) [Sub Address 0x10] that decoding has been completed. The results are written into the Closed Caption 1 Register ( R ) [ Sub Address 0x12 ] / Closed Caption 2 Register ( R ) [ Sub Address 0x13 ], Extended Data 1 Register ( R ) [ Sub Address 0x14 ] / Extended Data 2 Register ( R ) [ Sub Address 0x15 ], VBID / WSS1 Register ( R ) [ Sub Address 0x16 ] / VBID / WSS2 Register ( R ) [ Sub Address 0x17 ] respectively. The data are super-imposed on the respective line: CRCC code of VBID data (CGMS-A) is decoded and the result is stored in the register. Signal Line Note
Closed Caption Closed Caption Extended VBID WSS NTSC : Line-21 NTSC : Line-284 NTSC : Line-20/283 PAL : Line-23 525-Line 525-Line 525-Line 625-Line
Configuration of Request VBI INFO Register: Sub Address 0x0A bit 7 bit 6
Reserved 0 Reserved 0
bit 5
Reserved 0
bit 4
bit 3
bit 2
VBWSRQ 0
Default Value: 0x00 bit 1 bit 0
EXTRQ 0 CCRQ 0
Reserved Reserved Default Value 0 0
Configuration of Status Register is as follows Sub Address 0x10 bit 7 bit 6
VBWSSDET EXTDET
bit 5
CCDET
bit 4
AGCSTS
bit 3
VLOCKSTS
bit 2
PKWHITE
bit 1
COLKILST
bit 0
NSIG
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2006/Dec
ASAHI KASEI
[AK8856VN]
Information read-out flow during VBI interval:
Start
[ Request VBI Info Register ] xxRQ-bit = 1 ( Decode Request )
Closed Caption: CCRQ-bit Closed Caption Extended : EXTRQ-bit VBID/WSS: VBWSRQ-bit
[ Status Register ] Read ( Verif ication of decode completion )
( Corresponding bit is "1" to the request ? ) Yes ( Read-out of the corresponding data register to the request )
No Closed Caption: CCDET-bit Closed Caption Extended : EXTDET-bit VBID/WSS: VBWSDET-bit Closed Caption: [Closed Caption 1/2 Register] Closed Caption Extended : [Extended Data 1/2 Register] VBID/WSS: [VBID/WSS 1/2 Register]
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2006/Dec
ASAHI KASEI
[AK8856VN]
Reading Closed Caption data : Write a "1" to the CCRQ-bit of Request VBI Info Register (W) [Sub Address 0x0A]. When a "1" is written to this bit, the AK8856 is placed in a wait condition for Closed Caption Data decoding. Then when data arrives, it is decoded and a "1" is written back to the CCDET-bit of the Status Register (R / W) [Sub Address 0x10]. After reset, the CCDET-bit is "1" (it goes to "0" when a "1" is written to the CCRQ-bit ). The decoded data is written into the Closed Caption 1 Register (R) [Sub Address 0x12] and the Closed Caption 2 Register (R) [Sub Address 0x13]. Data in the Closed Caption 1 Register and Closed Caption 2 Register are retained until they are over-written with new data. Configuration of Closed Caption 1 Register and Closed Caption 2 Register: Closed Caption 1 Register (R) [Sub Address 0x12] Sub Address 0x12 bit 7 bit 6 bit 5 bit 4
CC7 CC6 CC5 CC4
bit 3
CC3
bit 2
CC2
bit 1
CC1
bit 0
CC0
Closed Caption 2 Register (R) [Sub Address 0x13] Sub Address 0x13 bit 7 bit 6 bit 5 bit 4
CC15 CC14 CC13 CC12
bit 3
CC11
bit 2
CC10
bit 1
CC9
bit 0
CC8
Reading out Closed Caption Extended Data : Write a "1" to the EXTRQ-bit of the Request VBI Info Register ( W ) [ Sub Address 0x0A ]. When a "1" is written to this bit, the AK8856 is placed in a wait condition for Extended Data decoding. Then when data arrives, it is decoded and a "1" is written to the EXTDET-bit of the Status Register (R / W) [ Sub Address 0x10]. After reset, the EXTDET-bit is "1" (it goes to "0" when a "1" is written to the EXTRQ-bit). The decoded data is written into the Extended Data 1 Register (R) [Sub Address 0x14] and the Extended Data 2 Register (R) [Sub Address ox15]. Data in the Extended Data 1 Register and Extended Data 2 Register are retained until they are over-written with new data. Configuration of Extended Data 1 Register and Extended Data 2 Register: Extended Data 1 Register (R) [Sub Address 0x14] Sub Address 0x14 bit 7 bit 6 bit 5 bit 4
EXT7 EXT6 EXT5 EXT4
bit 3
EXT3
bit 2
EXT2
bit 1
EXT1
bit 0
EXT0
Extended Data 2 Register (R) [Sub Address 0x15] Sub Address 0x15 bit 7 bit 6 bit 5 bit 4
EXT15 EXT14 EXT13 EXT12
bit 3
EXT11
bit 2
EXT10
bit 1
EXT9
bit 0
EXT8
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2006/Dec
ASAHI KASEI
[AK8856VN]
Reading out VBID Data : Write a "1" to the VBWSRQ-bit of the Request VBI Info Register (W) [Sub Address 0x0A]. When a "1" is written to this bit, the AK8856 is placed in a wait condition for VBID data decoding. Then when data arrives, it is decoded and a "1" is written to the VBWSDET-bit of the Status Register (R / W) [Sub Address 0x10 ]. After reset, the VBWSDET-bit is a "1" (it goes to "0" when a "1" is written to the VBWSRQ-bit). Decoded data is 13-bits long, and it is written into the VBID / WSS1 Register ( R ) [ Sub Address 0x16 ] and VBID / WSS 2 Register ( R ) [ Sub Address 0x17 ]. VBID data is valid only in a 525-line system. These registers are also commonly used for WSS Read-Out register. CRCC code is decoded and the result is stored in the register. Data in the VBID / WSS 1 Register and VBID / WSS 2 Register are retained until they are over-written with new data. Configuration of VBID / WSS 1 Register and VBID / WSS 2 Register: VBID/WSS 1 Register (R) [Sub Address 0x16] Register to store VBID data Sub Address 0x16 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
Reserved Reserved VBID1 VBID2 VBID3 VBID4
bit 1
VBID5
bit 0
VBID6
VBID/WSS 2 Register (R) [Sub Address 0x17] Register to store VBID data Sub Address 0x17 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
VBID7 VBID8 VBID9 VBID10 VBID11 VBID12
bit 1
VBID13
bit 0
VBID14
Reading out WSS Data : Write a "1" to the VBWSRQ-bit of the Request VBI Info Register (W) [Sub Address 0x0A]. When a "1" is written to this bit, the AK8856 is placed in a wait condition for VBWS data decoding. Then when data arrives, it is decoded and a "1" is written back to the VBWS-bit of Status Register (R / W) [Sub Address 0x10]. After reset, the VBWS-bit is a "1" (it goes to "0" when a "1" is written to the VBWSRQ-bit). WSS data is valid only for 625-line systems. These registers are also commonly used for VBID Read-Out register. Decoded data are written into the VBID / WSS 1 Register (R) [Sub Address 0x16] and the VBID / WSS 2 Register (R) [Sub Address 0x17]. Data in the VBID / WSS 1 Register and the VBID / WSS 2 Register are retained until they are over-written with new data. VBID/WSS 1 Register (R) [Sub Address 0x16] Register for storing WSS data Sub Address 0x16 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
Reserved Reserved G4-13 G4-12 G4-11 G3-10
bit 1
G3-9
bit 0
G3-8
VBID/WSS 2 Register (R) [Sub Address 0x17] Register for storing WSS data Sub Address 0x17 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
G2-7 G2-6 G2-5 G2-4 G1-3 G1-2
bit 1
G1-1
bit 0
G1-0
MS0522-E-00
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ASAHI KASEI
[AK8856VN]
Macrovision Decoding
When a Macrovision Copy Protect signal is present, the AK8856 decodes the additional Macrovision information and stores the result in the Macrovision Status Register (R/W) [Sub Address 0x11]. Configuration of the Macrovision Status Register: Sub Address 0x11 bit 7 bit 6
Reserved PSPDET
bit 5
AGCPDET
bit 4
BPPDET
bit 3
SYNCRED
bit 2
CSTYPE
bit 1
CSDET
bit 0
AGCDET
[AGCDET] bit When Macrovision AGC process is detected, this bit goes to "1". [AGCDET]-bit Status of Macrovision Detection
0 1 AGC Process not detected AGC Process detected
Condition
[CSDET] bit When Macrovision Color Stripe Process is detected, this bit goes to "1". [CSDET]-bit Status of Macrovision Detection
0 1 Color Stripe Process not detected Color Stripe Process detected
Condition
[CSTYPE] bit When the CSDET-bit is "1", Color Stripe Process type is indicated. [CSTYPE]-bit Status of Macrovision Detection
0 1 Color Stripe Type 2 is set Color Stripe Type 3 is set
Condition
[SYNCRED] bit When the SYNCRED-bit is "1", Sync Reduction has been detected. [SYNCRED]-bit Status of Macrovision Detection
0 1 Sync Reduction detected
Condition
[BPPDET] bit When the BPPDET-bit is "1", an "End of Field Back Porch Pulse" has been detected. [BPPDET]-bit Status of Macrovision Detection Condition
0 1 End of Field Back Porch Pulse detected
[AGCPDET] bit When AGCPDET-bit is "1", an AGC Pulse has been detected. [AGCPDET]-bit Status of Macrovision Detection
0 1 AGC Pulse detected
Condition
[PSPDET] bit When PSPDET-bit is "1", a Pseudo Sync Pulse has been detected.
[PSPDET]-bit 0 1 Status of Macrovision Detection Pseudo Sync Pulse detected. Condition
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ASAHI KASEI
[AK8856VN]
Decode Data Output (Rec. 601 Limit)
The AK8856 outputs decoded data at a level (Y / Cb / Cb 4:2:2) specified by ITU-R BT.601. Minimum and maximum output data can be selected by the [LIMIT601] bit of the Output Control 1 Register (R/W) [Sub Address 0x01]. Bit allocation of Output Control 1 Register is as follows. Sub Address 0x01
bit 7 VDPSUP 0 bit 6 TRSVSEL 0 bit 5 OIF1 0 bit 4 bit 3 OIF0 LIMIT601 Default Value 0 0 bit 2 OFORM2 0
Default Value : 0x00
bit 1 OFORM1 0 bit 0 OFORM0 0
[LIMIT601] bit Maximum and minimum output data is specified by the [LIMIT601]-bit. All internal arithmetic operations are processed at Min. = 1, Max. = 254. Clipping value of the output code differs by the setting of the [LIMIT601] -bit. The default setting value is "0". LIMIT601-bit
0 1
Output code Min.Max
Y : 1 ~ 254 Cb/Cr : 1 ~ 254 Y : 16 ~ 235 Cb/Cr : 16 ~ 240
Condition
( Default value )
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ASAHI KASEI
[AK8856VN]
Output Interface
The AK8856 supports 3 types of interfaces: (1) Camera interface (QVGA / CIF / QCIF) (2) Interface by HD / VD / DVALID (VGA / QVGA / CIF / QCIF) (3) 656 Interface (601 specification compatible size (720 X 480)) (1) Camera Interface There are two types of data interfaces: "(1-1) HV & VAF Interface Mode" and "(1-2) SAV / EAV Interface Mode". In this mode, since synchronization shift with the input signal is adjusted at the head part of the line, the interval between lines may fluctuate to some degree. When an exceptional input signal is decoded, there may be cases where the lack of number of lines and lack of number of pixels per line occur, regardless of operation mode. At the default value, an end of frame is set at the rising edge of the VAF signal, and an end of line is set by the HV signal. The polarity of VAF / HV / DVALID / CLKO is programmable through the Output Control 2 Register (R/W) [Sub Address (0x02)]. The following timing diagrams show operation examples at HDP = 0, VDP = 0, DVALDP = 0, and CLKINV = 1 settings. Since the output is progressive in Camera Interface mode, picture sizes in this mode are QVGA / CIF / QCIF / rotated QVGA / rotated CIF. Definition of SAV / EAV Interface Mode: SAV 0x80 0xAB EAV 0x9D 0xB6
Active VBlank
In SAV / EAV output mode, HV / VAF signal is not output by default. The register must be set for this mode.
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2006/Dec
ASAHI KASEI
[AK8856VN]
(1-1) HV / VAF Interface The following timing diagram shows CIF size output as an example.
VD/VAF
HD/HV
****** Line288
Line1
Line2
Line3
Line4
Line1
Line2
D/CDT[7:0]
CLKO
HD/HV
Cb175
Cr175
Y351
D/CDT[7:0]
******
Cb0
Cb1
Cb2
Cr0
Cr1
Y0
Y1
Y2
Y3
Y4
CLKO
******
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2006/Dec
ASAHI KASEI
[AK8856VN]
(1-2) SAV / EAV Interface (CIF size output example)
VD/VAF
HD/HV active SAV
****** VBlank SAV Blank Line Line288 Line287 Line4 Line1
Line1
Line2
Line3
D/CDT[7:0]
active EAV CLKO
VBlank EAV
HD/HV D/CDT[7:0]
Cb175
Cr175
Y351
0xFF
0xFF
0x00
0x00
0x00
0x00
SAV
EAV
******
Cb0
Cb1
Cr0
Y0
Y1
Y2
MS0522-E-00
41
2006/Dec
ASAHI KASEi
Output timing for the Camera Interface mode is illustrated here (the polarity of HV/VAF/DVALID can be changed by register setting).
NTSC Register Set : VLF = 1'b0, OIF[1:0] = 2'b10
Line # HV/DVALID
(QVGA)
3
4
5
6
7
...
21
22
23
24
25
26
27
28
29
30
31
...
258
259
260
261
262
263
264
265
VAF
(QVGA)
HV/DVALID
(VGA)
VAF
(VGA)
HV/DVALID
(CIF)
VAF
(CIF)
HV/DVALID
(QCIF)
VAF
(QCIF)
HV/DVALID
(QVGAL)
VAF
(QVGAL)
HV/DVALID
(CIFL)
VAF
(CIFL)
HV/DVALID
(601)
VAF
(601)
Note: For output modes other than VGA or 601, DVALID signal becomes active (low) at either ODD or EVEN timing. QVGAL: Rotated QVGA, CIFL: Rotated CIF
MS0522-E-00
42
2006/Dec
ASAHI KASEi
NTSC Register Set : VLF = 1'b0, OIF[1:0] = 2'b10
Line # HV/DVALID
(QVGA)
266
267
268
269
270
...
284
285
286
287
288
289
290
291
292
293
294
...
521
522
523
524
525
1
2
3
VAF
(QVGA)
HV/DVALID
(VGA)
VAF
(VGA)
HV/DVALID
(CIF)
VAF
(CIF)
HV/DVALID
(QCIF)
VAF
(QCIF)
HV/DVALID
(QVGAL)
VAF
(QVGAL)
HV/DVALID
(CIFL)
VAF
(CIFL)
HV/DVALID
(601)
VAF
(601)
Note: For output modes other than VGA or 601, DVALID signal becomes active (low) at either ODD or EVEN timing. QVGAL: Rotated QVGA, CIFL: Rotated CIF
MS0522-E-00
43
2006/Dec
ASAHI KASEi
PAL
Register Set : VLF = 1'b1, OIF[1:0] = 2'b10
625 1 2 3 4 ... 22 23 24 25 26 27 28 29 30 31 32 ... 307 308 309 310 311 312 313 314
Line # HV/DVALID
(QVGA)
VAF
(QVGA)
HV/DVALID
(VGA)
VAF
(VGA)
HV/DVALID
(CIF)
VAF
(CIF)
HV/DVALID
(QCIF)
VAF
(QCIF)
HV/DVALID
(QVGAL)
VAF
(QVGAL)
HV/DVALID
(CIFL)
VAF
(CIFL)
HV/DVALID
(601)
VAF
(601)
Note: For output modes other than VGA or 601, DVALID signal becomes active (low) for either ODD or EVEN timing. QVGAL: Rotated QVGA, CIFL: Rotated CIF
MS0522-E-00
44
2006/Dec
ASAHI KASEi
PAL
Register Set : VLF = 1'b1, OIF[1:0] = 2'b10
313 314 315 316 317 ... 335 336 337 338 339 340 341 342 343 344 345 ... 620 621 622 623 624 625 1 2
Line # HV/DVALID
(QVGA)
VAF
(QVGA)
HV/DVALID
(VGA)
VAF
(VGA)
HV/DVALID
(CIF)
VAF
(CIF)
HV/DVALID
(QCIF)
VAF
(QCIF)
HV/DVALID
(QVGAL)
VAF
(QVGAL)
HV/DVALID
(CIFL)
VAF
(CIFL)
HV/DVALID
(601)
VAF
(601)
Note: For output mode modes other than VGA or 601, DVALID signal becomes active (low) for either ODD or EVEN timing. QVGAL: Rotated QVGA, CIFL: Rotated CIF
Timing Chart (Camera I/F)
QVGA (NTSC) Register Set : VLF = 1'b0, OFORM[2:0] = 3'b000, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(12.2727MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 318
Y 318
Cr318
Y 319
0x80
0x80
640 clock @CLKO
Timing Chart (Camera I/F)
VGA (NTSC)
Register Set : VLF = 1'b0, OFORM[2:0] = 3'b001, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(24.5454MHz)
H L H
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 318 Y 636 Cr318 Y 637 Cb 319 Y 638 Cr319 Y 639 0x80 0x10
0x80 0x10
1280 clock @CLKO
MS0522-E-00
45
2006/Dec
ASAHI KASEi
Timing Chart (Camera I/F)
CIF (NTSC)
Register Set : VLF = 1'b0, OFORM[2:0] = 3'b010, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(27.0MHz)
H L H
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 348 Y 348 Cr348 Y 349 Cb 350 Y 350 Cr350 Y 351 0x80 0x10
0x80 0x10
704 clock @CLKO
For NTSC, CIF output mode, 2 lines are output while the 1 line input. HD/VD signal are also output doubled rate.
Timing Chart (Camera I/F)
QCIF (NTSC)
Register Set : VLF = 1'b0, OFORM[2:0] = 3'b011, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(13.5MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 174
Y 174
Cr174
Y 175
0x80
0x80
352 clock @CLKO
MS0522-E-00
46
2006/Dec
ASAHI KASEi
Timing Chart (Camera I/F)
Rotated QVGA (NTSC) Register Set: VLF = 1'b0, OFORM[2:0] = 3'b100, OIF[1:0] = 2'b00
HV VAF DVALID CLKO (12.2727MH D[7:0]
H L H
Cb 0
Y0
Cb 238
Y 238
Cr 238
Y239
0x80
0x80
480 clock @CLKO
Timing Chart (Camera I/F)
Rotated CIF (NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b101, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(12.2727MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 286
Y 286
Cr 286
Y287
0x80
0x80
576 clock @CLKO
Timing Chart (Camera I/F)
601Output (NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b110, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(27.0MHz)
H L H
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 716 Y 716 Cr716 Y 717 Cb 718 Y 718 Cr718 Y 719 0x80 0x10
0x80 0x10
1440 clock @CLKO
MS0522-E-00
47
2006/Dec
ASAHI KASEi
Timing Chart (Camera I/F)
QVGA (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b000, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(12.2727MHz)
H L H
D[7:0]
0x10
Cb 0
Y0
Cb 318
Y 318
Cr318
Y 319
0x80
0x80
640 clock @CLKO
Timing Chart (Camera I/F)
QVGA (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b000, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(24.5454MHz)
H L H
D[7:0]
0x10
Cb 0
Y0
Cb 319
Y 638
Cr319
Y 639
0x80
0x80
1280 clock @CLKO
MS0522-E-00
48
2006/Dec
ASAHI KASEi
Timing Chart (Camera I/F)
CIF (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b010, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(13.5MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 175
Y 350
Cr 175
Y351
0x80
0x80
704 clock @CLKO
Timing Chart (Camera I/F)
QCIF (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b011, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(13.5MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 87
Y 174
Cr87
Y175
0x80
0x80
352 clock @CLKO
MS0522-E-00
49
2006/Dec
ASAHI KASEi
Timing Chart (Camera I/F)
Rotated QVGA (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b100, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(12.2727MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 119
Y 238
Cr119
Y 239
0x80
0x80
480 clock @CLKO
Timing Chart (Camera I/F)
Rotated CIF (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b101, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(13.5MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 143
Y 286
Cr143
Y 287
0x80
0x80
576 clock @CLKO
MS0522-E-00
50
2006/Dec
ASAHI KASEi
Timing Chart (Camera I/F)
601Output (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b110, OIF[1:0] =
HD/HV VAF DVALID CLKO
(27.0MHz)
H L H
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 358 Y716 Cr358 Y 717 Cb 359 Y 718 Cr359 Y 719 0x80 0x10
0x80 0x10
1440 clock @CLKO
MS0522-E-00
51
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet ]
(2) Interface by HD / VD / DVALID In this interface mode, synchronization is determined by HD and VD. The DVALID signal is active low during the active video space. Since even and odd field recognition can be achieved through HD and VD, interlace information is known. The relationship of the DVALID signal and video data is illustrated here (601 output):
Video Signal
HSYNC DVALID CLK27MOUT
D[7:0]
Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
Y3
Y718 Cr359 Y719
Activ e Video Start position ( in normal operation, it is at 123th / 133th ( NTSC / P ) sampling, counting from 0h point )(601 mode ) AL
Timing diagram for HD / VD interface mode:
CLKOUT
HD DVALID DATA[7:0] b a
FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 FF 00 00 EAV
(Data FF0000SAV & FF0000EAV are in Rec.656 mode. For modes other than Rec.656, the data are replaced with 10H80H10H80H data)
MS0522-E-00
52
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet ]
525-Line (VLF-bit = 0) Mode
QVGA VGA CIF QCIF Rotated QVGA Rotated CIF 601
625-Line (VLF-bit = 1) Number of CLKO cycles
a 127 254 140 316 207 159 264 b 640 1280 704 352 480 576 1440 DTCLK Rate 12.2727MHz 24.5454MHz 13.5MHz 13.5MHz 12.2727MHz 12.2727MHz 27.0MHz
[OFORM2:OFROM0]
000 001 010 011 100 101 110
Number of CLKO cycles
a 118 236 130 306 198 150 244 b 640 1280 704 352 480 576 1440 DTCLK Rate 12.2727MHz 24.5454MHz 27.0MHz 13.5MHz 12.2727MHz 12.2727MHz 27MHz
* note: output data rate of CIF size mode in 525 line system (NTSC) is doubled.
MS0522-E-00
53
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
The relationship of HD/VD/DVALID is illustrated here. (The polarity of HD/VD/DVALID can be changed by setting the register)
NTSC Register Set : VLF = 1'b0, OIF[1:0] = 2'b10
Line # HD/HV
(Excep CIF)
3
4
5
6
7
...
21
22
23
24
25
26
27
28
29
30
31
...
258
259
260
261
262
263
264
265
HD(CIF) VD VDALID
(QVGA)
VAF
(QVGA)
VDALID
(VGA)
VAF
(VGA)
VDALID
(CIF)
VAF
(CIF)
VDALID
(QCIF)
VAF
(CIF)
VDALID
(QVGAL)
VAF
(QVGAL)
VDALID
(CIFL)
VAF
(CIFL)
VDALID
(601)
VAF
(601)
Note: For output modes other than VGA or 601, the DVALID signal becomes active (low) for either ODD or EVEN timing. QVGAL: Rotated QVGA, CIFL: Rotated CIF
MS0522-E-00
54
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
NTSC
Line # HD/HV
(Excep CIF)
Register Set: VLF = 1'b0, OIF[1:0] = 2'b10
266 267 268 269 270 ... 284 285 286 287 288 289 290 291 292 293 294 ... 521 522 523 524 525 1 2 3
HD(CIF) VD VDALID
(QVGA)
VAF
(QVGA)
VDALID
(VGA)
VAF
(VGA)
VDALID
(CIF)
VAF
(CIF)
VDALID
(QCIF)
VAF
(CIF)
VDALID
(QVGAL)
VAF
(QVGAL)
VDALID
(CIFL)
VAF
(CIFL)
VDALID
(601)
VAF
(601)
Note: For output modes other than VGA or 601, the DVALID signal becomes active (low) for either ODD or EVEN timing. QVGAL: Rotated QVGA, CIFL: Rotated CIF
MS0522-E-00
55
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
PAL
Line # HD/HV 625 1
Register Set: VLF = 1'b1, OIF[1:0] = 2'b10
2 3 4 ... 22 23 24 25 26 27 28 29 30 31 32 ... 307 308 309 310 311 312 313 314
VD VDALID
(QVGA)
VAF
(QVGA)
VDALID
(VGA)
VAF
(VGA)
VDALID
(CIF)
VAF
(CIF)
VDALID
(QCIF)
VAF
(CIF)
VDALID
(QVGAL)
VAF
(QVGAL)
VDALID
(CIFL)
VAF
(CIFL)
VDALID
(601)
VAF
(601)
Note: For output modes other than VGA or 601, the DVALID signal becomes active (low) for either ODD or EVEN timing. QVGAL: Rotated QVGA, CIFL: Rotated CIF
MS0522-E-00
56
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
PAL
Line # HD/HV 313 314
Register Set: VLF = 1'b1, OIF[1:0] = 2'b10
315 316 317 ... 335 336 337 338 339 340 341 342 343 344 345 ... 620 621 622 623 624 625 1 2
VD VDALID
(QVGA)
VAF
(QVGA)
VDALID
(VGA)
VAF
(VGA)
VDALID
(CIF)
VAF
(CIF)
VDALID
(QCIF)
VAF
(CIF)
VDALID
(QVGAL)
VAF
(QVGAL)
VDALID
(CIFL)
VAF
(CIFL)
VDALID
(601)
VAF
(601)
Note: For output modes other than VGA or 601, the DVALID signal becomes active (low) for either ODD or EVEN timing. QVGAL: Rotated QVGA, CIFL: Rotated CIF
MS0522-E-00
57
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
QVGA (NTSC) Register Set : VLF = 1'b0, OFORM[2:0] = 3'b000, OIF[1:0] = 2'b10
0x80
0x80
0x10
Cb 0
Y0
Cr 0
Y1
Cb 2
58 clock @CLKO 118 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] Cb 0 Y0 Cb 318 Y 318 Cr 318 Y 319 0x80 0x80 H H H
640 clock @CLKO
22 clock @CLKO
This value is not guaranteed. Just reference value.
MS0522-E-00
58
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
VGA (NTSC)
Register set : VLF = 1'b0, OFORM[2:0] = 3'b001, OIF[1:0] = 2'b10
0x80 0x10
0x80 0x10 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 2
Y2
Cr2
Y3
Cb 4
Y4
116 clock @CLKO 236 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] 0x80 0x10 Cb 0 Y0 Cr0 Y1 Cb 636 Y 636 Cr636 Y 637 Cb 638 Y 638 Cr638 Y 639 0x80 0x10 0x80 0x10 H H H
1280 clock @CLKO
44 clock @CLKO
This value is not guaranteed. Just reference value.
MS0522-E-00
59
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
CIF(NTSC)
Register Set : VLF = 1'b0, OFORM[2:0] = 3'b010, OIF[1:0] = 2'b10
0x80 0x10
0x80 0x10 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 2
Y2
Cr2
Y3
Cb 4
Y4
128 clock @CLKO 130 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] 0x80 0x10 Cb 0 Y0 Cr0 Y1 Cb 348 Y 348 Cr348 Y 349 Cb 350 Y 350 Cr350 Y 351 0x80 0x10 0x80 0x10 H H H
704 clock @CLKO
24 clock @CLKO
This value is not guaranteed. Just reference value.
For NTSC and CIF output mode, two lines are output while one line is input. HD/VD signal are also output at a doubled rate.
MS0522-E-00
60
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
QCIF (NTSC)
Register Set : VLF = 1'b0, OFORM[2:0] = 3'b011, OIF[1:0] = 2'b10
0x10
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 2
64 clock @CLKO 306 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] Cb 0 Y0 Cb 174 Y 174 Cr174 Y 175 0x80 0x10 H H H
352 clock @CLKO
200 clock @CLKO
This value is not guaranteed. Just reference value.
MS0522-E-00
61
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
Rotated QVGA (NTSC) Register Set: VLF = 1'b0, OFORM[2:0] = 3'b100, OIF[1:0] = 2'b10
0x80
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 2
58 clock @CLKO 198 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] Cb 0 Y0 Cb 238 Y 238 Cr238 Y 239 0x80 0x80 H H H
480 clock @CLKO
102 clock @CLKO
*This value is not guaranteed. Just reference value.
MS0522-E-00
62
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
Rotated CIF(NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b101, OIF[1:0] = 2'b10
0x80
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 2
58 clock @CLKO 150 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] Cb 0 Y0 Cb 286 Y 286 Cr286 Y 287 0x80 0x80 H H H
576 clock @CLKO
54 clock @CLKO
*This value is not guaranteed. Just reference value.
MS0522-E-00
63
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
601output (NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b110, OIF[1:0] = 2'b10
0x80 0x10
0x80 0x10 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 2
Y2
Cr2
Y3
Cb 4
Y4
128 clock @CLKO 244 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] 0x80 0x10 Cb 0 Y0 Cr0 Y1 Cb 716 Y 716 Cr716 Y 717 Cb 718 Y 718 Cr718 Y 719 0x80 0x10 0x80 0x10 H H H
1440 clock @CLKO
32 clock @CLKO
This value is not guaranteed. Just reference value.
MS0522-E-00
64
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
QVGA (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b000, OIF[1:0] = 2'b10
0x10
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 2
58 clock @CLKO 127 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] Cb 0 Y0 Cb 318 Y 318 Cr318 Y 319 0x80 0x10 H H H
640 clock @CLKO
13 clock @CLKO
*This value is not guaranteed. Just reference value.
MS0522-E-00
65
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
VGA (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b001, OIF[1:0] = 2'b10
0x80 0x10
0x80 0x10 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 2
Y2
Cr2
Y3
Cb 4
Y4
116 clock @CLKO 254 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] 0x80 0x10 Cb 0 Y0 Cr0 Y1 Cb 636 Y 636 Cr636 Y 637 Cb 638 Y 638 Cr638 Y 639 0x80 0x10 0x80 0x10 H H H
1280 clock @CLKO
26 clock @CLKO
*This value is not guaranteed. Just reference value.
MS0522-E-00
66
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
CIF (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b010, OIF[1:0] = 2'b10
0x80
0x80
0x10
Cb 0
Y0
Cr 0
Y1
Cb 2
64 clock @CLKO 140 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] Cb 0 Y0 Cb 350 Y 350 Cr 350 Y 351 0x80 0x80 H H H
704 clock @CLKO
20 clock @CLKO
This value is not guaranteed. Just reference value.
MS0522-E-00
67
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
QCIF (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b011, OIF[1:0] = 2'b10
0x80
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 2
64 clock @CLKO 316 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] Cb 0 Y0 Cb 174 Y 174 Cr174 Y 175 0x80 0x80 H H H
352 clock @CLKO
196 clock @CLKO
*This value is not guaranteed. Just reference value.
MS0522-E-00
68
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
Rotated QVGA (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b100, OIF[1:0] = 2'b10
0x10
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 2
58 clock @CLKO 207 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] Cb 0 Y0 Cb 238 Y 238 Cr238 Y 239 0x80 0x10 H H H
480 clock @CLKO
93 clock @CLKO
*This value is not guaranteed. Just reference value.
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Timing Chart
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
Rotated CIF (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b101, OIF[1:0] = 2'b10
0x10
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 2
58 clock @CLKO 159 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] Cb 0 Y0 Cb 286 Y 286 Cr286 Y 287 0x80 0x10 H H H
576 clock @CLKO
45 clock @CLKO
This value is not guaranteed. Just reference value.
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Timing Chart 2'b10
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] H H H
601output (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b110, OIF[1:0] =
0x80 0x10
0x80 0x10 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 2
Y2
Cr 2
Y3
Cb 4
Y4
128 clock @CLKO 264 clock @CLKO
CLKO HD/HV VD/VAF DVALID CLKO D[7:0] 0x80 0x10 Cb 0 Y0 Cr 0 Y1 Cb 716 Y 716 Cr716 Y 717 Cb 718 Y 718 Cr 718 Y 719 0x80 0x10 0x80 0x10 H H H
1440 clock @CLKO
24 clock @CLKO
*This value is not guaranteed. Just reference value.
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[AK8856 Preliminary Data Sheet]
(3) 656 Interface The AK8856 is designed for applications where the video data is typically processed with an MPEG algorithm. As such, it is capable of supporting a specific subset of the BT656 data interface. In 656 mode, the AK8856 generates synchronization codes SAV and EAV to indicate active video data. These codes are interpreted by the external digital video processor. In this mode, HD, DV, and DVALID signals are held low. The HD and DV signals can be read through a register setting. The relationship between the interface and the output format register is described here. Related registers are [OFORM1 : OFORM0] bits and [OIF2 : OIF0] bits of the Output Control 1 Register (R/W) [Sub Address 0x01]. Interface modes are set, regardless of OFORM register setting. OIF[0] = 1'b0 : without SAV/EAV 1'b1 : with SAV/EAV (at OFORM [ 2:0 ] = = 3'b 110 ", ITU-R BT.656) OIF[1] = 1'b0 : Camera I/F 1'b1 : HD/VD/DVALID I/F The Rec.656 mode supported by the AK8855 can be ITU-R BT. 656 compatible by setting OIF with SAV / EAV code (OIF [0] = = 1'b 1) when OFORM [2:0] = = 3' b 110. In all other codes, the V-bit of SAV / EAV becomes "0" during Vertical Active Video region only. When OIF [1:0] = = 2'b 11, the interface mode is HD / VD / DVALID interface with SAV / EAV code in the AK8856. In addition, when OFORM [2:0] = = 3'b 110, SAV / EAV is output in ITU-R BT.656 compatible fashion. By setting the [TRSVSEL] bit of the Output Control 1 Register (R/W) [Sub Address 0x01], it is possible to change the V-bit shift point of the 656 specified Video Timing Reference code (SAV / EAV) separately from the values referred to in the previous section. By properly setting the [TRSVSEL] bit, it is possible to make the shift point of V-bit compatible with ITU-R BT.656-3 or ITU-R BT.656-4 and SMPTE125M. Bit allocation of Output Control 1 Register Sub Address 0x01
bit 7 VDPSUP 0 bit 6 TRSVSEL 0 bit 5 OIF1 0 bit 4 bit 3 OIF0 LIMIT601 Default Value 0 0 bit 2 OFORM2 0
Default Value : 0x00
bit 1 OFORM1 0 bit 0 OFORM0 0
[TRSVSEL] bit This is a control bit to specify V-bit handling in the Rec 656 EAV / SAV code.
NTSC(525Lines) V-bit PAL(625Lines)
TRSVSEL = 0 Based on ITU-R Bt.656-3
Line10 ~ Line263 Line273 ~ Line525 Line1 ~ Line9 Line264 ~ Line272
TRSVSEL = 1 Based on ITU-R Bt.656-4 and SMPTE125M
Line20 ~ Line263 Line283 ~ Line525 Line1 ~ Line19 Line264 ~ Line282
TRSVSEL = 0
TRSVSEL = 1
V-bit = 0 V-bit = 1
Line23 ~ Line310 Line336 ~ Line623 Line1 ~ Line22 Line311 ~ Line335 Line624 ~ Line625
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(4) Field Signal Output The field signal can be output on VD / VAF /FIELD signal output pin. Output signal selection between VD / VAF signal and FIELD signal is done by Control 1 Register (Sub Address 0x03).
Pin output and Field relation:
FIELD Signal State Low High Field Information Odd Even
The value of the Field signal is determined during DVALID active. The Field signal does not directly reflect the input field, but it is a field signal which is forced to toggle at each VSYNC signal. Therefore, even when Odd Field or Even Field only signal is input, the Field signal also toggles. Switching Timing between Field signal and VD signal: NTSC
Digital Line-No. HD VD FIELD 525 1 2 3 4 5 6 7 8 9 10
Digital Line-No. HD VD FIELD
262
263
264
265
266
267
268
269
270
271
272
PAL
Digital Line-No. HD VD FIELD 622 623 624 625 1 2 3 4 5 6 7
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Digital Line-No. HD VD FIELD
310
311
312
313
314
315
316
317
318
319
320
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Variable Frame Rate Function
The AK8856 can vary the output frame rate. The frame rate can be selected by the [FRMRT1 : FRMRT0] bits of
Control 2 Register (R/W) [Sub Address0x04]
NTSC : 30 / 15 / 7.5 [fps] PAL : 25 / 12.5 / 6.25 [fps] Output timing is illustrated here. ( indicates "active")
QVGA, CIF, QCIF, Rotated QVGA, Rotated CIF
Field DVALID(ODEV DVALID(ODEV DVALID(ODEV DVALID(ODEV DVALID(ODEV DVALID(ODEV
0,30fps) 1,30fps) 0,15fps) 1,15fps) 0,7.5fps) 1,7.5fps)
VGA,601
Field DVALID(30fps) DVALID(15fps) DVALID(7.5fps
Note 1: These diagrams are typical for OFORM and OIF modes. Note 2: When OIF [1:0] = 2'b 10 is set, VD pulse is not output at the default setting. However, HD pulse and DVALID signal are output at the FIELD (Frame) where video is not output. In this case, the data is Black level data (Y : 0x10, Cb / Cr : 0x80). In order to output VD pulse in this mode, set the VDPSUP-bit of Output Control 1 Register (R/W) [Sub Address 0x01]. Note 2: When OIF [1:0] = 2'b 10 is set, VD pulse is not output at the default setting. However, HD pulse and DVALID signal are output at the FIELD (Frame) where video is not output. In this case, the data is Black level data (Y : 0x10, Cb / Cr : 0x80). In order to output VD pulse in this mode, set VDPSUP-bit of Output Control 1 Register (R/W) [Sub Address 0x01]. Note 3: In VGA or 601 mode, ODEV setting does not affect output. Note 4: When Vertical Sync is disturbed during switching signals., this timing may not be valid.
Setting of [VDPSUP-bit] VDPSUP-bit condition
0 1
VD pulse output
To output VD pulse during Active Frames only. To output VD pulse even at other than Active Frames.
Note
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Digital Pixel Interpolator
The Digital Pixel Interpolator is used to align vertical pixels (the interpolation block used is not compatible with the AK8855/AK8880. The AK8856 Interpolator is the same one used for theAK8851).
YC Delay
YC delay time is adjustable. In tuner output mode, there is a condition where the C signal is delayed from the Y signal. The adjustable YC Delay function is effective for this condition. The delay amount is adjustable with a single, internal processing clock unit. The setting is in 2's complement format. The delay amount is adjusted by setting the YC Delay Control Register (R/W) [Sub Address 0x0B]. Sub Address 0x0B
bit 7 Reserved 0 bit 6 Reserved 0 bit 5 Reserved 0 bit 4 bit 3 Reserved Reserved Default Value 0 0 bit 2 YCDELAY2 0
Default Value : 0x00
bit 1 YCDELAY1 0 Note Delay amount depends on the selected output mode. VGA/QVGA/QVGA Rotated/CIF Rotated : 12. 2727 MHz 601/CIF/QCIF : 13.5 MHz Delay amount is based on the selected clock mode. bit 0 YCDELAY0 0
YCDELAY2 :YCDELAY0 101 110 111 000 001 010 011
Delay amount Y is delayed from C by 3 clock cycles Y is delayed from C by 2 clock cycles Y is delayed from C by 1 clock cycles No delay between Y and C Y is advanced from C by 1 clock cycles Y is advanced from C by 2 clock cycles Y is advanced from C by 3 clock cycles
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Notification Function of Internal Conditions
The AK8856 has a Status Register (R/W) [Sub Address 0x10] to notify externally the AK8856 internal condition. Bit allocation of Status Register is as follows. Sub Address 0x10
bit 7 VBWSSDET bit 6 EXTDET bit 5 CCDET bit 4 AGCSTS bit 3 VLOCKSTS bit 2 PKWHITE bit 1 COLKILST bit 0 NSIG
(1) No Signal Decision The AK8856 detects when no signal input is present. When there is no input signal, the data output goes to Black level output (Y = 0x10, Cr / Cb = 0x80). This result is flagged by the output pin NSIG and the [NSIG] bit of Status Register. The output logical state is:
Signal condition With signal input No signal input [NOSIG] bit 0 1 NSIG pin 0 1
(2) COLKILST This indicates that the Color Killer Function has been activated, since the color signal level is very small.
[COLKIL]-bit 0 1 Input level Normal signal Color Killer is enabled Condition
(3) Input Level Overflow Notification Function This function is activated when the numerical result of the luminance signal exceeds 255. [PKWHITE] bit When an overflow of the luminance signal is detected, this bit is set to "1".
[PKWHITE]- bit 0 1 Input level Input signal overflow occurred No input overflow occurred Condition
(4) Color PLL Status This indicates a PLL lock condition with the input Color Burst signal. [CPLLLCK] bit
[CPLLLCK] bit 0 1 Input level Locked with input Color Burst signal Not locked with input Color Burst signal Condition
(5) AGC Status This indicates the status of adaptive AGC. [AGCSTS] bit
[AGCSTS]-bit 0 1 Input level Operating in Sync AGC Operating in Peak AGC Condition
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No Input Signal Condition
Two output modes can be selected when no Video signal is input to the AK8856. The default value is Black code output. This is set by the NSIGMD-bit of Output Control 2 Register (R/W) [Sub Address 0x02]. Detection of a no signal condition is indicated by a hardware pin and the Status Register (R / W) [Sub Address 0x10]. [NSIGMD] bit This sets the output signal when no input signal is detected.
[NSIGMD]-bit 00 01 10 11 Output signal when no signal is input Black code output Blue back output Input signal is directly output as is. Reserved Y = 0x10 Cb/Cr = 0x80 So-called " Sand-Storm " mode output. Condition
Power-Down Mode
The AK8856 has a power-saving wait mode function. The PDN pin is used to put the AK8856 into power-saving mode, including the digital block. By setting this pin low, all blocks in the analog and digital blocks are put into power-saving mode. After recovering from power-saving mode by resetting the PDN pin, a reset sequence must be executed. When reducing power supplies (except PVDD), a power-down sequence must be followed by setting the PDN pin and then reducing AVDD and DVDD after the power-down condition is established. During power-down mode, digital output pins should be tied to the PVDD power supply, or set the OE pin = high (high output).
Output Pin Condition
Output pins of the AK8856 are controlled by the OE (Output Enable) pin and RSTN pin conditions. Output pin conditions:
After Power up OE = High OE = Low unknown Hi-z RSTN = Low Hi-z Hi-z After Reset Sequence PDN = Low PDN = High High Data output Hi-z Hi-z
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[AK8856 Preliminary Data Sheet]
Device Control Interface
The AK8855 is controlled through an I2C Bus Control Interface. [I2C SLAVE Address] I2C Slave Address is 0x88 [I2C Control Sequence] (1) Write Sequence When the Slave Address of the AK8856 Write Mode is received at the first byte, Sub Address at the second byte and Data at the third and succeeding bytes are received. There are two operations in the Write Sequence - a sequence to write at every single byte, and a sequential write operation to write multiple bytes successively.
(a) 1 Byte Write Sequence
S Slave Address 8-bits W A 1bit
Sub Address 8-bits
A 1bit
Data 8-bits
A 1bit
Stp
(b) Multiple Bytes ( m-bytes ) Write Sequence ( Sequential Write Operation )
S Slave Address 8-bits w A 1bit
Sub Address(n) 8-bits
A 1bit
Data(n) 8-bits
A 1bit
Data(n+1) 8-bits
A 1bit
---
Data(n+m) 8-bits
A 1bit
stp
(2) Read Sequence
When the Slave Address of the AK8855 Read mode is received, Data at the second and succeeding bytes are transmitted.
S Slave Address 8-bits
w A
Sub Address(n) 8-bits
A
rS
Slave Address 8-bits
R
A
Data1 8-bits
A
Data1 8-bits
A
Data2 8-bits
A
---
Data n 8-bits
stp
1
1
1
1
1
1
1
Note ) At Sequential Read Operation, the first byte Read-out Data is repeatedly output (this does not occur in a normal, single byte Read operation).
Abbreviated terms listed in the tables : S, rS A Astp R/W : Start Condition : Acknowledge (SDA Low) : Not Acknowledged (SDA High) : Stop Condition 1 : Read 0 : Write : Controlled by the Master Device; micro-computer interface is output. : Controlled by the Slave Device; output by the AK8856.
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[AK8856 Preliminary Data Sheet]
Register Definition
Sub Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 Register Input video standard register Output control 1 register Output control 2 register Control 1 register Control 2 register PGA control register Contrast control register Brightness control register Saturation control register HUE control register Request VBI info register YC Delay control register Status register Macrovision status register Closed caption 1 register Closed caption 2 register Extended data 1 register Extended data 2 register VBID/WSS 1 register VBID/WSS 2 register Device & revision ID & mode status register Default 0x00 0x00 0x00 0x00 0x00 0x15 0x80 0x00 0x80 0x00 0x0A 0x00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R R R R R R R R 0x80 R Function Sets standard input signal Sets output picture size Sets output pin characteristics Sets YC separation, color killer, AGC, VD field Sets AGC, color killer, frame rate, contrast mode Sets PGA parameters Sets contrast level
Sets brightness level Sets saturation level Sets Hue level Requests VBI information
Controls YC delay Status register Macrovision Status register Closed Caption Data 1 register Closed Caption Data 2 register Closed Caption Extended Data 1 register Closed Caption Extended Data 2 register VBID ( CGMS-A ) / WSS1 Data register VBID ( CGMS-A ) / WSS 2 Data register Device & Revision ID register
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Input Video Standard Register (R/W) [Sub Address 0x00] Sets input signal Sub Address 0x00
bit 7 Reserved 0 bit 6 Reserved 0 bit 5 Reserved 0 bit 4 bit 3 AINSEL VLF Default Value 0 0 bit 2 VCEN 0
Default Value : 0x00
bit 1 VSCF1 0 bit 0 VSCF0 0
Input Video Standard Register Definition
BIT Register Name R/W Definition Sets Sub-carrier frequency of input video signal bit 0 ~ bit 1 VSCF0 ~ VSCF1 Sub carrier Frequency R/W VSCF1 - VSCF0 [MHz] 00 : 3.57954545 01 : 3.57561188 10 : 3.5820558 11 : 4.43361875 Sets Color Encoding System of input video signal 0: NTSC 1: PAL to set Line Frequency of input video signal. 0 : 525 Lines 1 : 625 Lines to select AIN Input Select switch. 0: to decode AIN 1 1: to decode AIN 2 Reserved
bit 2
VCEN
Video Color Encode
R/W
bit 3
VLF
Video Line Frequency
R/W
bit 4 bit 5 ~ bit 7
AINSEL
AIN Select bit
R/W
Reserved
Reserved
R/W
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[AK8856 Preliminary Data Sheet]
Output Control 1 Register (R/W) [Sub Address 0x01] Sub Address 0x01
bit 7 VDPSUP 0 bit 6 TRSVSEL 0 bit 5 OIF1 0 bit 4 bit 3 OIF0 LIMIT601 Default Value 0 0 bit 2 OFORM2 0
Default Value : 0x00
bit 1 OFORM1 0 bit 0 OFORM0 0
Output Control 1 Register Definition
BIT Register Name R/W Definition Set output picture size: OFORM[2:0] 000: QVGA 001: VGA ( interlaced output ) 010: CIF 011: QCIF 100: rotated QVGA ( 240 X 180 ) 101: rotated CIF ( 288 X 216 ) 110: 601 output 111: Reserved Sets Minimum / Maximum limit for output data: 0 : 1-254 (Y/Cb/Cr) 1 : 16-235 (Y) / 16-240 (Cb/Cr) when "1" is set in the LIMIT601 register, data smaller than 16 is clipped to 16 and data larger than 235 / 240 ( Y / Cb, Cr ) is clipped to 240. Sets output interface mode: 00: Camera Interface mode (without SAV / EAV) 01: Camera Interface mode (with SAV / EAV) 10: HD / VD mode 11: 656 Interface mode In modes 01 / 11, HD / VD output is fixed low. Switches shift line of V-bit of EAV / ASAV which is included in TRS: This register is valid when OFORM [ 2:0 ] = 110. NTSC system (525 line input) TRSVSEL=0 : V = 1 when Line 1 ~ Line 9 / Line 264 ~ Line 272 V = 0 when Line 10 ~ Line 263 / Line 272 ~ Line 525 TRSVSEL=1: V = 1 when Line 1 ~ Line 19 / Line 264 ~ Line 282 V = 0 when Line 20 ~ Line 263 / Line 283 ~ Line 525 PAL system (625 line input) Regardless of the set value of the TRSVSEL bit, V = 1 when Line 1 ~ Line 22 / Line 311 ~ Line 355 / Line 624 ~ Line 625 V = 0 when Line 23 ~ Line 310 / Line 336 ~ Line 623 When Frame Rate Variable Function is activated in HD / VD mode and 656 I / F mode, 0 : VD / VAF pulse is not output at the frames that are not active. 1 : VD / VAF pulse is output even at the Frames which are not active. 2006/Dec
bit 0 ~ bit 2
OFORM0 ~ OFORM2
Output Format Set bit
R/W
bit 3
LIMIT601
601 Output Limit
R/W
bit 4 ~ bit 5
OIF0 ~ OIF1
Output interface set bit
R/W
bit 6
TRSVSEL
Time Reference Signal V Select bit
R/W
bit 7
VDPSUP
VD Pulse SUPress
R/W
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Output Control 2 Register (R/W) [Sub Address 0x02] Sets polarity of output pin and to set output condition when no input signal is fed. Functional modification has been made on bit 7 of this register from the AK8855. Sub Address 0x02 Default Value: 0x00
bit 7 NSIGMD1 0 bit 6 NSIGMD0 0 bit 5 DVALACT 0 bit 4 bit 3 HVACT CLKINV Default Value 0 0 bit 2 DVALIDP 0 bit 1 VDP 0 bit 0 HDP 0
Output Control 2 Register Definition
BIT bit 0 Register Name HDP HD pin Polarity set bit R/W R/W Definition Sets polarity of HD signal: 0: Active Low 1: Active High Sets polarity of VD signal: 0: Active Low 1: Active High Sets polarity of DVALID signal: 0: Active Low 1: Active High Sets polarity of CLKO: 0: normal output (data should be taken at the rising edge) 1: phase relation between data and clock is inverted (data should be taken at the falling edge). Outputs HD & VD in EAV / SAV Interface mode: no output ( fixed to low ) 1 : to output Outputs DVALID signal in EAV / SAV Interface mode: 0: no output ( fixed to low ) 1: to output Sets output condition when no signal input condition is detected: 00 : Output Black level 01 : Output Blue level (Blue back) 10 : Output input condition directly as is(" SandStorm " condition). 11 : Reserved
bit 1
VDP
VD pin Polarity set bit
R/W
bit 2
DVALDP
DVALID pin Polarity set bit
R/W
bit 3
CLKINV
CLK invert set bit
R/W
bit 4
HVACT
HD/VD action bit
R/W
bit 5
DVALACT
DVALID action bit
R/W
bit 6 ~ bit 7
NSIGMD0 ~ NSIGMD1
No SiGnal Output MoDe
R/W
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Control 1 Register (R/W) [Sub Address 0x03] Control Register Sub Address 0x03
bit 7 Reserved 0 bit 6 VDFLD 0 bit 5 AGCTR 0 bit 4 bit 3 AGCC1 AGCC0 Default Value 0 0 bit 2 CKILSEL1 0
Default Value: 0x00
bit 1 CKILSEL0 0 bit 0 YCSEP 0
Control 1 Register Definition
BIT Register Name R/W Definition Selects YC separation method: Operation of YC separation is fixed by a selected input signal type and output data size. For NTSC & QVGA,CIF,QCIF, QVGAL,CIFL: 0 : primary YC separation (AK8855 compatible) 1 : Y by primary YC separation filter and C by two dimensional YC separation filter Sets " ON " condition of Color-Killer: 00 : when at [01] condition or at [10] condition 01 : locked Color Decode PLL becomes out-of-lock condition. 10 : Color Burst signal level becomes lower than approximately -23 dB. 11 : Reserved Sets AGC Coring level 00 : +/_ 2 LSB Coring level 01 : +/_ 3 LSB Coring level 10 : +/_ 4 LSB Coring level 11 : no Coring level Sets transient conditions of Sync AGC and Peak AGC: 0 : Quick 1 : Slow Sets the type of output signal on VD / VAF / FIELD pin: VAF signal is always output on this pin in Camera interface mode. 0 : VD / VAF signal is output 1 : FIELD signal is output
bit 0
YCSEP
YC Separation Set bit
R/W
bit 1 ~ bit 2
CKILSEL0 ~ CKILSEL1
Color killer Select bit
R/W
bit 3 ~ bit 4
AGCC0 ~ AGCC1
AGC Coring Level
R/W
bit 5
AGCTR
AGC Transient Level
R/W
bit 6
VDFLD
VD Field Select bit
R/W
bit 7
Reserved
Reserved bit
R/W
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[AK8856 Preliminary Data Sheet]
Control 2 Register (R/W) [Sub Address 0x04] Control Register Sub Address 0x04
bit 7 CNTSEL 0 bit 6 NSIGDEF 0 bit 5 ODEV 0 bit 4 bit 3 FRMRT1 FRMRT0 Default Value 0 0 bit 2 COLKIL 0
Default Value: 0x00
bit 1 ACC 0 bit 0 AGC 0
Control 1 Register Definition
BIT bit 0 bit 1 bit 2 Register Name AGC ACC COLKIL AGC set bit ACC set bit Color Killer Set bit R/W R/W R/W R/W Definition 0 : AGC Disable (PGA manual setting is enabled ) 1 : AGC Enable 0 : ACC Disable 1 : ACC Enable 0 : Color Killer enabled 1 : Color Killer disabled Sets Frame Rate [Frames / sec] FRMRT 1:0 (525 / 625) 00: 30/25 01: 15/12.5 10: 7.5/6.25 11: Reserved Sets decode field for QVGA / CIF / QCIF decoding: 0 : Decode Odd Field 1 : Decode Even Field Sets NSIG pin output condition. 0 : when both Horizontal and Vertical synchronizations lose sync, NSIG goes high (output shifts to self-running mode) 1 : when Vertical synchronization loses sync, NSIG goes high Sets the start point for contrast adjustment 0 : Contrast varies, starting at Luminance level of 128 (gray) as a center value 1 : Contrast varies, starting at Luminance level of 16 (black) as a center value
bit 3 ~ bit 4
FRMRT0 ~ FRMRT1
Frame Rate Set bit
R/W
bit 5
ODEV
ODD Even Select bit
R/W
bit 6
NSIGDEF
NSIG Define Mode
R/W
bit 7
CNTSEL
Contrast mode select bit
R/W
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PGA Control Register (R/W) [Sub Address 0x05] Sets PGA gain; when the AGC function is enabled, the gain value for the AGC is set by this register. Sub Address 0x05
bit 7 Reserved 0 bit 6 PGA6 0 bit 5 PGA5 0 bit 4 bit 3 PGA4 PGA3 Default Value 1 0 bit 2 PGA2 1
Default Value: 0x15
bit 1 PGA1 0 bit 0 PGA0 1
PGA Control Register Definition
BIT bit 0 ~ bit 6 bit 7 Register Name PGA0 ~ PGA6 Reserved R/W PGA Gain Set Reserved R/W R/W Definition Sets gain of PGA: PGA can be adjusted in approximately 0.1 dB / step. Reserved
Note) When reading this register while the AGC is enabled, the PGA value which is set by AGC is returned. It is possible for the user to write a value (user-set-value) while the AGC is enabled, but its value is not written to the PGA. A returned value from the register read operation is the same AGC set value. When the AGC is disabled, the user-set-value is valid, and its value is returned by a Register Read operation.
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Contrast Control Register (R/W) [Sub Address 0x06] This register is for Contrast Adjustment, and the default value (no adjustment) is 0x80. Sub Address 0x06
bit 7 CONT7 1 bit 6 CONT6 0 bit 5 CONT5 0 bit 4 bit 3 CONT4 CONT3 Default Value 0 0 bit 2 CONT2 0
Default Value: 0x80
bit 1 CONT1 0 bit 0 CONT0 0
Contrast Control Register Definition
BIT bit 0 ~ bit 7 Register Name CONT0 ~ CONT7 Contrast Control R/W Definition Contrast Adjustment: resolution is 1 / 256 step and the range is from 0 to 255 / 128. Default value is 0x80.
R/W
Brightness Control Register (R/W) [Sub Address 0x07] This register is for Brightness Adjustment and the default value (no adjustment) is 0x00. Sub Address 0x07
bit 7 BR7 0 bit 6 BR6 0 bit 5 BR5 0 bit 4 bit 3 BR4 BR3 Default Value 0 0 bit 2 BR2 0
Default Value: 0x00
bit 1 BR1 0 bit 0 BR0 0
Brightness Control Register Definition
BIT bit 0 ~ bit 7 Register Name BR0 ~ BR7 R/W Brightness Control R/W Definition Brightness Adjustment: Two's complement format
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Saturation Control Register (R/W) [Sub Address 0x08] This register is for Color Saturation Adjustment, and the default value (no adjustment) is 0x80. Sub Address 0x08
bit 7 SAT7 1 bit 6 SAT6 0 bit 5 SAT5 0 bit 4 bit 3 SAT4 SAT3 Default Value 0 0 bit 2 SAT2 0
Default Value: 0x80
bit 1 SAT1 0 bit 0 SAT0 0
Saturation Control Register Definition
BIT bit 0 ~ bit 7 Register Name SAT0 ~ SAT7 R/W Definition Saturation Adjustment: resolution is 1/256 step and the range is from 0 to 255/128. SAT7:SAT0 0 : 0 x (no color exists) 0xff : 255/128 x 0xff : 255/128 x
Saturation Control
R/W
HUE Control Register (R/W) [Sub Address 0x09] This register is for Hue Adjustment, and the default value (no adjustment) is 0x00. Sub Address 0x09
bit 7 HUE7 0 bit 6 HUE6 0 bit 5 HUE5 0 bit 4 bit 3 HUE4 HUE3 Default Value 0 0 bit 2 HUE2 0
Default Value: 0x00
bit 1 HUE1 0 bit 0 HUE0 0
HUE Control Register Definition
BIT bit 0 ~ bit 7 Register Name HUE0 ~ HUE7 HUE Control R/W R/W Definition Hue adjustment: two's complement format. Default value is 0x00. Resolution is 1/256 step (approximately 0.35 / step ), with a range of 45.
MS0522-E-00
88
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Request VBI Info Register (W) [Sub Address 0x0A] This register is used to decode VBLANK information, including Closed Caption Data, Extended Data, VBID (CGMS), and WSS Data. When a "1" is written to the decode request bit for VBLANK information, the AK8856 is put into Data Decode Ready state and waits for Data. After decoding is completed, a "1" is written to the CCDET bit, the EXTDET bit, and the VBWSSDET bit. These bits correspond to a Status Register ( R / W ) [ Sub Address 0x10] request, and decoded data are written to the Closed Caption Data 1 / 2 Registers, Extended Data 1 / 2 Registers and VBID / WSS Data 1/ 2 Registers respectively. Sub Address 0x0A
bit 7 Reserved 0 bit 6 Reserved 0 bit 5 Reserved 0 bit 4 bit 3 Reserved Reserved Default Value 0 0 bit 2 VBWSRQ 0
Default Value: 0x00
bit 1 EXTRQ 0 bit 0 CCRQ 0
Request VBI Info Register Definition
BIT bit 0 Register Name CCRQ Closed Caption Data Decode Request Extended Request Data Decode R/W W Definition Request decoding of Closed Caption Data 0:1 : decode request Request decoding of Extended Data 0:1 : decode request Request decoding of VBID / WSS Data 0:1 : decode request Reserved
bit 1
EXTRQ
W
bit 2 bit 3 ~ bit 7
VBWSRQ
VBID Data Decode Request
W
Reserved
Reserved
W
Note) When a "1" is written to the RQ-bit, CCDET, EXTDET, and VBWSSDET bits are cleared to "0", which corresponds to a Status Register Request.
MS0522-E-00
89
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
YC Delay Control Register (R/W) [Sub Address 0x0B] YC Delay Control Register Definition Sub Address 0x0B
bit 7 Reserved 0 bit 6 Reserved 0 bit 5 Reserved 0 bit 4 bit 3 Reserved Reserved Default Value 0 0 bit 2 YCDELAY2 0
Default Value : 0x00
bit 1 YCDELAY1 0 bit 0 YCDELAY0 0
YC Delay Control Register Definition
BIT Register Name R/W Definition Adjusts amount of Y/C output delay; Delay amount depends on the selected output mode. VGA/QVGA/QVGA Rotated/CIF Rotated : 12.2727MHz clock cycles per each one delay (81.5ns) 601/CIF/QCIF : 13.5MHz sample clock cycles per each one delay ( 74 ns) YCDELAY2 : YCDELAY0 101 : Y is delayed from C by 3 clock cycles 110 : Y is delayed from C by 2 clock cycles 111 : Y is delayed from C by 1 clock cycles 000 : no delay between Y and C 001 : Y is advanced from C by 1 clock cycles 010 : Y is advanced from C by 2 clock cycles 011 : Y is advanced from C by 3 clock cycles Reserved
bit 0 ~ bit 2
YCDELAY0 ~ YCDELAY2
Y/C Delay Control
R/W
bit 3 ~ bit 7
Reserved
Reserved bit
R/W
MS0522-E-00
90
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Status Register (R/W) [Sub Address 0x10] Register to indicate internal conditions of the AK8856. Sub Address 0x10
bit 7 VBWSSDET bit 6 EXTDET bit 5 CCDET bit 4 AGCSTS bit 3 VLOCKSTS bit 2 PKWHITE bit 1 COLKILST bit 0 NSIG
Status Register Definition
BIT bit 0 Register Name NOSIG No Signal R/W R Definition Detects presence of input signal. 0 : signal is being input 1 : no signal input condition Status of Color Killer 0 : Color Killer is in-active 1 : Color Killer process is active Detects input overflow by monitoring output of ADC 0 : normal 1 : input level overflow VLOCK status 0 : VLOCK is properly operating 1 : VLOCK is out-of-lock condition 0 : Sync AGC operation 1 : Peak AGC operation Detects presence of decoded Closed Caption data in the Closed Caption 1/2 registers 0 : no Closed Caption Data exists 1 : decoded Closed Caption Data exists Detects decoded data in Extended Data 1/2 Registers 0 : no Extended Data exists 1 : decoded Extended Data exists Detects decoded data in VBID/WSS Data 1/2 Registers. 0 : no VBID / WSS data exists 1 : decoded VBID / WSS data exists
bit 1
COLKILST
Color killer
R
bit 2
PKWHITE
Peak White Detection
R
bit 3 bit 4
VLOCKSTS AGCSTS
VLOCK Status bit AGC Status bit
R R
bit 5
CCDET
Closed Caption Detect
R
bit 6
EXTDET
Extended Data Detect
R
bit 7
VBWSDET
VBID / WSS Data Detect
R
MS0522-E-00
91
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Macrovision Status Register (R/W) [Sub Address 0x11] Displays result of Macrovision signal detection. Sub Address 0x11
bit 7 Reserved bit 6 PSPDET bit 5 AGCPDET bit 4 BPPDET bit 3 SYNCRED bit 2 CSTYPE bit 1 CSDET bit 0 AGCDET
Macrovision Status Register Definition
BIT bit 0 Register Name AGCDET AGC Process Detect R/W R Definition Detects Macrovision AGC Process in input signal. 0 : no Macrovision AGC Process detected 1 : Macrovision AGC Process detected Detects Macrovision Color Stripe Process in input signal. 0 : no Color Stripe process 1 : Color Stripe process is detected Displays types of Color Stripe in input signal 0 : Color Stripe Type 2 1 : Color Stripe Type 3 Detects Sync Reduction 0:1 : Sync Reduction is detected Detects end of Field Back Porch Pulse 0:1 : end of Field Back Porch Pulse is detected Detects AGC Pulse 0:1 : AGC Pulse is detected Detects Pseudo Sync Pulse 0:1 : Pseudo Sync Pulse is detected Reserved
bit 1
CSDET
Color Stripe Detect
R
bit 2
CSTYPE
Color Stripe Type
R R
bit 3
SYNCRED
Sync Reduction bit
bit 4
BPPDET
Back Porch Pulse Detect bit
R
bit 5
AGCPDET
AGC Pulse Detect bit
R
bit 6 bit 7
PSPDET Reserved
Pseudo Sync Pulse Detect bit Reserved bit
R R
MS0522-E-00
92
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Closed Caption 1 Register (R) [Sub Address 0x12] Register to store Closed Caption Data. Sub Address 0x12
bit 7 CC7 bit 6 CC6 bit 5 CC5 bit 4 CC4 bit 3 CC3 bit 2 CC2 bit 1 CC1 bit 0 CC0
Closed Caption 2 Register (R) [Sub Address 0x13] Register for storing Closed Caption Data. Sub Address 0x13
bit 7 CC15 bit 6 CC14 bit 5 CC13 bit 4 CC12 bit 3 CC11 bit 2 CC10 bit 1 CC9 bit 0 CC8
Extended Data 1 Register (R) [Sub Address 0x14] Register for storing Closed Caption Extended Data. Sub Address 0x14
bit 7 EXT7 bit 6 EXT6 bit 5 EXT5 bit 4 EXT4 bit 3 EXT3 bit 2 EXT2 bit 1 EXT1 bit 0 EXT0
Extended Data 2 Register (R) [Sub Address 0x15] Register for storing Closed Caption Extended Data. Sub Address 0x15
bit 7 EXT15 bit 6 EXT14 bit 5 EXT13 bit 4 EXT12 bit 3 EXT11 bit 2 EXT10 bit 1 EXT9 bit 0 EXT8
VBID/WSS 1 Register (R) [Sub Address 0x16] Register for storing VBID data and to store WSS data. Sub Address 0x16
bit 7 Reserved Reserved bit 6 Reserved Reserved bit 5 VBID1 G4-13 bit 4 VBID2 G4-12 bit 3 VBID3 G4-11 bit 2 VBID4 G3-10 bit 1 VBID5 G3-9 bit 0 VBID6 G3-8
VBID/WSS 2 Register (R) [Sub Address 0x17] Register for storing VBID data and to store WSS data. Sub Address 0x17
bit 7 VBID7 G2-7 bit 6 VBID8 G2-6 bit 5 VBID9 G2-5 bit 4 VBID10 G2-4 bit 3 VBID11 G1-3 bit 2 VBID12 G1-2 bit 1 VBID13 G1-1 bit 0 VBID14 G1-0
MS0522-E-00
93
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Device & Revision ID Register (R) [Sub Address 0x18] Register displays Device ID & Revision of the AK8856. Device ID of the AK8856 is 56 in decimal. (0x38 at Hexadecimal) Initial Version of the Revision ID is 0x00. Revision number is modified only when the control software needs to be modified. Sub Address 0x18
bit 7 Rev1 0 bit 6 REV0 0 bit 5 DEV5 1 bit 4 DEV4 1 bit 3 DEV3 1 bit 2 DEV2 0
Default Value 0x38
bit 1 DEV1 0 bit 0 DEV0 0
Revision Register Definition
BIT bit 0 ~ bit 5 bit 6 ~ bit 7 Register Name DEV0 ~ DEV5 REV0 ~ REV1 R/W Revision bit R to show Device ID Device ID is 0x38h. to show Revision information REV1 - REV0 Initial version is 0x00 Definition
Device ID
R
MS0522-E-00
94
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
System Connection Example
I/O =PVDD 1.8V PVDD 1.8V
pull
up
Micro Processor 2 (I C Controller)
PVDD 1.8V SDA SCL RSTN PDN Video IN
39 0.033uF
OE PVDD
0.1uF 10uF
AIN1 AIN2
39
IREF VRP VCOM VRN 6.8k
0.1u 0.1u 0.1u
DATA[7..0] NSIG DTCLK DVALID HD/HV VD/VAF
AK8856
LPF 27MHz XTI 22pF XTO 22pF Analog 1.8V
TEST0 TEST1
TEST2
Digital 1.8V AVDD AVSS DVSS DVDD
10uF
0.1uF
0.1uF
10uF
Analog GND
Digital GND
MS0522-E-00
95
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Package Drawing
7.200.10 7.000.05 A
7.200.10
7.000.05
48
1
0.5
0.75
0.220.05 0.25
+0.40 -0.15
0.05 M
0.75 5 AB 3-0.50 -0.15
+0.40
45
45 45
45
0.170.05
0.92 0.08 (Note1)
0.005Min, 0.04Max
S
0.02 (Typ.)
OUTER LEAD [N.T.S] 0.350.12 Note1. These Dimensions Include Package BEND 0.05 S
Material : Plating Package molding compound: Epoxy Interposer material: BT resin Solder ball material: SnAgCu
MS0522-E-00
0.170.05
0.5
Index
B
96
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Package Marking Drawing
AKM
AK8856VN XXXXXXX
a. Package type
: QFN
b. Number of pins c. Product number d. Control Code
: 48 pins : AK8856VN : xxxxxxx ( 7 digit number )
MS0522-E-00
97
2006/Dec
ASAHI KASEI
[AK8856 Preliminary Data Sheet]
IMPORTANT NOTICE
* These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0522-E-00
98
2006/Dec

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