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CY8C20110
CapSenseLITE - 10 Configurable IOs
Features
Overview
The CapSenseLITE controller allows the control of ten IOs configurable as capacitive sensing buttons or as GPIOs for driving LEDs or interrupt signals based on various button conditions. The GPIOs are also configurable for waking up the device from sleep based on an interrupt input. The user has the ability to configure buttons, outputs, and parameters, through specific commands sent to the I2C port. The IOs have the flexibility in mapping to capacitive buttons and as standard GPIO functions such as interrupt output or input, LED drive and digital mapping of input to output using simple logical operations. This enables easy PCB trace routing and reduces the PCB size and stack up. CapSenseLITE products are designed for easy integration into complex products.
Ten configurable IOs supporting CapSense buttons LED drive Interrupt outputs WAKE on interrupt input User defined input/output 2.4V to 5.25V operating voltage Industrial temperature range: -40C to +85C I2C slave interface for configuration Reduce BOM cost Internal oscillator - no external oscillators or crystal Free development tool - no external tuning components Low operating current Active current: continuous sensor scan - 1mA Sleep current: no scan, continuous sleep - 2.6uA Available in 16-pin QFN and 16-pin SOIC packages

Architecture
The logic block diagram illustrates the internal architecture of CY8C20110. The user is able to configure registers with parameters needed to adjust the operation and sensitivity of the CapSense system. CY8C20110 supports a standard IC serial communication interface that allows the host to configure the device and to read sensor information in real time through easy register access.
The CapSenseLITE Core
The CapSenseLITE Core has a powerful configuration and control block. It encompasses SRAM for data storage, an interrupt controller, along with sleep and watchdog timers. System resources provide additional capability, such as a configurable I2C slave communication interface and various system resets. The Analog system contains the CapSense PSoC block and an internal 1.8V analog reference, which together support capacitive sensing of up to 10 inputs.
Cypress Semiconductor Corporation Document Number: 001-17345 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised November 22, 2007
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CY8C20110
Logic Block Diagram
External Vcc 2.4 - 5.25 CapSenseLITE Core 2KB Flash 512B SRAM 10 Configurable IOs
Document Number: 001-17345 Rev. *B
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CY8C20110
Pinouts
Figure 1. Pin Diagram - 16 QFN GP0[4] CSInt GP0[3] VDD
GP0[0] GP0[1] I2C SCL I2C SDA
GP0[2] XRES
GP1[4] GP1[3]
GP1[0] GP1[1] VSS Table 1. Pin Definitions - 16 QFN Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I Name GP0[0] GP0[1]
2C
GP1[2]
Description Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as Capsense or GPIO Active HIGH external reset with internal pull down Configurable as CapSense or GPIO Supply voltage Configurable as CapSense or GPIO Integrating Capacitor Input Configurable as CapSense or GPIO
SCL
I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD GP0[3] CSInt GP0[4]
Document Number: 001-17345 Rev. *B
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CY8C20110
Figure 2. Pin Diagram - 16 SOIC
GP0[3] CSInt GP0[4] GP0[0] GP0[1] I2CSCL I2CSDA GP1[0]
1 2 3 4 5 6 7 8
16 15 14
VDD GP0[2] XRES GP1[4] GP1[3] GP1[2] VSS GP1[1]
SOIC (Top View)
13 12 11 10 9
Table 2. Pin Definitions - 16 SOIC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I Name GP0[3] CSInt GP0[4] GP0[0] GP0[1]
2C
Description Configurable as CapSense or GPIO Integrating Capacitor Input Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Active HIGH external reset with internal pull down. Configurable as CapSense or GPIO Supply voltage
SCL
I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD
Document Number: 001-17345 Rev. *B
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CY8C20110
The CapSense Analog System
The CapSense analog system contains the capacitive sensing hardware. The CapSense Successive Approximation (CSA) algorithm is supported. This hardware performs capacitive sensing and scanning without external components. Capacitive sensing is configurable on each pin.
I2C Interface
The two modes of operation for the I2C interface are:

Device register configuration and status read or write for controller Command execution
Additional System Resources
System Resources provide additional capability useful to complete systems. Additional resources are low voltage detection and Power On Reset (POR).

The I2C address is programmable during configuration. It can be locked to prevent accidental change by setting a flag in a configuration register.
CapSenseLITE Software Tool
An easy to use software tool integrated with PSoC Express is available for configuring and tuning CapSenseLITE devices. Refer to the Application Note AN42137 for details of the software tool.
The I C slave provides 50, 100, or 400 kHz communication over two wires. Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels and the advanced POR circuit eliminates the need for a system supervisor.
2
An internal 1.8V reference provides an absolute reference for capacitive sensing.
Electrical Specifications
Absolute Maximum Ratings
Parameter TSTG Description Storage temperature Min -55 Typ 25 Max +100 Unit C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25C 25C. Extended duration storage temperatures above 65C degrades reliability.
TA VDD VIO VIOZ IMIO ESD LU
Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any GPIO pin Electrostatic discharge voltage Latch up current
-40 -0.5 VSS - 0.5 VSS - 0.5 -25 2000 -
- - - - - - -
+85 +6.0 VDD + 0.5 VDD + 0.5 +50 200
C V V V mA V mA Human body model ESD
Operating Temperature
Parameter TA TJ Description Ambient temperature Junction temperature Min -40 -40 Typ - - Max +85 +100 Unit C C Notes
Document Number: 001-17345 Rev. *B
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CY8C20110
DC Electrical Characteristics
DC Chip Level Specifications
Parameter VDD IDD ISB27 ISB Description Supply voltage Supply current Sleep mode current with POR and LVD active. Mid temperature range Sleep mode current with POR and LVD active. Min 2.40 - - - Typ - 1.5 2.6 2.8 Max 5.25 2.5 4 5 Unit V mA A A Conditions are Vdd = 3.0V, TA = 25C VDD = 2.55V, 0C < TA < 40C VDD = 3.3V, -40C < TA < 85C Notes
5V and 3.3V DC General Purpose IO Specifications
Parameter RPU VOH1 VOH2 VOH3 VOH4 VOH5 Description Pull up resistor High output voltage Port 0 pins High output voltage Port 0 pins High output voltage Port 1 pins High output voltage Port 1 pins High output voltage Port 1 pins with 3.0V LDO regulator enabled High Output Voltage Port 1 pins with 3.0V LDO regulator enabled High Output Voltage Port 1 pins with 2.4V LDO regulator enabled High Output Voltage Port 1 pins with 2.4V LDO regulator enabled Low output voltage Min 4 VDD - 0.2 VDD - 0.9 VDD - 0.2 VDD - 0.9 2.75 Typ 5.6 - - - - 3.0 Max 8 - - - - 3.2 Unit k V V V V V IOH < 10 A, Vdd > 3.0V, maximum of 20 mA source current in all IOs. IOH = 1 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 A, Vdd> 3.0V, maximum of 10 mA source current in all IOs. IOH = 5 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 A, Vdd> 3.1V, maximum of 4 IOs all sourcing 5mA. IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA source current in all IOs. IOH < 10 A, Vdd > 3.0V, maximum of 20 mA source current in all IOs. IOH < 200 A, Vdd > 3.0V, maximum of 20 mA source current in all IOs. V IOL = 20 mA, Vdd > 3V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[3]). Vdd = 3.6 to 5.25V. Vdd = 3.6 to 5.25V. Gross tested to 1 A. Package and pin dependent. Temp = 25C. Package and pin dependent. Temp = 25C. Notes
VOH6
2.2
-
-
V
VOH7
2.1
2.4
2.5
V
VOH8
2
-
-
V
VOL
-
-
0.75
VIL VIH VH IIL CIN COUT
Input low voltage Input high voltage Input hysteresis voltage Input leakage Capacitive load on pins as input Capacitive load on pins as output
- 2.0 - - 0.5 0.5
- - 140 1 1.7 1.7
0.8 - - - 5 5
V V mV nA pF pF
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CY8C20110
2.7V DC General Purpose IO Specifications
Parameter RPU VOH1 VOH2 VOH3 VOH4 VOL Description Pull up resistor High output voltage Port 0 Pins High output voltage Port 0 Pins High output voltage Port 1 Pins High output voltage Port 1 Pins Low output voltage Min 4 VDD - 0.2 VDD - 0.5 VDD - 0.2 VDD - 0.5 - Typ 5.6 - - - - - Max 8 - - - - 0.75 Unit k V V V V V IOH <10 A, maximum of 10 mA source current in all IOs. IOH = 0.2 mA, maximum of 10 mA source current in all IOs. IOH < 10 A, maximum of 10 mA source current in all IOs. IOH = 2 mA, maximum of 10 mA source current in all IOs. IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[3]). IOL=5mA Maximum of 50mA sink current on even port pins (for example, P0[2] and P1[4]) and 50mA sink current on odd port pins (for example, P0[1] and P1[3]). 2.4<=Vdd<=3.6V Vdd = 2.4 to 3.6V. Vdd = 2.4 to 2.7V. Vdd = 2.7 to 3.6V Gross tested to 1 A. Package and pin dependent. Temp = 25C. Package and pin dependent. Temp = 25C. Notes
VOLP1
Low Output Voltage Port 1 Pins
-
-
0.4
V
VIL VIH1 VIH2 VH IIL CIN COUT
Input low voltage Input high voltage Input high voltage Input hysteresis voltage Input leakage Capacitive load on pins as input Capacitive load on pins as output
- 1.4 1.6 - - 0.5 0.5
- - - 60 1 1.7 1.7
0.75 - - - - 5 5
V V V mV nA pF pF
DC POR and LVD Specifications
Parameter VPPOR0 VPPOR1 Description VDD Value PPOR Trip VDD= 2.7V VDD= 3.3V,5V VDD Value for LVD trip VDD= 2.7V VDD= 3.3V VDD= 5V Min - - Typ 2.36 2.60 Max 2.40 2.65 Unit V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog.
VLVD0 VLVD2 VLVD6
2.39 2.75 3.98
2.45 2.92 4.05
2.51 2.99 4.12
V V V
Document Number: 001-17345 Rev. *B
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CY8C20110
AC Electrical Characteristics
5.0V and 3.3V AC General Purpose IO Specifications Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload = 50pF, Port 0 Rise time, strong mode, Cload = 50pF, Port 1 Fall time, strong mode, Cload = 50pF, all ports Min 15 10 10 Max 80 50 50 Unit ns ns ns Notes Vdd = 3.0V to 3.6V and 4.75V to 5.25V, 10% - 90% Vdd = 3.0V to 3.6V, 10% - 90% Vdd = 3.0V to 3.6V and 4.75V to 5.25V, 10% - 90%
AC I2C Specifications
Parameter FSCLI2C Description SCL clock frequency Standard Mode Min 0 4.0 Max 100 - Fast Mode Min 0 0.6 Max 400 - Unit KHz s Notes Fast mode not supported for VDD < 3.0V
THDSTAI2C Hold time (repeated) START condition. After this period, the first clock pulse is generated. TLOWI2C THIGHI2C TSUSTAI2C LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition
4.7 4.0 4.7 0 250 4.0 4.7 -
- - - - - - - -
1.3 0.6 0.6 0 100 0.6 1.3 0
- - - - - - - 50
s s s s ns s s ns
THDDATI2C Data hold time TSUDATI2C Data setup time TSUSTOI2C Setup time for STOP condition TBUFI2C TSPI2C BUS free time between a STOP and START condition Pulse width of spikes suppressed by the input filter
2.7V AC General Purpose IO Specifications Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload = 50pF, Port 0 Rise time, strong mode, Cload = 50pF, Port 1 Fall time, strong mode, Cload = 50pF, all ports Min 15 10 10 Max 100 70 70 Unit ns ns ns Notes Vdd = 2.4V to 3.0V, 10% - 90% Vdd = 2.4V to 3.0V, 10% - 90% Vdd = 2.4V to 3.0V, 10% - 90%
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CY8C20110
Figure 3. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Sr
P
S
Document Number: 001-17345 Rev. *B
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CY8C20110
Ordering Information
Ordering Code CY8C20110-LDX2I CY8C20110-SX2I Package Diagram 001-09116 51-85068 Package Type 16 QFN 16 SOIC Operating Temperature Industrial Industrial
Thermal Impedances by Package
Package 16 QFN 16 SOIC
Note 1. TJ = TA + Power x JA
Typical JA[1] 46 C/W 79.96 C/W
Solder Reflow Peak Temperature
Package 16 QFN 16 SOIC Minimum Peak Temperature[2] 240 C 240 C Maximum Peak Temperature 260 C 260 C
Note 2. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5C with Sn-Pb or 245 5C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
Package Diagram
Figure 4. 16 - Pin Chip On Pb-free 3x3 mm (Sawn) QFN
DIMENSIONS IN mm MIN. MAX.
2.9 3.1
0.20 min
0.45 0.55
1 2 0.20 DIA TYP. 0.05 MAX 0.60 MAX
2.9 3.1
1.5 (NOM) 2 0.152 REF. 1
PIN #1 ID
0.30 0.18 0.50
SEATING PLANE
1.5
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PART NO. LG16A LD16A
DESCRIPTION LEAD-FREE STANDARD
JEDEC # MO-220 Package Weight: 0.014g
001-09116-*C
Document Number: 001-17345 Rev. *B
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CY8C20110
Figure 5. 16 - Pin (150-Mil) SOIC
51-85068-*B
Document Number: 001-17345 Rev. *B
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CY8C20110
Document History Page
Document Title: CY8C20110 CapSenseLITE - 10 Configurable IOs Document Number: 001-17345 REV. ** *A ECN. 1341766 1494145 Issue Date See ECN See ECN Orig. of Change TUP/SFV TUP/AESA New Data Sheet Changed to FINAL Datasheet Removed table - 2.7V DC General Purpose IO Specifications - Open Drain with a pull up to 1.8V Updated Logic Block Diagram Removed table - 3V DC General Purpose IO Specifications Updated Logic Block Diagram Updated table - DC POR and LVD Specifications Updated table - DC Chip Level Specifications Updated table - 5V and 3.3V DC General Purpose IO Specifications Updated table - 2.7V DC General Purpose IO Specifications Updated table - AC GPIO Specifications and split it into two tables for 5V/3.3V and 2.7V Added section on CapSenseLITE Software tool Updated 16-QFN Package Diagram Description of Change
*B
1773608
See ECN
TUP/AESA
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-17345 Rev. *B
Revised November 22, 2007
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PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.
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