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| TMP92CD54I CMOS 32-bit Micro-controller TMP92CD54IF 1. Outline and Device Characteristics TMP92CD54I is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP92CD54I is a micro-controller which has a high-performance CPU (900/H1 CPU) and various built-in I/Os. TMP92CD54I is housed in a 100-pin mini flat package. Device characteristics are as follows: (1) CPU : 32-bit CPU(900/H1 CPU) Compatible with TLCS-900,900/L,900/L1,900/H,900/H2's instruction code 16Mbytes of linear address space General-purpose register and register banks Micro DMA : 8channels (250ns / 4bytes at fc = 20MHz, best case) Minimum instruction execution time : 50ns(at 20MHz) Internal data bus : 32-bit Internal memory Internal RAM : 32K-byte Internal ROM : 512K-byte Mask ROM (2) 92CD54I-1 2006-01-27 TMP92CD54I (3) External memory expansion 16M-byte linear address space (memory mapped I/O) External data bus : 8bit(for external I/O expansion) * Can't use upper address bus when built-in I/Os are selected Memory controller (MEMC) Chip select output : 1 channel (5) 8-bit timer : 8 channels 8-bit interval timer mode (8 channels) 16-bit interval timer mode (4 channels) 8-bit programmable pulse generation (PPG) output mode (4 channels) 8-bit pulse width modulation (PWM) output mode (4 channels) 16-bit timer : 2 channels 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) output mode Frequency measurement mode Pulse width measurement mode Time differential measurement mode Serial interface (SIO) : 2 channels I/O interface mode Universal asynchronous receiver transmitter (UART) mode Serial expansion interface (SEI) : 1 channel Baud rate 4/2/0.5Mbps at fc=20MHz. Serial bus interface (SBI) : 3 channels Clocked-synchronous 8-bit serial interface mode I2C bus mode (10) CAN controller : 1channel Supports CAN version 2.0B. 16 mailboxes (11) 10-bit A/D converter (ADC) : 12 channels A/D conversion time 8sec @fc=20MHz. Total tolerance +/- 3LSB (excluding quantization error) Scan mode for all 12channels (12) Watch dog timer (WDT) (13) Timer for real-time clock (RTC) Can operate with only low frequency oscillator. (14) Interrupt controller (INTC) : 60 interrupt sources 9 interrupts from CPU 42 internal interrupt vectors 9 external interrupt vectors (15) I/O Port : 68pins (16) Standby mode Four modes : IDLE3,IDLE2,IDLE1 and STOP STOP mode can be released by 9 external inputs. (17) Internal voltage detection flag (RAMSTB) (9) (4) (6) (7) (8) 92CD54I-2 2006-01-27 TMP92CD54I (18) Power supply voltage VCC5 = 4.5V to 5.25V VCC3 = 3.3V (VCC3 Connect to REGOUT; built-in voltage regulator.) (19) (20) Operating temperature : -40 to 85 degree C Package : P-LQFP100-1414-0.50F 92CD54I-3 2006-01-27 TMP92CD54I PG0toPG7 (AN0toAN7) PL0toPL3 (AN8toAN11) ADVCC ADVSS VREFH VREFL (TXD0)PF0 (RXD0)PF1 (SCLK0/ CTS0 )PF2 (TXD1)PF3 (RXD1)PF4 (SCLK1/ CTS1 )PF5 (TX)PF6 (RX)PF7 (TI0/INT1)PC0 (TO1)PC1 10-BIT 12CH A/D CONVERTER XWA XBC XDE SERIAL I/O Channel 0 SERIAL I/O Channel 1 CAN CONTROLLER W B D H IX IY IZ SP 32 bits SR P C A C E L Regulator REGEN REGOUT X1 X2 CLK XT1 XT2 RESET XHL XIX XIY XIZ XSP OSC RTC F INTERRUPT CONTROLLER AM0 AM1 TEST0 TEST1 NMI INT0 P00toP07 (D0toD7) P40toP47 (A0toA7) P70( RD ) P71( WR ) P73( CS ) P74 P75( WAIT ) PN0(SCK0) PN1(SO0/SDA0) PN2(SI0/SCL0) PN3(SCK1/A12) PN4(SO1/SDA1/A13) PN5(SI1/SCL1/A14) PM4(SCK2) PN6(SO2/SDA2/A15) P72(SI2/SCL2) 8BIT TIMER (TIMER0) 8BIT TIMER (TIMER1) 8BIT TIMER (TIMER2) WATCH-DOG TIMER REAL TIME CLOCK (RTC) PORT0 PORT4 32KB RAM PORT7 (TO3/INT2)PC2 (TI4/INT3)PC3 8BIT TIMER (TIMER3) 8BIT TIMER (TIMER4) 8BIT TIMER (TIMER5) 8BIT TIMER (TIMER6) 8BIT TIMER (TIMER7) 16BIT TIMER (TIMER8) 16BIT TIMER (TIMERA) Figure 1 TMP92CD54I block diagram SERIAL EXP.I/F 512KB Mask ROM SERIAL BUS I/F Channel 0 SERIAL BUS I/F Channel 1 SERIAL BUS I/F Channel 2 (TO5)PC4 (TO7/INT4)PC5 (TI8/WUINT0/INT5/A16)PD0 (TI9/WUINT1/INT6/A17)PD1 (TO8/WUINT2/A18)PD2 (TO9/WUINT3/A19)PD3 (TIA/WUINT4/INT7/A20)PD4 (TIB/WUINT5/A21)PD5 (TOA/WUINT6/A22)PD6 (TOB/WUINT7/A23)PD7 PM0( SS /A8) PM1(MOSI/A9) PM2(MISO/A10) PM3(SECLK/A11) 92CD54I-4 2006-01-27 CONNECT 900/H1 CPU DVSS[6] DVCC5[5] DVCC3[3] TMP92CD54I 2. Pin Assignment and Functions 2.1 Pin Assignment 095 090 085 080 ADVSS ADVCC VREFL VREFH RX/PF7 TX/PF6 CTS1/SCLK1/PF5 RXD1/PF4 TXD1/PF3 CTS0/SCLK0/PF2 RXD0/PF1 TXD0/PF0 DVSS PM4/SCK2 DVCC5 A8/SS/PM0 A9/MOSI/PM1 A10/MISO/PM2 A11/SECLK/PM3 D0/P00 D1/P01 D2/P02 D3/P03 D4/P04 D5/P05 01 076 100 PL3/AN11 PL2/AN10 PL1/AN9 PL0/AN8 PG7/AN7 PG6/AN6 PG5/AN5 PG4/AN4 PG3/AN3 PG2/AN2 PG1/AN1 PG0/AN0 DVSS P75/WAIT DVCC3 P74 P73/CS P72/SI2/SCL2 P71/WR P70/RD AM0 RESET AM1 CLK TEST0 75 05 70 10 TMP92CD54IF (P-LQFP100-1414-0.50F) 65 14 x 14 x 1.4 15 TOP VIEW 60 20 55 26 30 35 40 45 D6/P06 D7/P07 A0/P40 A1/P41 A2/P42 A3/P43 A4/P44 A5/P45 A6/P46 A7/P47 DVCC3 INT0 DVSS NMI DVCC5 A16/WUINT0/INT5/TI8/PD0 A17/WUINT1/INT6/TI9/PD1 A18/WUINT2/TO8/PD2 A19/WUINT3/TO9/PD3 A20/WUINT4/INT7/TIA/PD4 A21/WUINT5/TIB/PD5 A22/WUINT6/TOA/PD6 A23/WUINT7/TOB/PD7 REGOUT DVCC5 Figure 2.1 TMP92CD54I Pin Assignment 92CD54I-5 50 25 51 DVCC5 X1 DVSS X2 TEST1 XT1 XT2 DVCC3 PN6/SO2/SDA2/A15 PN5/SI1/SCL1/A14 PN4/SO1/SDA1/A13 PN3/SCK1/A12 DVSS PN2/SI0/SCL0 DVCC5 PN1/SO0/SDA0 PN0/SCK0 PC0/TI0/INT1 PC1/TO1 PC2/TO3/INT2 PC3/TI4/INT3 PC4/TO5 PC5/TO7/INT4 REGEN DVSS 2006-01-27 TMP92CD54I 2.2 Pin names and functions The following table shows the names and functions of the input/output pins. Pin Number of In/Out Function number pins P00..P07 (CMOS) in/out Port 0: I/O port. Input or output specifiable in units of bits. 20th...27th 8 D0..D7 (TTL) in/out Data: Data bus 0 to 7. in/out Port4: I/O port. Input or output specifiable in units of bits. P40..P47 8 28th...35th out Address: Address bus 0 to 7. A0..A7 in/out Port70: I/O port. P70 81st 1 out Read: Outputs strobe signal to read external memory. RD Pin name P71 WR P72 SI2 SCL2 P73 CS P74 P75 WAIT PC0 TI0 INT1 PC1 TO1 PC2 TO3 INT2 PC3 TI4 INT3 PC4 TO5 PC5 TO7 INT4 PD0 TI8 INT5 A16 WUINT0 PD1 TI9 INT6 A17 WUINT1 PD2 TO8 A18 WUINT2 PD3 TO9 A19 WUINT3 82nd 83rd 84th 85th 87th 58th 57th 56th 55th 54th 53rd 1 1 1 1 1 1 1 1 1 1 1 in/out Port 71: I/O port. out Write: Output strobe signal to write external memory. Port 72: I/O port. in/out SBI channel 2: Input data at SIO mode SBI channel 2: Clock input/output at IC mode in/out Port 73: I/O port. out Chip select: Outputs "low" if address is within specified address area. in/out Port 74: I/O port. in/out Port 75: I/O port. in Wait: Signal used to request CPU bus wait. Port C0: I/O port. Timer input 0: Input pin for timer 0. INT1 Interrupt request pin 1: Rising-edge interrupt request pin. Port C1: I/O port. Timer output 1: Output pin for timer 1. Port C2: I/O port. Timer output 3: Output pin for timer 3. INT2 Interrupt request pin 2: Rising-edge interrupt request pin. Port C3: I/O port. INT3 Timer input 4: Input pin for timer 4. Interrupt request pin 3: Rising-edge interrupt request pin. Port C4: I/O port. Timer output 5: Output pin for timer 5. Port C5: I/O port. INT4 Timer output 7: Output pin for timer 7. Interrupt request pin 4: Rising-edge interrupt request pin. Port D0: I/O port. INT5 Timer input 8: Input pin for timer 8. Interrupt request pin 5: Interrupt request pin with programmable rising/falling WUINT0 edge. out Address: Address bus 16. Wake up input 0: Wake up request pin with programmable rising, falling or both in falling and rising edge. in/out Port D1: I/O port. WUINT1 INT6 in Timer input 9: Input pin for timer 9. in Interrupt request pin 6: Rising-edge interrupt request pin. out Address: Address bus 17. in Wake up input 1: Wake up request pin with programmable rising, falling or both falling and rising edge. in/out Port D2: I/O port. out Timer output 8: Output pin for timer 8 WUINT2 out Address: Address bus 18. in Wake up input 2: Wake up request pin with programmable rising, falling or both falling and rising edge. in/out Port D3: I/O port. out Timer output 9: Output pin for timer 9 WUINT3 out Address: Address bus 19. in Wake up input 3: Wake up request pin with programmable rising, falling or both falling and rising edge. in/out in in in/out out in/out out in in/out in in in/out out in/out out in in/out in in 41st 1 42nd 1 43rd 1 44th 1 92CD54I-6 2006-01-27 TMP92CD54I Pin name PD4 TIA INT7 A20 WUINT4 PD5 TIB A21 WUINT5 PD6 TOA A22 WUINT6 PD7 TOB A23 WUINT7 PF0 TXD0 PF1 RXD0 PF2 SCLK0 CTS0 PF3 TXD1 PF4 RXD1 PF5 SCLK1 Pin number Number of pins In/Out Function 45th 1 46th 1 47th 1 48th 1 12th 11th 10th 9th 8th 7th 1 1 1 1 1 1 1 1 8 4 in/out Port D4: I/O port. INT7 Timer input A: Input pin for timer A in Interrupt request pin 7: Interrupt request pin with programmable rising/falling in edge. WUINT4 out Address: Address bus 20. Wake up input 4: Wake up request pin with programmable rising, falling or both in falling and rising edge. in/out Port D5: I/O port. WUINT5 Timer input B: Input pin for timer B. in out Address: Address bus 21. Wake up input 5: Wake up request pin with programmable rising, falling or both in falling and rising edge. in/out Port D6: I/O port. WUINT6 out Timer output A: Output pin for timer A. out Address: Address bus 22. in Wake up input 6: Wake up request pin with programmable rising, falling or both falling and rising edge. in/out Port D7: I/O port. WUINT7 out Timer output B: Output pin for timer B. out Address: Address bus 23. in Wake up input 7: Wake up request pin with programmable rising, falling or both falling and rising edge. in/out Port F0: I/O port. out Serial interface channel 0: Transmission data. in/out Port F1: I/O port. in Serial interface channel 0: Receive data. in/out Port F2: I/O port. in/out Serial interface channel 0: Clock input/output. in Serial interface channel 0: Data ready to send. (Clear-to-send) in/out out in/out in in/out in/out in in/out out in/out in in in in in Port F3: I/O port. Serial interface channel 1: Transmission data. Port F4: I/O port. Serial interface channel 1: Receive data. Port F5: I/O port. Serial interface channel 1: Clock input/output. Serial interface channel 1: Data ready to send. (Clear-to-send) Port F6: I/O port. CAN: Transmission data. Port F7: I/O port. CAN: Receive data. Port G: Input-only port. Analog input 0 to 7: AD converter input pins. Port L0 to L3: Input-only port. Analog input 8 to 11: AD converter input pins. CTS1 PF6 6th TX PF7 5th RX PG0..PG7 89th...96th AN0..AN7 PL0..PL3 AN8..AN1 97th...100th 1 PM0 16th SS A8 PM1 MOSI 17th A9 PM2 MISO 18th A10 PM3 SECLK 19th A11 PM4 14th SCK2 PN0 59th SCK0 1 in/out Port M0: I/O port. in SEI: Slave select input. out Address: Address bus 8. in/out in/out out in/out in/out out in/out in/out out in/out in/out in/out in/out Port M1: I/O port. SEI: Master output, slave input. Address: Address bus 9. Port M2: I/O port. SEI: Master input, slave output. Address: Address bus 10. Port M3: I/O port. SEI: Clock input/output. Address: Address bus 11. Port M4: I/O port. SBI channel 2: Clock input/output at SIO mode. Port N0: I/O port. SBI channel 0: Clock input/output at SIO mode. 1 1 1 1 1 92CD54I-7 2006-01-27 TMP92CD54I Pin name PN1 SO0 SDA0 PN2 SI0 SCL0 PN3 SCK1 A12 PN4 SO1 SDA1 A13 PN5 SI1 SCL1 A14 PN6 SO2 SDA2 A15 NMI INT0 AM0,1 TEST0,1 CLK X1/X2 XT1/XT2 RESET VREFH VREFL ADVCC ADVSS DVCC5 DVCC3 DVSS REGOUT REGEN Pin number 60th 62nd 64th Number of pins 1 1 1 In/Out in/out out in/out in/out in in/out in/out in/out out in/out out in/out out in/out in in/out out Function 65th 1 66th 1 67th 1 39th 1 Port N1: I/O port. SBI channel 0: Output data input/output at SIO mode SBI channel 0: Data input/output at IC mode Port N2: I/O port. SBI channel 0: Input data at SIO mode SBI channel 0: Clock input/output at IC mode Port N3: I/O port. SBI channel 1: Clock input/output at SIO mode Address: Address bus 12. Port N4: I/O port. SBI channel 1: Output data at SIO mode SBI channel 1: Data input/output at IC mode Address: Address bus 13. Port N5: I/O port. SBI channel 1: Input data at SIO mode SBI channel 1: Clock input/output at IC mode Address: Address bus 14 Port N6: I/O port. in/out SBI channel 2: Output data at SIO mode out SBI channel 2: data input output at I2C mode Address: Address bus 15. Non-maskable interrupt: Interrupt request pin with programmable falling or both in falling and rising edge. NMI in in in out Interrupt request pin 0: Interrupt request pin with programmable level or rising-edge. INT0 Address Mode selection: Connect AM0 pin to L, AM1 pins to H. Test mode pins: Should be set to L. Programmable clock output (with pull-up register) Low frequency oscillator connecting pins. Crystal or ceramic resonator is connected. RC oscillation is also possible Reset: Initializes LSI (with pull-up register). AD reference voltage high AD reference voltage low Power supply pin for AD converter (+5V): Connect ADVCC pin to 5V power supply. GND pin for AD converter: Connect ADVSS pin to GND (0V). Power supply pins (+5V): Connect all DVCC5 pins to 5V power supply. Power supply pins (+3.3V): Connect all DVCC3 pins to REGOUT pin. GND: Connect all DVSS pins to GND (0V). Regulator output 3.3V: Connect capacitor to stabilize the regulator output. Regulator enable pin: Should be set to H or OPEN (with pull-up register). 37th 80th, 78th 76th, 71st 77th 74th, 72nd 70th, 69th 79th 4th 3rd 2nd 1st 15th, 40th, 50th,61st,75th 36th,68th,86th 13th,38th,51st, 63rd,73rd,88th 49th 52nd 1 2 2 1 2 2 1 1 1 1 1 5 3 6 1 1 in/out Oscillator connecting pins in/out in in in out in 92CD54I-8 2006-01-27 TMP92CD54I 3. OPERATION This section describes the basic components, functions and operation of TMP92CD54I. 3.1 CPU TMP92CD54I contains an advanced high-speed 32-bit CPU (900/H1 CPU) 3.1.1 CPU Outline 900/H1 CPU is high-speed and high-performance CPU based on 900/H CPU. 900/H1 CPU has expanded 32-bit internal data bus to process Instructions more quickly. Outline of 900/H1 CPU are as follows: 900/H1 CPU 24-bit 32-bit 16 to 20MHz (@fOSC=8 to 10MHz) 1-clock access (50ns@fOSC=10MHz) 32-bit 1-clock access 32-bit interleave 2-1-1-1-clock access 8/16-bit 2-clock access PORT, INTC, MEMC 8/16-bit 5 to 6-clock access SEI, SIO, WDT, 8-bit Timer, 16-bit Timer, RTC, 10-bit ADC, SBI, CAN 8-bit 2-clock access (can insert some waits) 1-clock(50ns@fOSC=10MHz) 2-clock(100ns@fOSC=10MHz) 12-byte Compatible with TLCS-900, 900/H, 900/L, 900/L1 and 900/H2 (NORMAL, MIN, MAX and LDX instruction is deleted) 8-channels Width of CPU Address Bus Width of CPU Data Bus Internal Operating Frequency Minimum Bus Cycle (Internal RAM) Internal RAM Internal ROM Internal I/O External Device Minimum Instruction Execution Cycle Conditional Jump Instruction Queue Buffer Instruction Set Micro DMA 92CD54I-9 2006-01-27 TMP92CD54I 3.1.2 Reset Operation When resetting TMP92CD54I microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input Low for at least 20 system clocks (4us). At reset the clock doubler is bypassed and system clock operates at 5MHz (fOSC=10MHz). When the Reset has been accepted, the CPU performs the following: * Sets the Program Counter (PC) as follows in accordance with the Reset Vector stored at address FFFF00H to FFFF02H: PC<0 to 7> data in location FFFF00H PC<8 to 15> data in location FFFF01H PC<16 to 23> data in location FFFF02H * Sets the Stack Pointer (XSP) to 00000000H. * Sets bits 3.1.3 Setting of TEST0, TEST1, AM0 and AM1 Connect TEST0, TEST1 pin to "GND" to use at NORMAL mode. Set AM0 pin to "0" and set AM1 pin to "1" to use. Table 3.1.2 Operation Mode Setup Table Operation Mode Single-chip Mode RESET Mode Setup input pin AM1 AM0 TEST1 1 0 0 TEST0 0 92CD54I-10 2006-01-27 TMP92CD54I 3.2 Memory Map Figure 3.2 is a memory map of TMP92CD54I. 000000H Direct area (n) 000100H 000400H Internal RAM (32 KByte) 008400H Internal I/O (1 KByte) 64Kbyte area (nn) 010000H External memory Emulator Control Area (64K Byte) (Note1) F80000H 512 KByte Internal ROM 16Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Vector table (256 Byte) ( (Note2) = Internal area) Figure 3.2 Memory Map Note1: The emulator control area is for emulator, it is mapped F00000H to F10000H address after reset. Note2: Don't use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved. Note3: On emulator WR signal and RD signal are asserted, when emulator control area is accessed. Be careful to use external memory. Note4: Since there is a possibility of abnormal writing/reading of the data if Bus width put the different memories in consecutive address, do not execute an access which is placed on both memories with one command. 92CD54I-11 2006-01-27 TMP92CD54I 3.3 The Clock Function and Standby Function 3.3.1 10MHz X1 X2 High Frequency OSC Block diagram of system clock (10MHz) (40MHz) To generate the external memory interface timing Clock doubler*1 (PLL)x4 System Clock `fc' 1/2 20MHz CPU MEMC INTC ROMC PORT CAN SIO TIMER WDT SBI A/D RTC SEI 1/2 10MHz 2/5 16MHz (32.768 kHz) XT1 XT2 (32.768 kHz) For RTC 14-stage binary counter Low frequency OSC fs *1) Clock-doubler outputs averaging 40MHz clock because it is corrected in clock unit of High Frequency OSC output (10MHz) though it has the possibility that the tolerance of 1.46ns at 40MHz (reference data) is included. Figure 3.3.1 Block Diagram of System clock 92CD54I-12 2006-01-27 TMP92CD54I 3.3.2 Standby controller (1) Halt Modes When the HALT instruction is executed, the operating mode switches to Idle2, Idle1, Idle3 or Stop Mode, depending on the contents of the CLKMOD CLKMOD (010AH) bit Symbol Read/Write After reset 1 Standby mode 00: IDLE3 01: STOP 10: IDLE1 11: IDLE2 HALTM1 R/W 1 - 6 HALTM0 5 - 4 R/W 0 Fix to "0" 3 - 2 CLKOE 0 CLKoutput enable 0: not output 1: output 1 CLKM1 R/W 0 0 CLKM0 0 Function CLK output select 00: fc 01: Reserved 10: 2/5 fc 11: Reserved CLK output clock select 00 01 10 11 fc Reserved 2/5 fc Reserved CLK output enable 0 1 Not output (Pull up) Output Selects standby mode by HALT instruction 00 01 10 11 IDLE3 STOP IDLE1 IDLE2 Figure 3.3.2 Clock Mode Register 92CD54I-13 2006-01-27 TMP92CD54I The subsequent actions performed in each mode are as follows: Idle2: The CPU only is halted. In Idle2 Mode internal I/O operations can be performed by setting the following registers. Table 3.3.1 Shows the registers of setting operation during Idle2 Mode. Table 3.3.1 Shows the registers of setting operation during Idle2 Mode Internal I/O SFR TIMER0,TIMER1 TIMER2,TIMER3 TIMER4,TIMER5 TIMER6,TIMER7 TIMER8 TIMERA SIO0 SIO1 SBI0 SBI1 SBI2 A/D converter WDT TRUN01 Idle1: Only the oscillator of low and high frequency continue to operate. Idle3: Only the oscillator of low frequency and RTC are operated. Stop: All internal circuits stop operating. The operation of each of the different Halt Modes is described in Table 3.3.2. Halt Mode CLKMOD Table 3.3.2 I/O operation during Halt Modes Idle2 Idle1 Idle3 11 10 00 Stop 01 See table 3.3.5 Halt Maintain same state as when HALT instruction was executed. Block Selectable See table 3.3.1 Stopped Operational 92CD54I-14 2006-01-27 TMP92CD54I (2) How to clear a Halt mode The Halt state can be cleared by a Reset or by an interrupt request. The combination of the value in 92CD54I-15 2006-01-27 TMP92CD54I Table 3.3.3 Source of Halt state clearance and Halt clearance operation Status of Received Interrupt Halt mode NMI INTWDT INT0 Interrupt Enabled Interrupt Disabled (interrupt level) (interrupt mask) (interrupt level) < (interrupt mask) Idle2 Idle1 x Idle3 *1 Stop *1 Idle2 - - Idle1 - - Idle3 - - *1 *2 *1 *2 Stop - - *1 *2 *1 *2 x *1 *2 *1 *2 x *1 *2 *1 *2 Source of Halt state clearance INT0 [MASK] INT1 to 7 INTT0 to 7 INTTR8 to B INTTO8, INTTOA INTRX0 to 1, TX0 to 1 INTCR0, INTCT0, INTCG0 INTSEM0, E0, R0, T0 INTSBE0, S0, E1, S1, E2, S2 INTAD All the above-mentioned interrupts [MASK] x x x x x x x x x x x x x x x x x x x x x *1 *1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x *1 *1 x x x x x x x x x x x x Interrupt INTRTC INTRTC [MASK] RESET : After clearing the Halt mode, CPU starts interrupt processing. (RESET initializes the microcont.) : After clearing the Halt mode, CPU resumes executing starting from instruction following the HALT instruction. x: Cannot be used to clear the Halt mode. -: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: The Halt mode is cleared when the warm-up time has elapsed. *2: Any WUINT interrupt (WUINT0 to WUINT7) generate an INT0 interrupt. Note 1: When the Halt mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level H, interrupt processing is not correctly started. Note 2: When the external interrupts INT5 to INT7 are used during Idle2 Mode, set to 1 for TRUN8 Address 8203H 8206H 8209H 820BH 820EH INT0 LD LD EI LD HALT (IIMC), 00H (INTE0AD), 06H 5 (CLKMOD), 80H ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets interrupt level to 5 for CPU. ; Sets Halt mode to Idle1 Mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 92CD54I-16 2006-01-27 TMP92CD54I (3) Operation Idle2 Mode In Idle2 Mode only specific internal I/O operations, as designated by the Idle2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.3.3 illustrates an example of the timing for clearance of the Idle2 Mode Halt state by an interrupt. fc A0 to 23 Internal signals Next Next+4 D0 to 31 Data Data RD WR Clearing interrupt HALT instruction execution sequence Interrupt response sequence Figure 3.3.3 Timing chart for Idle2 Mode Halt state cleared by interrupt Idle1 Mode In Idle1 Mode, only the internal oscillator continue to operate. The system clock in the MCU stops. In the Halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the Halt state (i.e. restart of operation) is synchronous with it. Figure 3.3.4 illustrates the timing for clearance of the Idle1 Mode Halt state by an interrupt. fc A0 to 23 Internal signals Next Next+4 D0 to 31 Data Data RD WR Clearing interrupt HALT instruction execution sequence Interrupt response sequence Figure 3.3.4 Timing chart for Idle1 Mode Halt state cleared by interrupt 92CD54I-17 2006-01-27 TMP92CD54I Idle3 Mode When Idle3 Mode is selected, internal circuits stop including the internal oscillator, except the oscillator of low frequency and RTC. Pin status in Stop Mode depends on the settings in the WDMOD (Note) fc fs(32kHz) Internal signals RTC A0 to 23 D0 to 31 Operated Programmable Next Data Operated Programmable Next+4 Data RD WR Clearing interrupt HALT instruction execution sequence Interrupt response sequence (Note); The interrupt processing starts after it completes for Startup time (Tsta) of Oscillator, Warm-up time and clock doubler stable time period, after releasing HALT (Tsta + 1.6 ms + 1.6 ms). Please inquire about Startup time (Tsta) to each oscillator manufacturer. Figure 3.3.5 Timing chart for Idle3 Mode Halt state cleared by interrupt 92CD54I-18 2006-01-27 TMP92CD54I Stop Mode When Stop Mode is selected, all internal circuits stop, including the internal oscillator. Pin status in Stop Mode depends on the settings in the WDMOD (Note) fc A0 to 23 Internal signals Next Next+4 D0 to 31 Data Data RD WR Clearing interrupt HALT instruction execution sequence Interrupt response sequence (Note); The interrupt processing starts after it completes for Startup time (Tsta) of Oscillator, Warm-up time and clock doubler stable time period, after releasing HALT (Tsta + 1.6 ms + 1.6 ms). Please inquire about Startup time (Tsta) to each oscillator manufacturer. Figure 3.3.6 Timing chart for Stop Mode Halt state cleared by interrupt Table 3.3.4 Warming-up time and clock doubler stable time after clearance of Stop Mode and Idle3 Mode (@ fc=20MHz) Warm-up time Clock doubler stable time 1.6 ms (2 /fOSC) 14 1.6 ms (2 /fOSC) fc = 2xfOSC 14 92CD54I-19 2006-01-27 TMP92CD54I Table 3.3.5 Pin states in Idle3 and Stop Mode Pin Names P00 to 07 I/O Input Mode Output Mode D0 to D7 Invalid Output High-z Invalid High-z Invalid High-z Input Input Invalid High-z Input High-z Input Invalid High-z Invalid Invalid Invalid High-z Invalid High-z Input Input Input Input Input Invalid P40 to 47/A0 to 7 P70,P71,P73 to 75/ RD , WR , CS to WAIT P72/SI2/SCL2 PC0 to PC5/TI0 to TO7 PD0 to PD7/TI8 to TOB Input Mode Output Mode Input Mode Output Mode Input Mode Output Mode Input Mode Output Mode Input Mode Output Mode WUINT0 to 7 Output Output Output Output Output PF0 to PF7/TXD0 to RX PG0 to PG7/AN0 to AN7 PL0 to PL3/AN8 to AN11 PM0 to PM4 / SS to SCK2 PN0 to PN6 /SCK0 to SO2&SDA2 NMI INT0 Input Mode Output Mode Input Mode Input Mode Input Mode Output Mode Input Mode Output Mode Input Input Input Input Input Input Output Input Output Output Output Output Output RESET AM0, AM1 TEST0, TEST1 X1 X2 XT1 XT2 CLK H Level Output Invalid (STOP) Operate (IDLE3, RTCFC Input: Input gate in operation. Input voltage should be fixed to "L" or "H" so that input pin stays constant. Output: Output state Invalid: Input pin invalid. High-z: Output pin High-Impedance. Note) At RTCFC 92CD54I-20 2006-01-27 TMP92CD54I 3.4 Interrupts Interrupts are controlled by the CPU Interrupt Mask Register A fixed individual interrupt vector number is assigned to each interrupt source. Any one of six levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority level of 7, the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. When more than one interrupt are generated simultaneously, the interrupt controller sends the priority value of the interrupt with the highest priority to the CPU. (The highest priority level is 7, the level used for non-maskable interrupts.) The CPU compares the interrupt priority level which it receives with the value held in the CPU Interrupt Mask Register 92CD54I-21 2006-01-27 TMP92CD54I Interrupt processing Micro DMA soft start request * Interrupt apecified by micro DMA start vector? Yes No * Micro DMA is initiated by a write cycle which writes to the register DMAR. Clear interrupt request flag Interrupt vector calue "V" read Interrupt request F/F clear Data transfer by micro DMA General-purpose interrupt processing PUSH PC PUSH SR SR Count Count1 Micro DMA processing Count = 0 No Yes Clear vector register generating micro DMA transfer end interrupt (INTTC0 to 7) PC (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNESTINTNEST - 1 End Figure 3.4.1 Interrupt and micro DMA processing sequence 92CD54I-22 2006-01-27 TMP92CD54I 3.4.1 General-purpose interrupt processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and Illegal Instruction interrupts generated by the CPU, the CPU skips steps (a) and (c) and executes only steps (b), (d) and (e). (a) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level have been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: the smaller the vector value, the higher the priority.) (b) The CPU pushes the Program Counter (PC) and Status Register (SR) onto the top of the stack (pointed to by XSP). (c) The CPU sets the value of the CPU's Interrupt Mask Register 92CD54I-23 2006-01-27 TMP92CD54I Table 3.4.1 TMP92CD54I interrupt vectors and micro DMA start vectors (1/2) Default Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Maskable Non Maskable Type Interrupt Source and Source of Micro DMA Request Reset or [SWI0] instruction [SWI1] instruction Illegal instruction or [SWI2] instruction [SWI3] instruction [SWI4] instruction [SWI5] instruction [SWI6] instruction [SWI7] instruction NMI: pin input INTWD: Watchdog Timer Micro DMA INT0: INT0 pin input (Note2) INT1: INT1 pin input INT2: INT2 pin input INT3: INT3 pin input INT4: INT4 pin input INT5: INT5 pin input INT6: INT6 pin input INT7: INT7 pin input INTT0: 8-bit timer 0 INTT1: 8-bit timer 1 INTT2: 8-bit timer 2 INTT3: 8-bit timer 3 INTT4: 8-bit timer 4 INTT5: 8-bit timer 5 INTT6: 8-bit timer 6 INTT7: 8-bit timer 7 INTTR8: 16-bit timer 8 INTTR9: 16-bit timer 8 INTTRA: 16-bit timer A INTTRB: 16-bit timer A INTTO8: 16-bit timer 8 (overflow) INTTOA: 16-bit timer A (overflow) INTRX0: Serial receive (Channel 0) INTTX0: Serial transmission (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial transmission (Channel 1) INTCR: CAN receive INTCT: CAN transmission INTCG: CAN global INTSEM: SEI mode fault error INTSEE: SEI transfer end / slave error INTSER: SEI receive INTSET: SEI transmission INTRTC: Read Time Counter (reserved) INTSBE2: SBI I2CBUS transfer end (Channel 2) INTSBS2: SBI I2CBUS stop condition (Channel 2) INTSBE0: SBI I2CBUS transfer end (Channel 0) INTSBS0: SBI I2CBUS stop condition (Channel 0) INTSBE1: SBI I2CBUS transfer end (Channel 1) Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H Address refer to Vector FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H FFFFB8H FFFFBCH FFFFC0H FFFFC4H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H (Note3) 21H 22H (Note3) 23H 24H (Note3) 25H (Note3) 26H (Note3) 27H (Note3) 28H (Note3) 29H 2AH 2BH 2DH 2EH 2FH 30H 31H Micro DMA Start Vector 92CD54I-24 2006-01-27 TMP92CD54I Table 3.4.2 TMP92CD54I interrupt vectors and micro DMA start vectors (2/2) Default Priority 51 52 53 54 55 56 57 58 59 60 to Maskable Type Interrupt Source and Source of Micro DMA Request INTSBS1: SBI I2CBUS stop condition (Channel 1) INTAD: AD conversion end INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) INTTC4: Micro DMA end (Channel 4) INTTC5: Micro DMA end (Channel 5) INTTC6: Micro DMA end (Channel 6) INTTC7: Micro DMA end (Channel 7) (reserved) Vector Value 00C8H 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H 00E4H 00E8H 00ECH 00F0H 00FCH Address refer to Vector FFFFC8H FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H FFFFE4H FFFFE8H FFFFECH FFFFF0H FFFFFCH Micro DMA Start Vector 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH to - Note1: Micro DMA default priority If an interrupt request is generated by micro DMA, the interrupt has a higher priority than any other maskable interrupt (irrespective of default channel priority). Note2: When standing-up micro DMA, set at edge detect mode. Note3: Micro DMA processing cannot be applied. Note4: This table mentions only the start address. Then each vector has 4 bytes. 92CD54I-25 2006-01-27 TMP92CD54I 3.4.2 Micro DMA processing In addition to general-purpose interrupt processing, TMP92CD54I also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (level 6), regardless of the priority level of the interrupt source. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU is a state of stand-by by HALT instruction, the requirement of micro DMA will be ignored (pending). Micro DMA supports 8 channels and can be transferred continuously by specifying the micro DMA burst function in the following. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the Micro DMA Start Vector Register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The eight micro DMA channels allow micro DMA processing to be set for up to eight types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data in one-byte or two-byte or four-byte blocks, is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a Micro DMA Transfer End interrupt (INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: the lower the channel number, the higher the priority (Channel 0 thus has the highest priority and Channel 7 the lowest). If an interrupt request is triggered on the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general-purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (i.e. interrupt requests should be disabled). If micro DMA and general-purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels. In this case, edge-triggered interrupts are the only kinds of general interrupts which can be accepted. Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16M-bytes (the upper eight bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: one-byte transfers, two-byte (one-word) transfer and four-byte transfer. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, from I/O to I/O, and memory to memory. For details of the various transfer modes, see Section 3.4.2 (4), Detailed description of the Transfer Mode Register. 92CD54I-26 2006-01-27 TMP92CD54I Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 43 different interrupts - the 42 interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft start. Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in Transfer Destination Address INC Mode (micro DMA transfers are the same in every mode except Counter Mode). (The conditions for this cycle are as follows: external 8-bit bus, 0 waits, and even-numbered transfer source and transfer destination addresses). One state 1 CLK A023 2 3 4 5 src dst Figure 3.4.2 Timing for micro DMA cycle States 1, 2: State 3: State 4: State 5: Instruction fefetch cycle (pretches the next instruction code) Micro DMA read cycle Micro DMA write cycle (The same as in state 1, 2) (2) Micro DMA operation TMP92CD54I can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a Write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once. On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0. When a burst is specified by the register DMAB, data is transferred continuously from the initiation of micro DMA until the value in the micro DMA transfer counter is 0. Symbol NAME DMA Request Address 109h (no RMW) 7 DREQ7 0 6 DREQ6 0 5 DREQ5 0 4 3 2 DREQ2 0 1 DREQ1 0 0 DREQ0 0 DMAR DREQ4 DREQ3 R/W 0 0 92CD54I-27 2006-01-27 TMP92CD54I (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form LDC cr,r can be used to set these registers. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA Source address register 0 DMA Destination address register 0 DMA Counter register 0 DMA Mode register 0 Channel 7 DMAS7 DMAD7 DMAC7 DMAM7 8 bits 16 bits 32 bits DMA Source address register 7 DMA Destination address register 7 DMA Counter register 7 DMA Mode register 7 92CD54I-28 2006-01-27 TMP92CD54I (4) Detailed description of the Transfer Mode Register 0 0 0 Mode DMAM0 to 7 DMAM[4:0] 000zz 001zz 010zz 011zz 100zz 101zz 110zz 111zz Mode Description Destination INC mode (DMADn +) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTCn Destination DEC mode (DMADn -) (DMASn) DMACn - 1 DMACn if DMACn = 0 then INTTCn Source INC mode (DMADn) (DMASn +) DMACn DMACn - 1 if DMACn = 0 then INTTCn Source DEC mode (DMADn) (DMASn -) DMACn DMACn - 1 if DMACn = 0 then INTTCn Source and Destination INC mode (DMADn +) (DMASn +) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source and Destination DEC mode (DMADn -) (DMASn -) DMACn DMACn - 1 If DMACn = 0 then INTTCn Destination and Fixed mode (DMADn) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTCn Counter mode DMASn DMASn + 1 DMACn DMACn - 1 If DMACn = 0 then INTTCn Execution time 5states 5states 5states 5states 6states 6states 5states 5states ZZ: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = (reserved) Note1: The execution time is measured at 1states = 50ns (operation @internal 20 MHz) Note2: n stands for the micro DMA channel number (0 to 7) DMADn+/DMASn+: Post-increment (register value is incremented after transfer) DMADn-/DMASn-: Post-decrement (register value is decremented after transfer) 92CD54I-29 2006-01-27 TMP92CD54I 3.4.3 Interrupt controller operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 51 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: when a Reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writting a micro DMA start vector to the INTCLR register). An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g. INTE0AD or INTE12). Six interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and Watchdog Timer interrupts) is fixed at 7. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt's vector address to the CPU. The CPU compares the mask value set in 92CD54I-30 2006-01-27 Interrupt controller Interrupt request F/F S R V = 20H V = 24H CPU 1 NMI Q Interrupt mask F/F RESET Interrupt request RESET interrupt vector read Priority setting register Dn A Dn + 1 INTWD Decoder Priority encoder signal to CPU IFF2:0 3 3 1 7 6 6 B C EI 1 to 7 DI Interrupt level detect Interrupt request signal D Dn + 2 Q CLR Interrupt request F/F Q Interrupt request F/F D1 51 Interrupt vector generator Y1 Y2 Y3 Y4 Y5 Y6 INT0 Dn + 3 Reset S R Interrupt vector read Micro DMA acknowledge V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH 1 A 2 3 INTRQ2 to 0 3 Highest B Priority 4 interrupt C 5 level select Interrupt vector V read 6 D0 7 if INTRQ2:0IFF2:0 then 1. INT1 INT2 INT3 INT4 INT5 INT6 INT7 INTT0 INTT1 D2 D3 D4 D5 D6 D7 During IDLE1 During STOP Figure 3.4.3 Block Diagram of Interrupt Controller 92CD54I-31 6 V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH HALT release Micro DMA Counter Zero Interrupt RESET INT0 NMI 8 8 input OR Micro DMA request INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 Micro DMA start vector setting register 6 Match Detect D5 D4 D3 D2 D1 D0 DQ CLR 6 Soft start INTTC0 DMA0V DMA1V : DMA7V if 1IFF2:06 then 1. 0 1 2 3 4 5 6 7 RESET A B C Micro DMA channel priority encoder 3 3 Micro DMA channel specification TMP92CD54I 2006-01-27 TMP92CD54I (1) Interrupt priority setting registers Symbol NAME INT0 & INTAD Enable Address 7 IADC R 0 I2C R 0 I4C R 0 I6C R 0 - 6 5 4 IADM0 0 I2M0 0 I4M0 0 I6M0 0 IT1M0 0 IT3M0 0 IT5M0 0 IT7M0 0 IT9M0 0 ITBM0 0 ITOAM0 3 I0C R 0 I1C R 0 I3C R 0 I5C R 0 I7C R 0 IT0C R 0 IT2C R 0 IT4C R 0 IT6C R 0 IT8C R 0 ITAC R 0 ITO8C R 0 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INT5 I5M2 0 INT7 I7M2 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 I5M1 R/W 0 0 (Note) I0M0 0 I1M0 0 I3M0 0 I5M0 0 I7M0 0 IT0M0 0 IT2M0 0 IT4M0 0 IT6M0 0 IT8M0 0 ITAM0 0 ITO8M0 0 INTE0AD F0h INTE12 INT1 & INT2 Enable D0h INTE34 INT3 & INT4 Enable D1h INTE56 INT5 & INT6 Enable D2h INTAD IADM2 IADM1 R/W 0 0 INT2 I2M2 I2M1 R/W 0 0 INT4 I4M2 I4M1 R/W 0 0 INT6 I6M2 I6M1 R/W 0 0 - INTE7 INT7 Enable D7h INTET01 INTT0 & INTT1 Enable D4h IT1C R 0 IT3C R 0 IT5C R 0 IT7C R 0 IT9C R 0 ITBC R 0 ITOAC R 0 INTET23 INTT2 & INTT3 Enable D5h INTET45 INTT4 & INTT5 Enable D6h INTET67 INTT6 & INTT7 Enable D7h INTET89 INTTR8 & INTTR9 Enable INTTRA & INTTRB Enable D8h INTETAB D9h INTTO8 & INTTOA INTETO8A (Overflow) Enable INTT1(Timer1) IT1M2 IT1M1 R/W 0 0 INTT3(Timer3) IT3M2 IT3M1 R/W 0 0 INTT5(Timer5) IT5M2 IT5M1 R/W 0 0 INTT7(Timer7) IT7M2 IT7M1 R/W 0 0 INTTR9(Timer8) IT9M2 IT9M1 R/W 0 0 INTTRB(TimerA) ITBM2 ITBM1 R/W 0 0 INTTOA ITOAM2 ITOAM1 DAh 0 R/W 0 0 I7M1 R/W 0 0 INTT0(Timer0) IT0M2 IT0M1 R/W 0 0 INTT2(Timer2) IT2M2 IT2M1 R/W 0 0 INTT4(Timer4) IT4M2 IT4M1 R/W 0 0 INTT6(Timer6) IT6M2 IT6M1 R/W 0 0 INTTR8(Timer8) IT8M2 IT8M1 R/W 0 0 INTTRA(TimerA) ITAM2 ITAM1 R/W 0 0 INTTO8 ITO8M2 ITO8M1 R/W 0 0 Note: When any bit of WUPMASK 92CD54I-32 2006-01-27 TMP92CD54I Symbol INTES0 NAME INTRX0 & INTTX0 Enable Address 7 ITX0C R 0 ITX1C R 0 ICTC R 0 - DBh INTES1 INTRX1 & INTTX1 Enable DCh INTECRT INTCR & INTCT Enable DDh 5 INTTX0 ITX0M2 ITX0M1 R/W 0 0 INTTX1 ITX1M2 ITX1M1 R/W 0 0 INTCT ICTM2 ICTM1 R/W 0 0 INTSEE0 - 6 4 ITX0M0 0 ITX1M0 0 ICTM0 0 - 3 IRX0C R 0 IRX1C R 0 ICRC R 0 ICGC R 0 ISEM0C INTECG INTCG Enable DEh 1 0 INTRX0 IRX0M2 IRX0M1 IRX0M0 R/W 0 0 0 INTRX1 IRX1M2 IRX1M1 IRX1M0 R/W 0 0 0 INTCR ICRM2 ICRM1 ICRM0 R/W 0 0 0 INTCG ICGM2 ICGM1 ICGM0 R/W 0 0 0* INTSEM0 ISEM0M2 ISEM0M1 ISEM0M0 2 INTESEE0 INTSEM0 & INTSEE0 Enable DFh ISEE0C ISEE0M2 ISEE0M1 ISEE0M0 R 0 ISET0C R/W 0 0 INTSET0 R/W 0 INTSBS2 0 R 0 ISER0C R/W 0 0 INTSER0 R/W 0 INTRTC IRTCM1 0 INTESED0 INTSER0 & INTSET0 Enable E0h ISET0M2 ISET0M1 ISET0M0 ISER0M2 ISER0M1 ISER0M0 R 0 - 0 - 0 - R 0 IRTCC 0 0 IRTCM0 INTERTC INTRTC Enable E1h IRTCM2 R 0 ISBE2C R/W 0 0 INTSBE2 R/W 0 0 INTSBE0 R/W 0 0 INTSBE1 R/W 0 0 INTTC0(DMA0) ITC0M2 ITC0M1 R/W 0 0 INTTC2(DMA2) ITC2M2 ITC2M1 R/W 0 0 INTTC4(DMA4) ITC4M2 ITC4M1 R/W 0 0 INTTC6(DMA6) ITC6M2 ITC6M1 R/W 0 0 0 INTESB2 INTSBE2 & INTSBS2 Enable E2h ISBS2C ISBS2M2 ISBS2M1 ISBS2M0 ISBE2M2 ISBE2M1 ISBE2M0 R 0 ISBS0C R/W 0 0 INTSBS0 R/W 0 0 INTSBS1 R/W 0 0 INTTC1(DMA1) ITC1M2 ITC1M1 R/W 0 0 INTTC3(DMA3) ITC3M2 ITC3M1 R/W 0 0 INTTC5(DMA5) ITC5M2 ITC5M1 R/W 0 0 INTTC7(DMA7) ITC7M2 ITC7M1 R/W 0 0 0 R 0 ISBE0C 0 INTESB0 INTSBE0 & INTSBS0 Enable E3h ISBS0M2 ISBS0M1 ISBS0M0 ISBE0M2 ISBE0M1 ISBE0M0 R 0 ISBS1C 0 R 0 ISBE1C 0 INTESB1 INTSBE1 & INTSBS1 Enable E4h ISBS1M2 ISBS1M1 ISBS1M0 ISBE1M2 ISBE1M1 ISBE1M0 R 0 ITC1C R 0 ITC3C R 0 ITC5C R 0 ITC7C R 0 0 ITC1M0 0 ITC3M0 0 ITC5M0 0 ITC7M0 0 R 0 ITC0C R 0 ITC2C R 0 ITC4C R 0 ITC6C R 0 0 ITC0M0 0 ITC2M0 0 ITC4M0 0 ITC6M0 0 INTETC01 INTTC0 & INTTC1 Enable INTTC2 & INTTC3 Enable F1h INTETC23 F2h INTETC45 INTTC4 & INTTC5 Enable F3h INTETC67 INTTC6 & INTTC7 Enable F4h 92CD54I-33 2006-01-27 TMP92CD54I Symbol NAME Address 7 INMIC R 0 6 NMI F7h IWDC R 0 5 4 3 2 INTWD 1 0 NMI & INTNMWDT INTWD Enable Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 LxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function ( write ) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Note: After executing DI command previously, the setting value of "Interrupt priority setting register" should change. (2) External interrupt control Symbol NAME Address 7 6 5 4 3 2 1 I0LE 0 R/W 0 NMIREE 0 Interrupt - - - - - IIMC Input Mode Control F6H (no RMW) INT0 mode NMI mode 0:edge 0:Falling mode 1:level mode edge 1:Falling & rising edges INT0 Level Enable 0 Rising edge detect INT 1 "H"level INT NMI rising edge Enable 0 INT request generation at falling edge 1 INT request generation at rising and falling edge Note 1 : Disable INT0 request before changing INT0 pin mode from level-sense to edge-sense. Then, execute EI instruction after waiting 3-cycles (3 times NOP instruction). Setting example: DI LD (IIMC), XXXXXX0-B LD (INTCLR), 0AH NOP NOP NOP EI ; Disable interrupts ; Switches from level to edge. ; Clears interrupt request flag. ; Wait 3-cycles ; Enable interrupts Note: X = Don't care; "-" = No change. Note 2 : See electrical characteristics in section 4 for external interrupt input pulse width. 92CD54I-34 2006-01-27 TMP92CD54I Table 3.4.2 Settings of External interrupt Pin Function Interrupt NMI Pin name NMI Mode Falling Edge Falling and Rising Edges Rising Edge High Level Rising Edge Rising Edge Rising Edge Rising Edge Rising Edge Falling Edge Rising Edge Rising Edge Falling Edge Falling and Rising Edges Falling Edge Rising Edge Falling and Rising Edges Falling Edge Rising Edge Falling and Rising Edges Falling Edge Rising Edge Falling and Rising Edges Falling Edge Rising Edge Falling and Rising Edges Falling Edge Rising Edge Falling and Rising Edges Falling Edge Rising Edge Falling and Rising Edges Falling Edge Rising Edge Falling and Rising Edges Falling Edge Rising Edge TMODA INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT0 PC0 PC2 PC3 PC5 PD0 PD1 PD4 WUINT0 PD0 WUINT1 PD1 WUINT2 PD2 WUINT3 PD3 WUINT4 PD4 WUINT5 PD5 WUINT6 PD6 WUINT7 PD7 92CD54I-35 2006-01-27 TMP92CD54I (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH Symbol NAME Interrupt Clear control Address F8H (no RMW) ; Clears interrupt request flag INT0. 7 0 6 0 5 0 4 3 2 0 1 0 0 0 INTCLR W 0 0 Interrupt Vector (4) Micro DMA start vector registers These registers assign an interrupt source which makes a micro DMA processing start. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel's micro DMA start vector register again, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.) 92CD54I-36 2006-01-27 TMP92CD54I Symbol DMA0V NAME DMA0 Start Vector DMA1 Start Vector DMA2 Start Vector DMA3 Start Vector DMA4 Start Vector DMA5 Start Vector DMA6 Start Vector DMA7 Start Vector Address 100h (no RMW) 7 - 6 - 5 DMA0V5 4 DMA0V4 3 2 DMA0 Start Vector DMA0V3 DMA0V2 1 DMA0V1 0 DMA0V0 0 DMA1V5 0 DMA1V4 R/W 0 0 DMA1 Start Vector DMA1V3 DMA1V2 0 DMA1V1 0 DMA1V0 DMA1V 101h (no RMW) - R/W 0 DMA2V5 0 DMA2V4 0 0 DMA2 Start Vector DMA2V3 DMA2V2 0 DMA2V1 0 DMA2V0 DMA2V 102h (no RMW) - R/W 0 DMA3V5 0 DMA3V4 0 0 DMA3 Start Vector DMA3V3 DMA3V2 0 DMA3V1 0 DMA3V0 DMA3V 103h (no RMW) - R/W 0 DMA4V5 0 DMA4V4 0 0 DMA4 Start Vector DMA4V3 DMA4V2 0 DMA4V1 0 DMA4V0 DMA4V 104h (no RMW) - R/W 0 DMA5V5 0 DMA5V4 0 0 DMA5 Start Vector DMA5V3 DMA5V2 0 DMA5V1 0 DMA5V0 DMA5V 105h (no RMW) - R/W 0 DMA6V5 0 DMA6V4 0 0 DMA6 Start Vector DMA6V3 DMA6V2 0 DMA6V1 0 DMA6V0 DMA6V 106h (no RMW) - R/W 0 DMA7V5 0 DMA7V4 0 0 DMA7 Start Vector DMA7V3 DMA7V2 0 DMA7V1 0 DMA7V0 DMA7V 107h (no RMW) - R/W 0 0 0 0 0 0 (5) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the Transfer Counter Register reaches zero. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol DMAB NAME DMA Burst Address 108h (no RMW) 7 DBST7 6 DBST6 5 DBST5 4 DBST4 3 DBST3 2 DBST2 1 DBST1 0 DBST0 R/W 0 0 0 0 0 0 0 0 92CD54I-37 2006-01-27 TMP92CD54I (6) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid this, an instruction which clears an interrupt request flag should always be preceded by a DI instruction. In addition, please note that the following two circuits are exceptional and demand special attention. INT0 Level Mode In Level Mode INT0 is not an edge-triggered interrupt. Hence, in Level Mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from Edge Mode to Level Mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to Level Mode so as to release a Halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the Halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the Halt state has been released.) When the mode changes from Level Mode to Edge Mode, interrupt request flags which were set in Level Mode will not be cleared. Interrupt request flags must be cleared using the following sequence. Also EI instruction should be execuse after waiting 3-cycle. DI LD (IIMC), 00H LD (INTCLR), 0AH NOP NOP NOP EI ; Switches from level to edge. ; Clears interrupt request flag. ; Wait 3-cycle INTRX The interrupt request flip-flop can only be cleared by a Reset or by reading the Serial Channel Receive Buffer. It cannot be cleared by an instruction. Note: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. INT0: Instructions which switch to Level Mode after an interrupt request has been generated in Edge Mode. The pin input changes from High to Low after an interrupt request has been generated in Level Mode. ("H" "L") INTRX: Instructions which read the Receive Buffer 92CD54I-38 2006-01-27 TMP92CD54I 3.4.4 Interrupt Mask register TMP92CD54I has Interrupt Mask registers. Unlike Interrupt priority register, Interrupt mask register only disables or enables interrupts. An interrupt will not be generated, if the interrupt is disabled by Interrupt mask register, even if the interrupt has been enabled by setting Interrupt priority register. One, two or more interrupt factors can be prohibited synchronous by setting of Interrupt Mask register. After reset, all bits in Interrupt mask register are initialize 1 (enabled interrupts). It is necessary to write 0 in the corresponding bit in case of making interrupt Mask register to prohibit interrupt. Internal I/O & external interrupts (except NMI, INTWD, INTTC0 to 7) SIO I2C TMR CAN MASK INTC Interrupt Signals Interrupt Mask registers Data Bus Address Bus Figure 3.4.4 Block Diagram of Interrupt Mask Control Symbol NAME Address 7 MKI7 6 MKI6 1 INT6 0: Mask 1: Enable MKIT6 1 INTT6 0: Mask 1: Enable MKIRTC 1 INTRTC 0: Mask 1: Enable 5 MKI5 1 INT5 0: Mask 1: Enable MKIT5 1 INTT5 0: Mask 1: Enable MKITOA 1 INTTOA 0: Mask 1: Enable 4 MKI4 R/W 1 INT4 0: Mask 1: Enable MKIT4 R/W 1 INTT4 0: Mask 1: Enable MKITO8 1 INTTO8 0: Mask 1: Enable 3 MKI3 1 INT3 0: Mask 1: Enable MKIT3 1 INTT3 0: Mask 1: Enable MKITRB R/W 1 INTTRB 0: Mask 1: Enable 2 MKI2 1 INT2 0: Mask 1: Enable MKIT2 1 INTT2 0: Mask 1: Enable MKITRA 1 INTTRA 0: Mask 1: Enable 1 MKI1 1 INT1 0: Mask 1: Enable MKIT1 1 INTT1 0: Mask 1: Enable MKITR9 1 INTTR9 0: Mask 1: Enable 0 MKI0 1 INT0 0: Mask 1: Enable MKIT0 1 INTT0 0: Mask 1: Enable MKITR8 1 INTTR8 0: Mask 1: Enable Interrupt INTMK0 Mask Control 0 E5H 1 INT7 0: Mask 1: Enable MKIT7 Interrupt INTMK1 Mask Control 1 E6H 1 INTT7 0: Mask 1: Enable - Interrupt INTMK2 Mask Control 2 E7H - 92CD54I-39 2006-01-27 TMP92CD54I Symbol NAME Address 7 Interrupt - 6 MKICG 1 INTCG 0: Mask 1: Enable 5 MKICT 1 INTCT 0: Mask 1: Enable - 4 MKICR 1 INTCR 0: Mask 1: Enable - 3 MKITX1 R/W 1 INTTX1 0: Mask 1: Enable MKISET0 1 INTSET 0: Mask 1: Enable 2 MKIRX1 1 INTRX1 0: Mask 1: Enable MKISER0 1 INTSER 0: Mask 1: Enable MKISBE1 1 INTSBE1 0: Mask 1: Enable 1 MKITX0 1 INTTX0 0: Mask 1: Enable MKISEE0 1 INTSEE 0: Mask 1: Enable MKISBS0 1 INTSBS0 0: Mask 1: Enable 0 MKIRX0 1 INTRX0 0: Mask 1: Enable MKISEM0 1 INTSEM 0: Mask 1: Enable MKISBE0 1 INTSBE0 0: Mask 1: Enable INTMK3 Mask Control 3 E8H Interrupt - - R/W E9H INTMK4 Mask Control 4 Interrupt - MKISBS2 1 INTSBS2 0: Mask 1: Enable MKISBE2 1 INTSBE2 0: Mask 1: Enable MKIAD 1 INTAD 0: Mask 1: Enable MKISBS1 R/W 1 INTSBS1 0: Mask 1: Enable INTMK5 Mask Control 5 EAH Maskable bit for INTAD request 0 INTAD is disabled 1 INTAD is enabled Note: Port D0, D1 and D4 have 2 kinds of interrupt source (PD0:INT5/WUINT0, PD1:INT6/WUINT1, PD4:INT7/WUINT4). If both interrupt requests are generated in both interrupt enabled status, both interrupt processing will be executed. When any of these interrupts is used, set Interrupt Mask register or Wake UP Mask register to enable/disable. Example of register setting: In the case of setting INT0 interrupt priority level to 7 from 3. LD (INTE0AD), 03H LD (INTMK0), 01H EI : : DI LD (INTMK0), 00H LD (INTE0AD), 07H LD (INTCLR), 0AH NOP NOP NOP LD (INTMK0), 01H EI ; Set INT0 level to 3 ; Enable INT0 ; Enable interrupt operation ; running program ; Disable interrupt operation ; Disable INT0 ; Set INT0 level to 7 ; Clear INT0 request ; Wait 3 cycles ; Enable INT0 ; Enable interrupt operation 92CD54I-40 2006-01-27 TMP92CD54I 3.4.5. ON/OFF LOGIC TMP92CD54I has 8 pins (WUINT0 to WUINT7) for wake up from standby mode. These pins are multiplexed with Port D (PD0 to PD7). All wake up events can release standby mode and triggering edge can be independently programmable as both rising and falling edge, rising edge or falling edge. It is possible to mask all wake up events independently. WUINT0 WUINT1 WUINT2 WUINT3 WUINT4 WUINT5 WUINT6 External Interrupts WUINT7 Edge select & Interrupt Mask A INT0 INT0 8OR B Selector S Interrupt Controller Clock Control etc. 8OR INTMK0 Mode control register Edge select register Flag status register Mask Register Internal bus Figure 3.4.5 Block diagram of ON/OFF logic Using ON/OFF logic, all interrupt signals of WUINT0 to 7 are sent to INT0 in internal logic. When any WUINTn requests are generated, INT0 interrupt request will be generated. Like external INT0, also INT0 from WUINTn is set disable/enable by Interrupt priority register or Interrupt mask register. Writing 1 to any bit in WUPMASK register, INT0 switches ON/OFF logic mode. In this case, WUINTn written 1 in WUPMASK register are enabled, external INT0 cannot use. When external INT0 is used, write 00 to WUPMASK register. Selection edge of WUINTn signal uses WUPMOD and WUPEDGE register, rising edge, falling edge or both falling and rising edge are selectable. Reading WUPFLAG register, request/no-request of WUINTn will be confirmed. 92CD54I-41 2006-01-27 TMP92CD54I Wake UP FLAG status Register 7 6 WFLG6 5 WFLG5 4 WFLG4 3 WFLG3 2 WFLG2 1 WFLG1 0 WFLG0 WUPFLAG Symbol Read/Write After reset function WFLG7 R/W 0 WUINT7 0:NO request 1: request 0 WUINT6 0:NO request 1: request 0 WUINT5 0:NO request 1: request 0 WUINT4 0:NO request 1: request 0 WUINT3 0:NO request 1: request 0 WUINT2 0:NO request 1: request 0 WUINT1 0:NO request 1: request 0 WUINT0 0:NO request 1: request (00ECH) Wake UP Mode Control Register 7 6 WMD6 5 WMD 5 4 WMD4 3 WMD3 2 WMD2 1 WMD1 0 WMD0 Symbol Read/Write After reset WUPMOD WMD7 R/W 0 WUINT7 0:Falling & Rising Edge 1:Falling or Rising Edge 0 WUINT6 0:Falling & Rising Edge 1:Falling or Rising Edge 0 WUINT5 0:Falling & Rising Edge 1:Falling or Rising Edge 0 WUINT4 0:Falling & Rising Edge 1:Falling or Rising Edge 0 WUINT3 0:Falling & Rising Edge 1:Falling or Rising Edge 0 WUINT2 0:Falling & Rising Edge 1:Falling or Rising Edge 0 WUINT1 0:Falling & Rising Edge 1:Falling or Rising Edge 0 WUINT0 0:Falling & Rising Edge 1:Falling or Rising Edge (00EDH) function Wake UP Edge Select Register 7 6 WED6 5 WED 5 4 WED4 3 WED3 2 WED2 1 WED1 0 WED0 WUPEDGE Symbol Read/Write After reset function WED7 R/W 0 WUINT7 0:Falling Edge 1:Rising Edge 0 WUINT6 0:Falling Edge 1:Rising Edge 0 WUINT5 0:Falling Edge 1:Rising Edge 0 WUINT4 0:Falling Edge 1:Rising Edge 0 WUINT3 0:Falling Edge 1:Rising Edge 0 WUINT2 0:Falling Edge 1:Rising Edge 0 WUINT1 0:Falling Edge 1:Rising Edge 0 WUINT0 0:Falling Edge 1:Rising Edge (00EEH) Note: WUPEDGE register is used with setting each WUPMOD Wake UP Mask Register 7 WUPMASK 6 WMK6 5 WMK5 4 WMK4 3 WMK3 2 WMK2 1 WMK1 0 WMK0 (00EFH) Symbol Read/Write After reset function WMK7 R/W 0 WUINT7 0: Disable 1: Enable 0 WUINT6 0: Disable 1: Enable 0 WUINT5 0: Disable 1: Enable 0 WUINT4 0: Disable 1: Enable 0 WUINT3 0: Disable 1: Enable 0 WUINT2 0: Disable 1: Enable 0 WUINT1 0: Disable 1: Enable 0 WUINT0 0: Disable 1: Enable Wake up interrupt mask control 0 WUINTn Disabled (MASK) 1 WUINTn Enabled Note1: Port D0, D1 and D4 have 2 kinds of interrupt source (PD0: INT5/WUINT0, PD1: INT6/WUINT1, PD4:INT7/WUINT4). If both interrupt requests are generated in both interrupt enabled status, both interrupt processing will be executed. When each interrupts is used, set Interrupt Mask register or Wake UP Mask register to enable/disable. Even if port D is any of Input/Output port, INTn, and WUINTn, the level of port D is inputted into these interrupts. For details, refer to the block diagram of the port. When any WUPMASK Note2: 92CD54I-42 2006-01-27 TMP92CD54I Example of register setting: To set WUINT0 with rising edge and set interrupt level 3, set the registers as follows: DI LD (INTMK0), 00H LD (PDFC), 00H LD (PDCR), 00H LD (WUPMOD), 01H LD (WUPEDGE), 01H LD (WUPFLAG), 00H LD (INTE0AD), 03H LD (INTCLR), 0AH NOP NOP NOP LD (INTMK0), 01H EI ; Disable interrupt operation ; Disable INT0 ; Set PD0 as port mode ; Set PD0 as input mode ; Set WUINT0 as "Falling or rising edge" ; Set WUINT0 to "Rising edge" ; Clear WUINT0 flag ; Set INT0 (function as WUINT0) interrupt level to 3 ; Clear INT0 request flag ; Wait 3 cycles ; Enable WUINT0 ; Enable interrupt operation 92CD54I-43 2006-01-27 TMP92CD54I 3.5 Function of Ports TMP92CD54I has I/O port pins that are shown in table 3.5.1. In addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table 3.5.1 Port Functions (1/2) Port Name Pin Name Number of Pins I/O I/O Setting Pin Name for built-in function Port 0 Port 4 Port 7 P00 to P07 P40 to P47 P70 P71 P72 P73 P74 P75 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 4 1 1 1 1 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit D0 to D7 A0 to A7 RD WR SI2/SCL2 CS WAIT Port C PC0 PC1 PC2 PC3 PC4 PC5 TI0 / INT1 TO1 TO3 / INT2 TI4 / INT3 TO5 TO7 / INT4 TI8 / INT5 / A16 / WUINT0 TI9 / INT6 / A17 / WUINT1 TO8 / A18 / WUINT2 TO9 / A19 / WUINT3 TIA / INT7 / A20 / WUINT4 TIB / A21 / WUINT5 TOA / A22 / WUINT6 TOB / A23 / WUINT7 TXD0 RXD0 SCLK0 / CTS0 TXD1 RXD1 SCLK1 / CTS1 TX RX AN0 to AN7 AN8 to AN11 SS / A8 Port D PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Port F PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 Port G Port L Port M PG0 to PG7 PL0 to PL3 PM0 PM1 PM2 PM3 PM4 MOSI / A9 MISO / A10 SECLK / A11 SCK2 SCK0 SO0 / SDA0 SI0 / SCL0 SCK1 / A12 SO1 / SDA1 / A13 SI1 / SCL1 / A14 SO2 / SDA2 / A15 Port N PN0 PN1 PN2 PN3 PN4 PN5 PN6 92CD54I-44 2006-01-27 TMP92CD54I 3.5.1 Port 0 (P00 to P07) Port0 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P0CR and function register P0FC. In addition to functioning as a general-purpose I/O port, port0 can also function as a data bus (D0 to D7). P0CR register P0FC register External write strobe P0 register S 0 Port 0 P00 to P07 (D0 to D7) External write data S 1 Selector 1 0 Selector Port read data External read data External read strobe Figure 3.5.1 Port0 Table 3.5.2 Port0 Registers SYMBOL NAME PORT0 Address 00H 7 P07 0 P07C 6 P06 0 P06C 0 - 5 P05 0 P05C 0 - 4 P04 3 P03 2 P02 0 P02C 0 - 1 P01 0 P01C 0 - 0 P00 0 P00C 0 P0F W 0 P0 P0CR PORT0 Control Register PORT0 Function Register 02H (no RMW) 0 - R/W 0 0 Input/Output P04C P03C W 0 0 0:Input 1:Output - P0FC 03H (no RMW) 0:PORT 1:Data Bus(D7 to D0) P0FC 0 Input port Output port 1 Data bus (D0 to D7) Data bus (D0 to D7) 92CD54I-45 2006-01-27 TMP92CD54I 3.5.2 Port 4 (P40 to P47) Port4 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs or outputs by control register P4CR and function register P4FC. In addition to functioning as a general-purpose I/O port, port4 can also function as an address bus (A0 to A7). P4CR register P4FC register (reserved) P4 register S 0 1 Selector S 1 0 Selector S 0 1 Selector Address bus (reserved) Port read data (reserved) Port4 P40 to P47 (A0 to A7) (reserved) Figure 3.5.2 Port4 Table 3.5.3 Port4 Registers SYMBOL NAME PORT4 Address 10H 7 P47 0 P47C 6 P46 0 P46C 0 P46F 0 5 P45 0 4 P44 3 P43 2 P42 1 P41 0 P41C 0 P41F 0 0 P40 0 P40C 0 P40F 0 P4 P4CR PORT4 Control Register PORT4 Function Register 12H (no RMW) 0 P47F P4FC 13H (no RMW) 0 R/W 0 0 0 Input/Output P45C P44C P43C P42C W 0 0 0 0 0:Input 1:Output P45F P44F P43F P42F W 0 0 0 0 0:PORT 1:Address Bus(A0 to A7) P4FC 0 Input port Output port 1 Address bus (A0 to A7) Don't use this setting. 92CD54I-46 2006-01-27 TMP92CD54I 3.5.3 Port 7 (P70 to P75) Port7 is a 6-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70, P71 and P73 pins can also function as read/write strobe signals and chip selection to connect with an external memory. P72 pin can also function as I/O functions of serial bus interface which employs clocked-synchronous 8-bit SIO and I2C. P75 pin can also function as wait input. The pin is always enabled for the following input signals: SBI data input (SIO) SI2#1, SBI clock I/O (I2C) SCL2#1,. #1 : In IDLE3/STOP mode, input signal is valid (Input gate opened) A reset initializes P70, P71, P73 and P74 pins to output port mode, and P72, P75 pin to input port mode. P7CR register P7FC register P7 register Read strobe Port read data S 1 0 Selector 0 S 1 Selector P70 (RD ) P7CR register P7FC register P7 register Write strobe Port read data S 1 0 Selector 0 1 S Selector P71 ( WR ) P7CR register P7FC register P7 register (reserved) 0 S 0 1 S Selector 1 0 Selector S When PNODE register is "1", P72 signal is open drain output. SCL output Port read data SI/SCL input 1 Selector P72 (SI2/SCL2) Figure 3.5.3 Port7 (P70 to P72) 92CD54I-47 2006-01-27 TMP92CD54I P7CR register P7FC register P7 register Chip selection S S 0 1 Selector 1 0 P73 ( CS ) Port read data Selector P7CR register P7FC register P7 register (reserved) S S 0 1 P74 Selector 1 0 Port read data Selector P7CR register P7FC register P7 register P75 ( WAIT ) S 1 0 Port read data Wait request Selector Figure 3.5.4 Port7 (P73 to P75) 92CD54I-48 2006-01-27 TMP92CD54I Table 3.5.4 Port7 Registers SYMBOL NAME PORT7 Address 1CH 7 - 6 - 5 P75 0 P75C 0 P75F 0 0:PORT 1: WAIT 4 P74 1 P74C 1 P74F 0 0:PORT 3 P73 2 P72 1 P71 1 P71C 1 P71F 0 0:PORT 1: WR 0 P70 1 P70C 1 P70F 0 0:PORT 1:RD P7 P7CR PORT7 Control Register 1EH (no RMW) - P7FC PORT7 Function Register 1FH (no RMW) - R/W 1 1 Input/Output P73C P72C W 1 0 0:Input 1:Output P73F P72F W 0 0 0:PORT 0:PORT 1: CS 1:SI2 SCL2 Note1 P7CR 0 1 1 P7FC 0 0 1 - - P75 P74 Input Port Don't use this setting. Don't use this setting. P73 P72 Input Port, P71 P70 WAIT SI2 Output Port Don't use this CS setting. Input Port WR RD 0 1 WAIT CS SI2, SCL2 WR RD Note1: P72 SCL2, clock input/output at I2C mode, can be open-drain output by setting 1 to PNODE 92CD54I-49 2006-01-27 TMP92CD54I 3.5.4 Port C (PC0 to PC5) PortC is a 6-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PCCR and function register PCFC. In addition to functioning as a general-purpose I/O port, PortC can also function as 8-bit timer I/O and interrupt input. The pin is always enabled for the following input signals: timer inputs TI0#1, TI4#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) A reset initializes PortC to input port mode. PCCR register PCFC register PC register (Reserved) Port read data Timer input Interrupt request S 1 0 1 0 S PC0 (TI0/INT1) PC3 (TI4/INT3) PCCR register PCFC register PC register (Reserved) Timer output 1 0 S 1 0 S 1 0 S PC1 (TO1) PC2 (TO3/INT2) Port read data Interrupt request PCCR register PCFC register PC register Timer output S 1 0 0 1 S PC4 (TO5) PC5 (TO7/INT4) Port read data Interrupt request Figure 3.5.5 PortC (PC0 to PC5) 92CD54I-50 2006-01-27 TMP92CD54I Table 3.5.5 PortC Registers SYMBOL NAME PORTC Address 30H 7 - 6 - 5 PC5 0 PC5C 0 PC5F 0 0:PORT INT4 1:TO7 4 PC4 0 PC4C 0 PC4F 0 0:PORT 1:TO5 3 PC3 2 PC2 1 PC1 0 PC1C 0 PC1F 0 0:PORT 1:TO1 0 PC0 0 PC0C 0 PC0F 0 0:PORT INT1 TI0 PC PCCR PORTC Control Register 32H (no RMW) - PCFC PORTC Function Register 33H (no RMW) - R/W 0 0 Input/Output PC3C PC2C W 0 0 0:Input 1:Output PC3F PC2F W 0 0 0:PORT 0:PORT INT3 INT2 TI4 1:TO3 PCCR 0 1 1 0 PCFC 0 0 1 1 - - PC5 PC4 PC3 PC2 PC1 PC0 Input Port, Input Port, Input Port, Input Port, Input Port Input Port INT3, INT1, INT4 INT2 TI4 TI0 Output Port TO7 TO5 Output Port TO3 TO1 Output Port TO7 TO5 Do not use this setting 92CD54I-51 2006-01-27 TMP92CD54I 3.5.5 Port D (PD0 to PD7) PortD is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PDCR and function register PDFC. In addition to functioning as a general-purpose I/O port, PortD can also function as 16-bit timer I/O, interrupt input and wake up interrupt input. The pin is always enabled (excluding address bus setting) for the following input signals: 16-bit timer input TI8#1, TI9#1, TIA#1, TIB#1, external interrupt INT5#2 to INT7#2, wake up interrupt WUINT0#2 to WUINT7#2. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) #2 : In IDLE3/STOP mode, input signal is valid (Input gate opened) A reset initializes Port D to input port mode. PDCR register PDFC register PD register 0 S 1 Selector S Address bus 1 0 Selector PD0 (TI8/INT5/A16/WUINT0) PD1 (TI9/INT6/A17/WUINT1) PD4 (TIA/INT7/A20/WUINT4) PD5 (TIB/A21/WUINT5) Port read data Interrupt request Timer input Wake up request PDCR register PDFC register PD register S 0 1 Selector S 1 0 Selector S 0 1 Selector Address bus Timer output Port read data PD2 (TO8/A18/WUINT2) PD3 (TO9/A19/WUINT3) PD6 (TOA/A22/WUINT6) PD7 (TOB/A23/WUINT7) Wake up request Figure 3.5.6 PortD 92CD54I-52 2006-01-27 TMP92CD54I Table 3.5.6 PortD Registers SYMBOL NAME PORTD Address 34H 7 PD7 0 PD7C 6 PD6 0 PD6C 0 PD6F 0 0:PORT WUINT6 1:TOA A22 5 PD5 0 PD5C 0 PD5F 0 0:PORT TIB WUINT5 1:A21 4 PD4 3 PD3 2 PD2 0 PD2C 0 PD2F 0 0:PORT WUINT2 1:TO8 A18 1 PD1 0 PD1C 0 PD1F 0 0:PORT TI9 INT6 WUINT1 1:A17 0 PD0 0 PD0C 0 PD0F 0 0:PORT TI8 INT5 WUINT0 1: A16 PD PDCR PORTD Control Register 36H (no RMW) 0 PD7F PDFC PORTD Function Register 37H (no RMW) 0 0:PORT WUINT7 1:TOB A23 R/W 0 0 Input/Output PD4C PD3C W 0 0 0:Input 1:Output PD4F PD3F W 0 0 0:PORT 0:PORT TIA WUINT3 INT7 1:TO9 WUINT4 A19 1:A20 PDCR 0 1 1 0 PDFC 0 0 1 1 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Input Port, Input Port, Input Port, Input Port, Input Port, Input Port, Input Port, Input Port, INT5, INT6, INT7, TIB, TI8, TI9, WUINT3 WUINT2 WUINT7 WUINT6 TIA, WUINT5 WUINT1 WUINT0 WUINT4 Output Port TI8, TIA, TI9, TIB, TOB TOA, TO9 TO8 INT5, INT7, INT6, WUINT5 WUINT4 WUINT1 WUINT0 A23 A22 A21 A20 A19 A18 A17 A16 Note: Port D0, D1 and D4 have 2 kinds of interrupt source (PD0: INT5/WUINT0, PD1: INT6/WUINT1, PD4: INT7/WUINT4). If both interrupt requests are generated in both interrupt enabled status, both interrupt processing are executed. When each interrupts is used, set Interrupt Mask register or Wake UP Mask register to enable/disable. If these ports are used as output/input ports, first, disable interrupt request, then set PDFC and PDCR (cf Timers). 92CD54I-53 2006-01-27 TMP92CD54I 3.5.6 Port F (PF0 to PF7) PortF is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or o outputs by control register PFCR and function register PFFC. In addition to functioning as a general-purpose I/O port, PortF can also function as serial channels I/O function and controller area network (CAN). The pin is always enabled for the following input signals: serial receive data RXD0#1, RXD1#1, CAN receive data RX#1, Clear-to-send CTS0#1, CTS1#1, and serial clock SCLK0#1, SCLK1#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) A reset initializes PortF to input port mode. PFCR register PFFC register When PFCR register is "0" and PFFC register is "1", TXD is open drain output. S 0 PF register PF0 (TXD0) PF3 (TXD1) TXD output S 1 0 Selector 1 Selector Port read data PFCR register PFFC register PF register S 0 PF6 (TX) TX output S 1 0 Selector 1 Selector Port read data Figure 3.5.7 PortF (PF0, PF3, PF6) 92CD54I-54 2006-01-27 TMP92CD54I PFCR register PFFC register PF register PF1 (RXD0) S Port read data RXD input 1 0 PF4 (RXD1) PF7 (RX) Selector PFCR register PFFC register PF register S 0 1 Selector S 1 0 Selector S 0 1 Selector (reserved) SCLK output Port read data SCLK input CTS input PF2 (SCLK0/CTS0) PF5 (SCLK1/CTS1) Figure 3.5.8 PortF (PF1, PF2, PF4, PF5, PF7) 92CD54I-55 2006-01-27 TMP92CD54I Table 3.5.9 PortF Registers SYMBOL NAME PORTF Address 3CH 7 PF7 0 PF7C 6 PF6 0 PF6C 0 PF6F 0 0:PORT 1:TX 5 PF5 0 PF5C 0 PF5F 0 0:PORT CTS1 1:SCLK1 4 PF4 3 PF3 2 PF2 0 PF2C 0 PF2F 0 0:PORT CTS0 1:SCLK0 1 PF1 0 PF1C 0 PF1F 0 0:PORT 1:RXD0 0 PF0 0 PF0C 0 PF0F 0 0:PORT 1:TXD0 PF PFCR PORTF Control Register 3EH (no RMW) 0 PF7F PFFC PORTF Function Register 3FH (no RMW) 0 0:PORT 1:RX R/W 0 0 Input/Output PF4C PF3C W 0 0 0:Input 1:Output PF4F PF3F W 0 0 0:PORT 0:PORT 1:RXD1 1:TXD1 PFCR PFFC PF7 Input Port, RX PF6 Input Port PF5 Input Port, SCLK1 (Input), CTS1 SCLK1 (Output) Don't use this Setting. PF4 Input Port, RXD1 PF3 Input Port PF2 Input Port, SCLK0 (Input), CTS0 SCLK0 (Output) Don't use this Setting. PF1 Input Port, RXD0 PF0 Input Port 0 0 1 1 0 0 1 1 RX RX TX TX Output Port RXD1 RXD1 TXD1 TXD1 (Open Drain) RXD0 RXD0 TXD0 TXD0 (Open Drain) 92CD54I-56 2006-01-27 TMP92CD54I 3.5.7 Port G (PG0 to PG7) PortG is an 8-bit general-purpose input-only port. In addition to functioning as a general-purpose input-only port, PortG can also function as input functions of AD converter. The pin is always enabled for the following input signals: AD converter input AN0#1 to AN7#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) Port read data PortG PG0 to PG7 (AN0 to AN7) AD converter input Figure 3.5.9 PortG Table 3.5.8 PortG Register SYMBOL NAME PORTG Address 40H 7 PG7 6 PG6 5 PG5 4 PG4 R Input 3 PG3 2 PG2 1 PG1 0 PG0 PG 92CD54I-57 2006-01-27 TMP92CD54I 3.5.8 Port L (PL0 to PL3) PortL is a 4-bit general-purpose input-only port. In addition to functioning as a general-purpose input-only port, PortL can also function as input functions of AD converter. The pin is always enabled for the following input signals: AD converter input AN8#1 to AN11#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) Port read data PortL PL0 to PL3 (AN8 to AN11) AD converter input Figure 3.5.10 PortL Table 3.5.9 PortL Register SYMBOL NAME PORTL Address 54H 7 - 6 - 5 - 4 - 3 PL3 2 PL2 R Input 1 PL1 0 PL0 PL 92CD54I-58 2006-01-27 TMP92CD54I 3.5.9 Port M (PM0 to PM4) PortM is a 5-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PMCR and function register PMFC. In addition to functioning as a general-purpose I/O port, PM0 to PM3 can also function as I/O functions of serial expansion interface. PM4 can also function as I/O function of serial bus interface which employs clocked-synchronous 8-bit SIO. The pin is always enabled for the following input signals: slave select SS #1, transmitting/ receiving serial data MOSI#1, MISO#1, SEI clock SECLK#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) A reset initializes PortM to input port mode. PMCR register PMFC register PM register 0 S 1 Selector S 1 0 Selector Address bus PM0 ( SS /A8) Port read data SS input SEI monitor MOSI, MISO, SECLK output enable PMCR register PMFC register When PMODE register is "1", PM1 to PM3 signals are open drain output. S 0 1 Selector S 1 0 Selector PM register Address bus MOSI output MISO output SECLK output Port read data MOSI input MISO input SECLK input 0 1 Selector S PM1 (MOSI/A9) PM2 (MISO/A10) PM3 (SECLK/A11) Figure 3.5.11 PortM (PM0 to PM3) 92CD54I-59 2006-01-27 TMP92CD54I PMCR register PMFC register PM register (reserved) 0 S 1 Selector S 1 0 Selector S 0 1 Selector SCK output Port read data PM4 (SCK2) SCK input Figure 3.5.12 PortM (PM4) Table 3.5.10 PortM Registers SYMBOL NAME PORTM Address 58H 7 - 6 - 5 - 4 PM4 0 - PM PMODE PORTM Open Drain Enable Register 59H PMCR PORTM Control Register 5AH (no RMW) - - - PM4C 0 PM4F 0 0:PORT 1:SCK2 PMFC PORTM Function Register 5BH (no RMW) - 2 1 PM2 PM1 R/W 0 0 0 Input/Output ODEM3 ODEM2 ODEM1 R/W 0 0 0 PM1 PM2 PM3 output output output 0:CMOS 0:CMOS 0:CMOS 1:Open 1:Open 1:Open Drain Drain Drain PM3C PM2C PM1C W 0 0 0 0:Input 1:Output PM3F PM2F PM1F W 0 0 0 0:PORT 0:PORT 0:PORT 1:SECLK A11 PM3 Input Port 1:MISO A10 PM2 Input Port Output Port 1:MOSI A9 PM1 Input Port 3 PM3 0 PM0 0 - PM0C 0 PM0F 0 0:PORT 1: SS A8 PM0 Input Port, SS PMCR 0 1 1 0 PMFC 0 0 1 1 - - - PM4 Input Port, SCK2 (Input) SCK2 (Output) Don't use this setting - - - SECLK A11 MISO A10 MOSI A9 SS A8 92CD54I-60 2006-01-27 TMP92CD54I 3.5.10 Port N (PN0 to PN6) PortN is a 7-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PNCR and function register PNFC. In addition to functioning as a general-purpose I/O port, PortN can also function as I/O functions of serial bus interface which employs clocked-synchronous 8-bit SIO and I2C. The pin is always enabled for the following input signals: SBI clock I/O (SIO) SCK0#1, SCK1#1, SBI data input (SIO) SI0#1, SI1#1, SBI clock I/O (I2C) SCL0#1, SCL1#1, SBI data I/O (I2C) SDA0#1, SDA1#1, SDA2#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) A reset initializes PortN to input port mode. PNCR register PNFC register PN register Address bus 0 S 1 Selector S 1 0 Selector S 0 1 Selector SCK output Port read data PN0 (SCK0) PN3 (SCK1/A12) SCK input PNCR register PNFC register When PNODE register is "1", PN1, PN2, PN4, PN5 and PN6 signals are open drain output. PN register Address bus SO/SDA output SCL output Port read data SDA input SI/SCL input 0 1 Selector S 1 0 Selector S S 0 1 Selector PN1 (SO0/SDA0) PN2 (SI0/SCL0) PN4 (SO1/SDA1/A13) PN5 (SI1/SCL1/A14) PN6 (SO2/SDA2/A15) Figure 3.5.13 PortN 92CD54I-61 2006-01-27 TMP92CD54I Table 3.5.11 PortN Registers SYMBOL PN NAME PORTN Address 5CH 7 6 PN6 0 5 PN5 0 4 PN4 0 3 PN3 2 PN2 1 PN1 0 PN0 PORTN Open Drain PNODE Enable Register PNCR PORTN Control Register PNFC PORTN Function Register R/W 0 0 0 0 Input/Output ODE72 ODEN6 ODEN5 ODEN4 ODEN2 ODEN1 R/W R/W 0 0 0 0 0 0 P72 PN6 PN5 PN4 PN2 PN1 5DH output output output output output output 0:CMOS 0:CMOS 0:CMOS 0:CMOS 0:CMOS 0:CMOS 1:Open 1:Open 1:Open 1:Open 1:Open 1:Open Drain Drain Drain Drain Drain Drain PN6C PN5C PN4C PN3C PN2C PN1C PN0C W 5EH (no RMW) 0 0 0 0 0 0 0 0:Input 1:Output PN6F PN5F PN4F PN3F PN2F PN1F PN0F W 0 0 0 0 0 0 0 5FH 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT (no RMW) 1:SCK1 SI0 1:SO0 1:SCK0 1:SO1 SI1 1: SO2 A12 1:SCL0 SDA0 SDA1 SDA2 1:SCL1 A13 A14 A15 PNCR 0 1 1 0 PNFC 0 0 1 1 - PN6 Input Port PN5 Input Port, SI1 PN4 PN3 PN2 Input Port, SI0 PN1 Input Port PN0 Input Port, SCK0 (Input) SO2/SDA2 SCL1 A14 A15 Input Input Port, Port SCK1 (Input) Output Port SCK1 SO1/SDA1 (Output) A13 A12 SCL0 SCK0 (Output) Don't use this setting. SO0/SDA0 92CD54I-62 2006-01-27 TMP92CD54I 3.6 Memory Controller 3.6.1 Memory controller functions TMP92CD54I has a memory controller with a variable 1-block external address area. The function is as follows. (1) 1-block external address area support. It specifies: A start address A block size for 1-block external address area (2) Connecting memory specifications. It specifies: SRAM ROM as memories to connect with the selected address area. (3) Data bus size 8-bit (4) Wait control Wait specification Wait input pin Both control the number of waits in the external access bus cycle. Read and write cycles can specify the number of waits individually. There are five modes all together: 0 wait, 1 wait, 2 wait, 3 wait, N wait (N is controlled with WAIT pin) 3.6.2 Control register and Operation after reset release This section describes the registers that control the memory controller, the state after reset release and necessary settings. (1) Control Registers Control registers (BCSH/BCSL: Block Chip Select High / Low) Sets the connecting memory type. (SRAM, ROM) Sets the number of waits to be read and written. Memory Start Address Register (MSAR) Sets a start address in the selected address areas. Memory Address Mask Register (MAMR) Sets a block size in the selected address areas. (2) Operation after reset release After reset release, The block address areas (specified by MSAR and MAMR) are set to address 000000H and FFFFEFH. Then BCSL / H is set. Set BCSH 92CD54I-63 2006-01-27 TMP92CD54I 3.6.3 Basic functions and registers setting In this section, Block address area specification, wait control and basic bus sizing are described. (1) Block address area specification If the bit BCSH Address CS CS TMP92CD54I OE RD WR Data (D0 to D7) RAM WE Figure 3.6.1 Example of connecting external memory (external RAM) 92CD54I-64 2006-01-27 TMP92CD54I (i) Setting memory start address register The MS23 to 16 bits of MSAR respectively correspond with addresses A23 to A16. The lower start address A15 to 0 is always set to address 0000H. Therefore, the start addresses of the block address area are set to addresses 000000H to FF0000H every 64KB (Because the settable LSB bit is 16th; 216 = 64 KB) (ii) Setting memory address mask register MAMR sets whether an address bit is compared or not. Set the register to 0 to compare, or to 1 not to compare. The combination of masked / enabled bits give the block size and therefore the address bit to be set depends on the block address area. Note: A23 is always compared. Thus, the block address area is between A22 and A15. The size to be set depending on the block address area is as follows: Size (bytes) CS area 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M CS Note: After reset release, BCSH (iii) Example of register setting To set the block address area 64 KB from address 110000H, set the registers as follows: MSB 76 MSAR 00 MAMR 00 5 0 0 4 1 0 3 0 0 2 0 0 1 0 0 LSB 0 1 ; set start address to 110000H 1 ; set block address area size to 64k-bytes Memory Start Address Register MSAR 92CD54I-65 2006-01-27 TMP92CD54I (iv) Case of overlapping blocks When the set block address area overlaps with the built-in memory area, the block address area is processed according to priorities as follows: Built-in I/O > Built-in memory > Block address area This means that the block address is not remapped but priorities are used to disable any conflict. Also note that any accessed areas outside the address spaces are set to 1 wait bus cycle ( CS signal is not outputted although RD and WR signal are outputted.). This factor depends on the speed of the external memory. It is a fixed parameter. (2) Wait control The external bus cycle completes a wait of two states at least (i.e. 100ns @fc = 20MHz). Setting the control register BCSL BWW/BWR bit (BCSL Regsiter) BWW2 BWR2 0 0 1 1 0 BWW1 BWR1 0 1 0 1 1 Others BWW0 BWR0 1 0 1 0 1 Function 2states (0 wait) access fixed mode 3states (1 wait) access fixed mode (Default) 4states (2 wait) access fixed mode 5states (3 wait) access fixed mode WAIT pin input mode (Reserved) (i) Waits number fixed mode The bus cycle is completed with the set states. The number of states is selected from 2 states (0WAIT) to 5 states (3WAIT). (ii) WAIT pin input mode This mode continuously samples the WAIT input pins and inserts a wait if the pin is active. The bus cycle is minimum 2 states and is therefore completed at 2 states when the wait signal is non active (High level). The bus cycle extends if the wait signal is active at 2 states and more. 92CD54I-66 2006-01-27 TMP92CD54I (3) Basic bus timing * External Read / Write Bus Cycle (0 WAIT) T1 CLK (20MHz) CS T2 ADDRESS RD read D7 to 0 WR input write D7 to 0 output * External Read / Write Bus Cycle (1 WAIT) T1 CLK (20MHz) CS ADDRESS RD TW T2 read D7 to 0 input WR write D7 to 0 output 92CD54I-67 2006-01-27 TMP92CD54I * External Read / Write Bus Cycle (0 WAIT @ WAIT pin input mode) T1 CLK (20MHz) CS T2 ADDRESS RD read D7 to 0 WR input write D7 to 0 output WAIT sampling * External Read / Write Bus Cycle (n WAIT @ WAIT pin input mode) T1 CLK (20MHz) CS TW T2 ADDRESS RD read D7 to 0 WR input write D7 to 0 output WAIT sampling sampling 92CD54I-68 2006-01-27 TMP92CD54I * Example of WAIT Input Cycle (5WAIT) FF0 D Q FF1 D Q FF2 D Q FF3 D Q FF4 D Q WAIT CK RES CLK CK RES CK RES CK RES CK RES CS RD WR 1 CLK(20MHz) CS RD 2 3 4 5 6 7 FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q WAIT 92CD54I-69 2006-01-27 TMP92CD54I 3.6.4 List of registers The memory control registers and the settings are described as follows. For the addresses of the registers, see List of Special Function Registers in section 5. (1) Control registers The control register is a pair of BCSL and BCSH. BCSL has the same configuration regardless of the block address areas. Block CS/WAIT control register (Low) 7 6 BWW2 0 5 BWW1 1 4 BWW0 W 0 3 - 2 BWR2 0 1 BWR1 1 0 BWR0 0 BCSL (0148H) bit Symbol Read/Write After Reset - BWW[2:0] Specifies the number of write waits. 001 = 2 states (0 WAIT) access 101 = 4 states (2 WAIT) access 011 = WAIT pin input mode BWR[2:0] 001 = 2 states (0 WAIT) access 101 = 4 states (2 WAIT) access 010 = 3 states (1 WAIT) access 110 = 5 states (3 WAIT) access Others = (Reserved) 010 = 3 states (1 WAIT) access 110 = 5 states (3 WAIT) access Specifies the number of read waits. 011 = WAIT pin input mode Others = (Reserved) Block CS/WAIT control register (High) 7 6 BM 0 5 0(Fix to 0) 4 W 0(Fix to 0) 3 BOM1 0 2 BOM0 0 1 BBUS1 0 0 BBUS0 0 BCSH (0149H) bit Symbol Read/Write After reset BE 1 BE Enable bit 0 = No chip select signal output 1 = Chip select signal output (Default) BM Block address area specification 0 = Sets the block address area of CS to addresses 000000H to FFFFEFH. (Default) 1 = Sets the block address area of CS to programmable. Note: After reset release, the block address area of CS is set to addresses 000000H to FFFFEFH. BOM[1:0] 00 = SRAM or ROM(Default) others = (Reserved) BBUS[1:0] Sets the data bus width 00 = 8-bit (Default) others = (Reserved) 92CD54I-70 2006-01-27 TMP92CD54I (2) Block address register A start address and an address area of the block address are specified by the memory start address register (MSAR) and the memory address mask register (MAMR). The bit to be set by the memory address mask register depends on the block address area. Memory Start Address Register MSAR (014BH) 7 bit Symbol Read/Write After Reset 1 MS23 6 MS22 1 5 MS21 1 4 MS20 R/W 1 3 MS19 1 2 MS18 1 1 MS17 1 0 MS16 1 MS[23:16] Sets a start address. Sets the start address of the block address areas. address A23 to A16. Memory Address Mask Register MAMR (014AH) 7 bit Symbol Read/Write After reset 1 MV22 6 MV21 1 5 MV20 1 4 MV19 R/W 1 3 MV18 1 2 MV17 1 1 MV16 1 0 MV15 1 MV[22:15] Enables or masks com parison of the addresses. 92CD54I-71 2006-01-27 TMP92CD54I 3.7 8-bit Timers TMP92CD54I features eight built-in 8-bit timers (timers 0 to 7). These timers are paired into four modules: timers 01, timers 23, timers 45, and timers 67. Each module consists of two channels and can operate in any of the following four operating modes. * * * * 8-Bit Interval Timer Mode 16-Bit Interval Timer Mode 8-Bit Programmable Square Wave Pulse Generation Output Mode (PPG - variable duty with variable cycle) 8-Bit Pulse Width Modulation Output Mode (PWM - variable duty with constant cycle) Figure 3.7.1 to Figure 3.7.4 show block diagrams for timers 01, timers 23, timers 45 and timers 67. Each channel consists of an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five control SFRs (special-function registers). Each of the four modules (timers 01, timers 23, timers 45 and timers 67) can be operated independently. All modules operate in the same manner; hence only the operation of timers 01 is explained here. Table 3.7.1 Registers and pins for each module Module Specification External pin Input pin for external clock Output pin for timer flip-flop Timer run register Timer register SFR (address) Timer mode register Timer flip-flop control register timers 01 TI0 (shared with PC0) TO1 (shared with PC1) TRUN01 (0080H) TREG0 (0082H) TREG1 (0083H) TMOD01 (0084H) TFFCR1 (0085H) timers 23 TO3 (shared with PC2) TRUN23 (0088H) TREG2 (008AH) TREG3 (008BH) TMOD23 (008CH) TFFCR3 (008DH) timers 45 TI4 (shared with PC3) TO5 (shared with PC4) TRUN45 (0090H) TREG4 (0092H) TREG5 (0093H) TMOD45 (0094H) TFFCR5 (0095H) timers 67 TO7 (shared with PC5) TRUN67 (0098H) TREG6 (009AH) TREG7 (009BH) TMOD67 (009CH) TFFCR7 (009DH) 92CD54I-72 2006-01-27 3.7.1 Prescaler 2 T1 T4 T16 T256 4 8 16 32 64 128 256 512 Run/Clear TRUN01 Block diagrams Prescaler clock: T0 TRUN01 (16bit interval timer mode) Selector TRUN01 Timer Flip-Flop TFF1 Timer flip-flop output: TO1 External input clock: TI0 T1 T4 T16 8-bit up counter (UC0) Over flow 2n Over flow T1 T16 T256 TMOD01 Figure 3.7.1 Timers 01 block diagram TMOD01 92CD54I-73 8-Bit comparator (CP0) TMOD01 Match 8-Bit comparator detect (CP1) 8-Bit Timer Register TREG1 TMOD01 Internal bus Timer 1 Interrupt output: INTT1 TMP92CD54I 2006-01-27 Prescaler 2 T1 T4 T16 T256 4 8 16 32 64 128 256 512 Run/Clear TRUN23 Prescaler clock: T0 TRUN23 (16bit interval timer mode) Selector TRUN23 Timer Flip-Flop TFF3 Timer flip-flop output: TO3 T1 T4 T16 8-bit up counter (UC2) Over flow 2n Over flow T1 T16 T256 8-Bit Up-Counter (UC3) TMOD23 TMOD23 Figure 3.7.2 Timers 23 block diagram TMOD23 92CD54I-74 8-Bit comparator (CP2) TMOD23 Match 8-Bit comparator detect (CP3) 8-Bit Timer Register TREG3 TMOD23 Internal bus Timer 3 Interrupt output: INTT3 TMP92CD54I 2006-01-27 Prescaler 2 T1 T4 T16 T256 4 8 16 32 64 128 256 512 Run/Clear TRUN45 Prescaler clock: T0 TRUN45 (16bit interval timer mode) Selector TRUN45 Timer Flip-Flop TFF5 Timer flip-flop output: TO5 External input clock: TI4 T1 T4 T16 8-bit up counter (UC4) Over flow 2n Over flow T1 T16 T256 TMOD45 Figure 3.7.3 Timers 45 block diagram TMOD45 92CD54I-75 8-Bit comparator (CP4) TMOD45 Match 8-Bit comparator detect (CP5) 8-Bit Timer Register TREG5 TMOD45 Internal bus Timer 5 Interrupt output: INTT5 TMP92CD54I 2006-01-27 Prescaler 2 T1 T4 T16 T256 4 8 16 32 64 128 256 512 Run/Clear TRUN67 Prescaler clock: T0 TRUN67 (16bit interval timer mode) Selector TRUN67 Timer Flip-Flop TFF7 Timer flip-flop output: TO7 T1 T4 T16 8-bit up counter (UC6) Over flow 2n Over flow T1 T16 T256 8-Bit Up-Counter (UC7) TMOD67 TMOD67 Figure 3.7.4 Timers 67 block diagram TMOD67 92CD54I-76 8-Bit comparator (CP6) TMOD67 Match 8-Bit comparator detect (CP7) 8-Bit Timer Register TREG7 TMOD67 Internal bus Timer 1 Interrup7 output: INTT7 TMP92CD54I 2006-01-27 TMP92CD54I 3.7.2 Operation of each circuit (1) Prescalers A 9-bit prescaler generates the input clock to timers 01. The clock T0 is the CPU clock fc divided by 4 and is the input to this prescaler. The prescaler's operation can be controlled using TRUN01 X1 X2 (10MHz) O (10MHz) S C CPU clock fc (20MHz) x4 /2 T0 T1 T2 T4 T8 T16 T32 T256 Interval 400 ns 1.6 s 6.4 s 102.4 s T4 (32/fc) T16 (128/fc) T256 (2048/fc) 0 /4 1 2 3 4 5 6 7 8 9-bit prescaler /2 fIO (internal I/O clock) run/stop & clear TRUN01 . 4/fc T1 T4 Figure 3.7.5 Prescaler 92CD54I-77 2006-01-27 TMP92CD54I (2) Up-counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TMOD01. The input clock for UC0 is selectable and can be either the external clock input via the TI0 pin or one of the three internal clocks T1, T4 or T16. The clock setting is specified by the value set in TMOD01 92CD54I-78 2006-01-27 TMP92CD54I (3) Timer registers (TREG0 and TREG1) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TREG0 or TREG1 matches the value in the corresponding up-counter, the Comparator Match Detect signal goes Active. If the value set in the timer register is 00H, the signal goes Active when the up-counter overflows. The TREG0 are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TRUN01 Up-counter Comparator (CP0) Timer Registers 0 (TREG0) B Selector S Register Buffers 0 Write TRUN01 Shift trigger Internal bus Figure 3.7.6 Configuration of TREG0 Note: The same memory address is allocated to the timer register and the register buffer. When All these registers are write-only and cannot be read. 92CD54I-79 2006-01-27 TMP92CD54I (4) Comparator (CP0) The comparator compares the value in an up-counter with the value set in a timer register. If they match, the up-counter is cleared to zero and an interrupt signal (INTT0 or INTT1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TFF1) The timer flip-flop (TFF1) is a flip-flop inverted by the match detect signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TFFCR1 Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required as explained below. If new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and the up-counter value, the timer flip-flop may output an unexpected value. For this reason, make sure that in PWM mode new data is written to the register buffer by six cycles (fc x 6) before the next overflow occurs by using an overflow interrupt. In the case of using PPG mode, make sure that new data is written to the register buffer by six cycles before the next cycle compare match occurs by using a cycle compare match interrupt. Example when using PWM mode: TREG0 and UC0 match 2 overflow interrupt n TO1 tPWM (PWM cycle) Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt 92CD54I-80 2006-01-27 TMP92CD54I 3.7.3 SFRs Timers 01 Run Register 7 TRUN01 (0080H) Bit symbol Read/Write After Reset T0RDE R/W 0 Double buffer 0: Disable 1: Enable 6 - 5 - 4 - 3 I2T01 0 2 T01PRUN 1 T1RUN 0 R/W 0 T0RUN 0 0 Function IDLE2 Timer Run/Stop control 0: Stop 0: Stop & Clear 1: Operate 1: Run (count up) TREG0 double buffer control 0 1 Disable Enable Timer Run/Stop control 0 1 Stop & Clear Run (count up) I2T01: Operation in IDLE2 Mode T01PRUN: Run prescaler T1RUN: Run Timer 1 T0RUN: Run Timer 0 Note1: The values of bits 4 to 6 of TRUN01 are undefined when read. Note2: Needs to set Timers 23 Run Register 7 TRUN23 (0088H) Bit symbol Read/Write After Reset T2RDE R/W 0 Double buffer 0: Disable 1: Enable 6 - 5 - 4 - 3 I2T23 0 IDLE2 0: Stop 1: Rung 2 T23PRUN 1 T3RUN 0 R/W 0 T2RUN 0 0 Function Timer Run/Stop control 0: Stop & Clear 1: Run (count up) TREG2 double buffer control 0 1 Disable Enable Timer Run/Stop control 0 1 Stop & Clear Run (count up) I2T23: Operation in IDLE2 Mode T23PRUN: Run prescaler T3RUN: Run Timer 3 T2RUN: Run Timer 2 Note1: The values of bits 4 to 6 of TRUN23 are undefined when read. Note2: Needs to set 92CD54I-81 2006-01-27 TMP92CD54I Timers 45 Run Register 7 TRUN45 (0090H) Bit symbol Read/Write After Reset T4RDE R/W 0 Double buffer 0: Disable 1: Enable 6 - 5 - 4 - 3 I2T45 0 2 T45PRUN 1 T5RUN 0 R/W 0 T4RUN 0 0 Function IDLE2 Timer Run/Stop control 0: Stop 0: Stop & Clear 1: Operate 1: Run (count up) TREG4 double buffer control 0 1 Disable Enable Timer Run/Stop control 0 1 Stop & Clear Run (count up) I2T45: Operation during IDLE2-Mode T45PRUN: Run for prescaler T5RUN: Run Timer 5 T4RUN: Run Timer 4 Note1: The values of bits 4 to 6 of TRUN45 are undefined when read. Note2: Needs to set Timers 67 Run Register 7 TRUN67 (0098H) Bit symbol Read/Write After Reset T6RDE R/W 0 Double buffer 0: Disable 1: Enable 6 - 5 - 4 - 3 I2T67 0 2 T67PRUN 1 T7RUN 0 R/W 0 T6RUN 0 0 Function IDLE2 Timer Run/Stop control 0: Stop 0: Stop & Clear 1: Operate 1: Run (count up) TREG6 double buffer control 0 1 Disable Enalbe Timer Run/Stop control 0 1 Stop & Clear Run (count up) I2T67: Operation during IDLE2 Mode T67PRUN: Run prescaler T7RUN: Run Timer 7 T6RUN: Run Timer 6 Note1: The values of bits 4 to 6 of TRUN67 are undefined when read. Note2: Needs to set Figure 3.7.8 Register for 8-bit Timers 92CD54I-82 2006-01-27 TMP92CD54I Timers 01 Mode Register 7 TMOD01 (0084H) Bit symbol Read/Write After Reset 0 T01M1 6 T01M0 0 5 PWM01 0 PWM cycle 00: reserved 01: 26 10: 27 11: 28 4 PWM00 0 R/W 3 T1CLK1 0 00: T0TRG 01: T1 10: T16 11: T256 2 T1CLK0 0 1 T0CLK1 0 0 T0CLK0 0 Function Operation mode 00: 8-Bit Timer Mode 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode Source clock for Timer 1 Source clock for Timer 0 00: TI0 pin (Note) 01: T1 10: T4 11: T16 Timer 0 source clock selection 00 01 10 11 TI0 (external input) T1 (prescaler) T4 (prescaler) T16 (prescaler) Timer 1 source clock selection TMOD01 00 01 10 11 Comparator output from Timer 0 Overflow output from Timer 0 T1 T16 T256 (16-Bit Timer Mode) PWM cycle selection 00 01 10 11 reserved 26 x clock source 27 x clock source 28 x clock source Timers 01 operation mode selection 00 01 10 11 Note : When setting the TI0 pin, first set the Port C setting, then TMOD01. Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (Timer 0) + 8-bit timer (Timer 1) Figure 3.7.9 Register for 8-bit Timers 92CD54I-83 2006-01-27 TMP92CD54I Timers 23 Mode Register 7 TMOD23 (008CH) Bit Symbol Read/Write After Reset 0 T23M1 6 T23M0 0 5 PWM21 0 PWM cycle 00: reserved 01: 26 10: 27 11: 28 4 PWM20 0 R/W 3 T3CLK1 0 00: T2TRG 01: T1 10: T16 11: T256 2 T3CLK0 0 1 T2CLK1 0 00: reserved 01: T1 10: T4 11: T16 0 T2CLK0 0 Function Operation mode 00: 8-Bit Timer Mode 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode Source clock for Timer 3 Source clock for Timer 2 Timer 2 source clock selection 00 01 10 11 Do not set T1 (prescaler) T4 (prescaler) T16 (prescaler) Timer 3 source clock selection TMOD23 00 01 10 11 Comparator output from Timer 2 T1 T16 T256 Overflow output from Timer 2 (16-Bit Timer Mode) PWM cycle selection 00 01 10 11 reserved 26 x clock source 27 x clock source 28 x clock source Timers 23 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (Timer 2) + 8-bit timer (Timer 3) Figure 3.7.10 Register for 8-bit Timers 92CD54I-84 2006-01-27 TMP92CD54I Timers 45 Mode Register 7 TMOD45 (0094H) Bit symbol Read/Write After Reset 0 T45M1 6 T45M0 0 5 PWM41 0 PWM cycle 00: reserved 01: 26 10: 27 11: 28 4 PWM40 0 R/W 3 T5CLK1 0 00: T4TRG 01: T1 10: T16 11: T256 2 T5CLK0 0 1 T4CLK1 0 0 T4CLK0 0 Function Operation mode 00: 8-Bit Timer Mode 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode Source clock for Timer 5 Source clock for Timer 4 00: TI4 pin (Note) 01: T1 10: T4 11: T16 Source clock for Timer 4 00 01 10 11 TI4 (external input) T1 (prescaler) T4 (prescaler) T16 (prescaler) Source clock for Timer 5 TMOD45 00 01 10 11 Comparator output from Timer 4 T1 T16 T256 Overflow output from Timer 4 (16-Bit Timer Mode) PWM cycle 00 01 10 11 reserved 26 x clock source 27 x clock source 28 x clock source Operation mode for Timers 45 00 01 10 11 Note : When setting the TI4 pin, first set the Port C setting, then TMOD45. Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (Timer 4) + 8-bit timer (Timer 5) Figure 3.7.11 Register for 8-bit Timers 92CD54I-85 2006-01-27 TMP92CD54I Timers 67 Mode register 7 TMOD67 (009CH) Bit symbol Read/Write After Reset 0 T67M1 6 T67M0 0 5 PWM61 0 PWM cycle 00: reserved 01: 26 10: 27 11: 28 4 PWM60 0 R/W 3 T7CLK1 0 00: T6TRG 01: T1 10: T16 11: T256 2 T7CLK0 0 1 T6CLK1 0 00: reserved 01: T1 10: T4 11: T16 0 T6CLK0 0 Function Operation mode 00: 8-Bit Timer Mode 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode Source clock for Timer 7 Source clock for Timer6 Source clock for Timer 6 00 01 10 11 Do not set T1 (prescaler) T4 (prescaler) T16 (prescaler) Source clock for Timer 7 TMOD67 00 01 10 11 Comparator output from Timer 6 T1 T16 T256 Overflow output from Timer 6 (16-Bit Timer Mode PWM cycle 00 01 10 11 reserved 26 x clock source 27 x clock source 28 x clock source Operation mode for Timers 67 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (Timer 6) + 8-bit timer (Timer 7) Figure 3.7.12 Register for 8-bit Timers 92CD54I-86 2006-01-27 TMP92CD54I Timer 1 Flip-Flop Control Register 7 TFFCR1 (0085H) Bit symbol Read/Write After Reset - 6 - 5 - 4 - 3 TFF1C1 1 00: Invert TFF1 01: Set TFF1 2 TFF1C0 R/W 1 1 TFF1IE 0 TFF1 0 TFF1IS 0 Read-Modify -Write instructions are prohibited. TFF1 Control for Inversion inversion 0: Disable 1: Enable select 0: Timer 0 1: Timer 1 Function 10: Clear TFF1 11: Don't care Inverse signal for Timer Flop-Flop 1 (TFF1) (Don't care except in 8-Bit Timer Mode) 0 1 Inversion by Timer 0 Inversion by Timer 1 Inversion of TFF1 0 1 Disabled Enabled Control of TFF1 00 Inverts the value of TFF1 01 10 Note: The values of bits 4 to 7 of TFFCR1 are undefined when read. 11 Sets TFF1 to 1 Clears TFF1 to 0 Don't care Figure 3.7.13 Register for 8-bit Timers 92CD54I-87 2006-01-27 TMP92CD54I Timer 3 Flip-Flop Control Register 7 TFFCR3 (008DH) Bit symbol Read/Write After Reset - 6 - 5 - 4 - 3 TFF3C1 1 00: Invert TFF3 01: Set TFF3 2 TFF3C0 R/W 1 1 TFF3IE 0 0 TFF3IS 0 TFF3 TFF3 Control for Inversion inversion 0: Disable 1: Enable select 0: Timer 2 1: Timer 3 Read-Modify -Write instructions are prohibited. Function 10: Clear TFF3 11: Don't care Inverse signal for Timer Flip-Flop 3 (TFF3) (Don't care except in 8-Bit Timer Mode) 0 1 Inversion by Timer 2 Inversion by Timer 3 Inversion of TFF3 0 1 Disabled Enabled Control of TFF3 00 01 10 Note: The values of bits 4 to 7 of TFFCR3 are undefined when read. 11 Inverts the value of TFF3 Sets TFF3 to 1 Clears TFF3 to 0 Don't care Figure 3.7.14 Register for 8-bit Timers 92CD54I-88 2006-01-27 TMP92CD54I Timer 5 Flip-Flop Control Register 7 TFFCR5 (0095H) Bit symbol Read/Write After Reset - 6 - 5 - 4 - 3 TFF5C1 1 00: Invert TFF5 01: Set TFF5 2 TFF5C0 R/W 1 1 TFF5IE 0 0 TFF5IS 0 TFF5 TFF5 Control for Inversion inversion 0: Disable 1: Enable select 0: Timer 4 1: Timer 5 Read-Modify -Write instructions are prohibited. Function 10: Clear TFF5 11: Don't care Inverse signal for Timer Flip-Flop 5 (TFF5) (Don't care except in 8-Bit Timer Mode) 0 1 Inversion by Timer 4 Inversion by Timer 5 Inversion of TFF5 0 1 Disabled Enabled Control of TFF5 00 01 10 Note: The values of bits 4 to 7 of TFFCR5 are undefined when read. 11 Inverts the value TFF5 Sets TFF5 to 1 Clears TFF5 to 0 Don't care Figure 3.7.15 Register for 8-bit Timers 92CD54I-89 2006-01-27 TMP92CD54I Timer 7 Flip-Flop Control Register 7 TFFCR7 (009DH) Bit symbol Read/Write After Reset - 6 - 5 - 4 - 3 TFF7C1 1 00: Invert TFF7 01: Set TFF7 2 TFF7C0 R/W 1 1 TFF7IE 0 0 TFF7IS 0 TFF7 TFF7 Control for Inversion invertsion 0: Disable 1: Enable select 0: Timer 6 1: Timer 7 Read-Modify -Write instructions are prohibited. Function 10: Clear TFF7 11: Don't care Inverse signal for Timer Flip-Flop 7 (TFF7) (Don't care except in 8-Bit Timer Mode) 0 1 Inversion by Timer 6 Inversion by Timer 7 Inversion of TFF7 0 1 Disabled Enabled Control of TFF7 00 01 10 Note: The values of bits 4 to 7 of TFFCR7 are undefined when read. 11 Inverts the value of TFF7 Sets TFF7 to 1 Clears TFF7 to 0 Don't care Figure 3.7.16 Register for 8-bit Timers 92CD54I-90 2006-01-27 TMP92CD54I Timer Register (TREG 0 to 7) Symbol TREG0 Address 82H (no RMW) 83H (no RMW) 8AH (no RMW) 8BH (no RMW) 92H (no RMW) 93H (no RMW) 9AH (no RMW) 9BH (no RMW) 7 6 5 4 3 2 1 0 TREG1 TREG2 TREG3 TREG4 TREG5 TREG6 TREG7 W Undefined W Undefined W Undefined W Undefined W Undefined W Undefined W Undefined W Undefined TREG is for the comparator (When UC matches TREG, occur match detect signal). Refer to setting example in Section 3.7.4, Operation in each mode. Figure 3.7.17 Register for 8-bit Timers 92CD54I-91 2006-01-27 TMP92CD54I 3.7.4 Operation in each mode (1) 8-Bit interval Timer Mode Both timer 0 and timer 1 can be used independently as 8-bit interval timers. Generating interrupts at a fixed interval (using timer 1) To generate interrupts at constant intervals using timer 1 (INTT1), first stop timer 1 then set the operation mode, input clock and a cycle to TMOD01 and TREG1 register, respectively. Then, enable the interrupt INTT1 and start timer 1 counting. Example: To generate an INTT1 interrupt every 40 seconds at fc = 20 MHz, set each register as follows: MSB 7 - 0 LSB 0 - - TRUN01 TMOD01 TREG1 INTET01 TRUN01 6 X 0 5 X X 4 X X 3 - 0 2 - 1 1 0 - 0 X - 1 1 X 1 0 X 0 1 X 0 - - 1 - 1 0 - 1 0 - - Stop timer 1 and clear it to 0. Select 8-Bit Interval Timer Mode and select T1 (0.4 s at fc = 20 MHz) as the input clock. Set TREG1 to 40 s / T1 = 100 = 64H Set INTT1 interrupt level to 5. Start timer 1 counting. Note: X = Don't care; "-" = No change TREG1 = 64H = 40 s / T1 UC1 & TREG1 Match detect INTT1 interrupt request occur Select the input clock using Table 3.7.2. Table 3.7.2 Selecting Interrupt Interval and the Input Clock Using 8-Bit Timer Input Clock T1 (8/fc) T4 (32/fc) T16 (128/fc) T256 (2048/fc) Interrupt Interval (at fc = 20 MHz) 0.4 s to 102.4 s 1.6 s to 409.6 s 6.4 s to 1.639 ms 102.4 s to 26.22 ms Resolution 0.4 s 1.6 s 6.4 s 102.4 s Note: The input clocks for timer 0 and timer 1 differ as follows: timer 0: Uses timer 0 input (TI0) and can be selected from T1, T4 or T16 timer 1: Match output of timer 0 (T0TRG) and can be selected from T1, T16, T256 92CD54I-92 2006-01-27 TMP92CD54I Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TFF1) is inverted at constant intervals and its status output via the timer output pin (TO1). Example: To output a 2.4-s square wave pulse from the TO1 pin at fc = 20 MHz, use the following procedure to make the appropriate register settings. This example uses timer 1; however, either timer 0 or timer 1 may be used. 7 - 0 6 X 0 5 X X 4 X X 3 - 0 2 - 1 1 0 - 0 - - TRUN01 TMOD01 TREG1 TFFCR1 PCCR PCFC TRUN01 Stop timer 1 and clear it to 0. Select 8-Bit Interval Timer Mode and select T1 (0.4 s at fc = 20 MHz) as the input clock. Set the timer register to 2.4 s / T1 / 2 = 3 Clear TFF1 to 0 and set it to invert on the match detect signal from timer 1. Set PC1 to function as the TO1 pin. Start timer 1 counting. 0 X X X - 0 X X X X 0 X - - X 0 X - - X 0 1 - - 0 0 - - 1 1 1 1 1 1 1 1 - - Note: X = Don't care; "-" = No change T1 TRUN01 0 1 2 3 0 1 2 3 0 1 2 3 0 TFF1 TO1 0.77 s at @fc = 20 Figure 3.7.18 Square wave output timing chart (50% Duty) 92CD54I-93 2006-01-27 TMP92CD54I Making timer 1 count up on the match signal from the timer 0 comparator Select 8-Bit Interval Timer Mode and set the comparator output from timer 0 to be the input clock to timer 1. Comparator output (timer 0 match) timer 0 up-counter (when TREG0 = 5) timer 1 up-counter (when TREG1 = 2) timer 1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.7.19 Timer 1 Count Up on Signal from Timer 0 (2) 16-Bit interval Timer Mode A 16-bit interval timer is configured by pairing the two 8-bit timers timer 0 and timer 1. To make a 16-bit interval timer in which timer 0 and timer 1 are cascaded together, set TMOD01 TRUN01 T1 T4 T16 TFFCR1 Clear Overflow 8-bit up-counter (UC0) 8-bit up-counter (UC1) TMOD01 TREG0 INTT1 Register Buffer TREG1 Internal bus Figure 3.7.19 Block diagram of 16-Bit interval timer Mode 92CD54I-94 2006-01-27 TMP92CD54I Setting example: To generate an INTT1 interrupt every 0.4 seconds at fc = 20 MHz, set the timer registers TREG0 and TREG1 as follows: If T16 (6.4 s at 20 MHz) is used as the input clock for counting, set the following value in the registers: 0.4 s / 6.4 s = 62500 = F424H; i.e. set TREG1 to F4H and TREG0 to 24H. The comparator match signal is output from timer 0 each time the up-counter UC0 matches TREG0, where the up-counter UC0 is not cleared. In the case of the timer 1 comparator, the match detect signal is output on each comparator pulse on which the values in the up-counter UC1 and TREG1 match. When the match detect signal is output simultaneously from both the comparators timer 0 and timer 1, the up-counters UC0 and UC1 are cleared to 0 and the interrupt INTT1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TFF1 is inverted. Example: When TREG1 = 04H and TREG0 = 80H Value of up-counter(UC1, UC0): 0000H UC0 & TREG0 match detect signal UC1 & TREG1 match detect signal Interrupt INTT1 Timer output TO1 Inversion 0080H 0180H 0280H 0380H 0480H Figure 3.7.20 Timer output by 16-Bit Interval Timer Mode (3) 8-Bit Programmable Pulse Generation(PPG) Output Mode Square wave pulses can be generated at any frequency and duty ratio by timer 0. The output pulses may be active-Low or active-High. In this mode timer 1 cannot be used. Timer 0 outputs pulses on the TO1 pin (which can also be used as PC1). tH tL t TREG0 and UC0 match (Interrupt INTT0) TREG1 and UC0 match (Interruput INTT1) TO1 Duty cycle TREG0 TREG1 Period Figure 3.7.21 8 bit PPG output waveforms 92CD54I-95 2006-01-27 TMP92CD54I In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up-counter (UC0) matches the value in one of the timer registers TREG0 or TREG1. The value set in TREG0 must be smaller than the value set in TREG1. Although the up-counter for timer 1 (UC1) is not used in this mode, TRUN01 TO1 Selector T1 T4 T16 TRUN01 Inversion TMOD01 Comparator Selector TREG0-WR TREG0 Shift trigger Register Buffer TREG1 TRUN01 Internal bus Figure 3.7.22 Block diagram of 8-Bit PPG Output Mode If the TREG0 double buffer is enabled in this mode, the value of the register buffer will be shifted into TREG0 each time TREG1 matches UC0. Use of the double buffer facilitates the handling of low-duty waves (when duty is varied). Match with TREG0 and up-Counter Match with TREG1 TREG0 (Value to be compared) Register buffer (Up-counter = Q1) (Up-countner = Q2) Shift from register buffer Q2 Q2 Q3 TREG0 (register buffer) write Q1 Figure 3.7.23 Operation of register buffer 92CD54I-96 2006-01-27 TMP92CD54I Example: To generate 1/4-duty 62.5 kHz pulses (at fc = 20 MHz): 16 s Calculate the value which should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 s T1 = 0.4 s (at 20 MHz); 16 s / 0.4 s = 40 Therefore set TREG1 to 40 (28H) The duty is to be set to 1/4: t x 1/4 = 16 s x 1/4 = 4 s 4 s / 0.4 s = 10 Therefore, set TREG0 = 10 = 0AH. 7 0 1 0 0 X 6 X 0 0 0 X 5 X X 0 1 X 4 X X 0 0 X 3 - X 1 1 0 2 0 X 0 0 1 1 0 0 1 0 1 0 0 1 0 0 X TRUN01 TMOD01 TREG0 TREG1 TFFCR1 PCCR PCFC TRUN01 Stop timer 0 and timer 1 and clear it to "0". Set the 8-bit PPG mode, and select T1 as input clock. Write 0AH Write 28H Set TFF1 and enable inversion. 10 generates a negative logic pulse. X X 1 X X X - - X - - X - - - - 1 1 1 1 - 1 Set PC1 as the TO1 pin. Set double buffer enable, and start timer 0 and timer 1 counting. Note: X = Don't care; "-" = No change 92CD54I-97 2006-01-27 TMP92CD54I (4) 8-Bit Pulse with Modulation ( PWM ) Output Mode This mode is only valid for timer 0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When timer 0 is used the PWM pulse is output on the TO1 pin (which is also used as PC1). Timer 1 can also be used as an 8-bit timer. The timer output is inverted when the up-counter (UC0) matches the value set in the timer register TREG0 or when 2n counter overflow occurs (n = 6, 7 or 8 as specified by TMOD01 TREG0 and UC0 match 2n overflow (INTT0 interrupt) TO1 tPWM (PWM cycle) Figure 3.7.24 8-bit PWM waveforms Figure 3.7.25 shows a block diagram representing this mode. TRUN01 T1 T4 T16 TO1 TFFCR1 Selector 8-bit up counter (UC0) Clear 2 n TAFF1 TMOD01 TMOD01 overflow control Comparator Overflow INTT0 TREG0 Selector Shift trigger Register buffer TREG0-WR TRUN01 Figure 3.7.25 Block diagram of 8-Bit PWM Mode 92CD54I-98 2006-01-27 TMP92CD54I In this mode the value of the register buffer will be shifted into TREG0 if 2n overflow is detected when the TREG0 double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TREG0 Up-counter = Q1 2n overflow TREG0 (value to be compared) Register buffer Q1 Q2 Shift into TREG0 Q2 Q3 TREG0 (register buffer) write Up-counter = Q2 Figure 3.7.26 Register buffer operation Example: To output the following PWM waves on the TO1 pin at fc = 20 MHz: 36.0 s 51.2 s To achieve a 51.2-s PWM cycle by setting T1 to 0.4 s (at fc = 20 MHz): 51.2 s / 0.4 s = 128 2n = 128 Therefore n should be set to 7. Since the low-level period is 36.0 s when T1 = 0.4 s, set the following value for TREG0: 36.0 s / 0.4 s = 90 = 5AH MSB 7 - 1 LSB 0 0 1 TRUN01 TMOD01 TREG0 TFFCR1 PCCR PCFC TRUN01 6 X 1 5 X 1 4 X 0 3 - - 2 - - 1 - 0 Stop timer 0 and clear it to 0. Select 8-Bit PWM Mode (cycle: 27) and select T1 as the input clock. Write 5AH. Clear TFF1 to 0, and enable the inversion. 0 X X X 1 1 X X X X 0 X - - X 1 X - - X 1 1 - - 0 0 - - 1 1 1 1 1 - 0 X - 1 Set PC1 and the TO1 pin. Set double buffer enable, and start timer 0 counting. Note: X = Don't care; "-" = No change 92CD54I-99 2006-01-27 TMP92CD54I Table 3.7.3 PWM cycle PWM Interval (at fc = 20MHz) T1 26 27 28 25.6 s ( 39.06 kHz ) 51.3 s ( 19.53 kHz ) 102.4 s ( 9.77 kHz ) T4 102.4 s ( 9.77 kHz ) 204.8 s ( 4.88 kHz ) 409.6 s ( 2.44 kHz ) T16 409.6 s ( 2.44 kHz ) 819.2 s ( 1.22 kHz ) 1.6384 ms ( 0.61 kHz ) (5) Settings for each mode Table 3.7.4 shows the SFR settings for each mode. Table 3.7.4 Interval Timer mode setting registers Register name 8-bit timer x 2 channels 00 - Lower timer match, External clock, T1, T16, T256 T1, T4, T16 (00, 01, 10, 11) (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) External clock, - T1, T16 , T256 (01, 10, 11) T1, T4, T16 (00, 01, 10, 11) - 16-bit interval timer mode 01 - - - 8-bit PPG x 1 channel 10 - - - 8-bit PWM x 1 channel 11 26 , 27 , 28 (01, 10, 11) - - 8-bit timer x 1 channel 11 Output disabled Note:"-" = Don't care 92CD54I-100 2006-01-27 TMP92CD54I 3.8 16-Bit Timer/Event Counters TMP92CD54I incorporates two multifunctional 16-bit timer/event counters (timer 8 and timer A) which have the following operation modes: * 16-Bit Interval Timer Mode * 16-Bit Event Counter Mode * 16-Bit Programmable Pulse Generation (PPG) Mode Can be used following operation modes by capture function: * * * Frequency Measurement Mode Pulse Width Measurement Mode Time Differential Measurement Mode Figure 3.8.1 to Figure 3.8.2 show block diagrams for timer 8 and timer A. Each timer/event counter channel consists of a 16-bit up-counter, two 16-bit timer registers (one of them with a double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, a timer flip-flop and a control circuit. Each timer/event counter is controlled by an 11-byte control SFR. The two channels (timer 8 and timer A) can be used independently. Both channels feature the same operations except for those described in Table 3.8.1. Thus, only the operation of timer 8 is explained below. Table 3.8.1 Differences between Timer 8 and Timer A Channel Specification External Pins External clock / Capture trigger input pins Timer flip-flop output pins Timer Run Register Timer Mode Register Timer Flip-Flop Control Register SFR (address) Timer 8 TI8 (also used as PD0) TI9 (also used as PD1) TO8 (also used as PD2) TO9 (also used as PD3) TRUN8 (00A0H) TMOD8 (00A2H) TFFCR8 (00A3H) TREG8L (00A8H) Timer A TIA (also used as PD4) TIB (also used as PD5) TOA (also used as PD6) TOB (also used as PD7) TRUNA (00B0H) TMODA (00B2H) TFFCRA (00B3H) TREGAL (00B8H) TREGAH (00B9H) TREGBL (00BAH) TREGBH (00BBH) CAPAL (00BCH) CAPAH (00BDH) CAPBL (00BEH) CAPBH (00BFH) Timer Register TREG8H (00A9H) TREG9L (00AAH) TREG9H (00ABH) CAP8L (00ACH) CAP8H (00ADH) CAP9L (00AEH) CAP9H (00AFH) Capture Register 92CD54I-101 2006-01-27 3.8.1 Internal data-bus Internal data bus INT output Register 0 Register 1 INTTR8 INTTR9 Block diagrams Prescaler clock: T0 2 T1 Capture Register 8 CAP8H/L Caputure register 9 CAP9H/L T4 T16 4 8 16 32 Run/ Clear TRUN8 External INT input INT5 INT6 TMOD8 Timer flip-flop TFF8 TFF9 Timer flip-flop output TO8 Timer Flip-Flop control TO9 Over flow INT INTTO8 TFF1 (from timer 01) TI8 TI9 Capture, External INT input control Slelector Count Clock 16-bit up counter (UC8) TMOD8 T1 Figure 3.8.1 Block Diagram of Timer 8 92CD54I-102 16-Bit Comparator (CP8) 16-Bit timer register TREG8H/L TRUN8 Match detection 16-Bit Comparator (CP9) 16-Bit Time Register TREG9H/L Intenal data bus TMP92CD54I 2006-01-27 Internal data bus Internal data bus INT output Register 0 Register 1 INTTRA INTTRB Prescaler clock : T0 2 T1 Capture register A CAPAH/L Caputure Register B CAPBH/L T4 T16 4 8 16 32 External INT input INT7 TMODA Run/ Clear TRUNA Timer flip-flop TFFA TFFB Timer flip-flop output TOA Timer Flip-Flop control TOB Over flow INT INTTOA TFF1 (from timer 01) TIA TIB Capture, External INT input control TMODA TRUNA Figure 3.8.2 Block diagram of Timer A Slelector Count T1 clock T4 T16 92CD54I-103 16-Bit comparator (CPA) 16-Bit Timer Register TREGAH/L TB0RUN Match detection 16-Bit comparator (CPB) 16-Bit Time Register TREGBH/L Intenal data bus TMP92CD54I 2006-01-27 TMP92CD54I 3.8.2 Operation of each block (1) Prescaler The 5-bit prescaler generates the source clock for timer 8. The prescaler clock (T0) is divided clock (divided by 4) from fc. This prescaler can be started or stopped using TRUN8 Table 3.8.2 Prescaler clock resolution At fc=20MHz Output clock Interval T1 ( 8/fc) 0.4 s T4 ( 32/fc) 1.6 s T16 (128/fc) 102.4 s (2) Up-counter (UC8) UC8 is a 16-bit binary counter which counts up pulses input from the clock specified by TMOD8 92CD54I-104 2006-01-27 TMP92CD54I (3) Timer registers (TREG8H/L and TREG9H/L) These two 16-bit registers are used to set the interval time. When the value in the up-counter UC8 matches the value set in this timer register, the Comparator Match Detect signal will go Active. Setting data for timer register TREG8H/L and TREG9H/L is executed using 2 byte data transfer instruction or using 1 byte date transfer instruction twice for lower 8 bits and upper 8 bits in order. The TREG8 timer register has a double-buffer structure, which is paired with register buffer 8. The value set in TRUN8 Timer 8 TREG8 Upper 8 bits 0000A9H Lower 8 bits 0000A8H Upper 8 bits 0000ABH TREG9 Lower 8 bits 0000AAH Timer A TREGA Upper 8 bits 0000B9H Lower 8 bits 0000B8H Upper 8 bits 0000BBH TREGB Lower 8 bits 0000BAH The Timer Registers are write-only registers and thus cannot be read. 92CD54I-105 2006-01-27 TMP92CD54I (4) Capture Registers (CAP8H/L and CAP9H/L) These 16-bit registers are used to latch the values in the up-counter UC8. Data in the Capture Registers should be read using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte. The addresses of the Capture Registers are as follows: Timer 8 CAP8 Upper 8 bits 0000ADH Lower 8 bits 0000ACH Upper 8 bits 0000AFH CAP9 Lower 8 bits 0000AEH Timer A CAPA Upper 8 bits 0000BDH Lower 8 bits 0000BCH Upper 8 bits 0000BFH CAPB Lower 8 bits 0000BEH The Capture Registers are read-only registers and thus cannot be written to. (5) Capture input control and external interrupt control This circuit controls the timing to latch the value of up-counter UC8 into CAP8, CAP8 and the generation of external interrupts. The latch timing for the capture register and selection of edge for external interrupt is determined by TMOD8 92CD54I-106 2006-01-27 TMP92CD54I 3.8.3 SFR Timer 8 Run Register 7 TRUN8 (00A0H) Bit symbol Read/Write After Reset T8RDE R/W 0 Double Buffer 0: Disable 1: Enable 6 R/W 0 Write 0 5 - 4 - 3 I2T8 R/W 0 IDLE2 0: Stop 2 T8PRUN 1 - 0 T8RUN R/W 0 R/W 0 Timer Run/Stop control 0: Stop & Clear Function 1: Operate 1: Run (count up) Count operation 0 1 Stop and Clear Count I2T8: Operation during IDLE2-mode Note: The 1, 4 and 5 of TRUN8 are read as underfined value. T8PRUN: Operation of prescaler T8RUN: Operation of Timer 8 Timer A Run Register 7 TRUNA (00B0H) Bit symbol Read/Write After Reset TARDE R/W 0 Double Buffer 0: Disable 1: Enable 6 R/W 0 Write 0 5 - 4 - 3 I2TA R/W 0 IDLE2 0: Stop 2 TAPRUN 1 - 0 TARUN R/W 0 R/W 0 Function 16 Bit Timer Run/Stop control 0: Stop & Clear 1: Operate 1: Run (count up) Count Operation 0 1 Stop and Clear Count I2TA: Operation during IDLE2-mode Note: The 1, 4 and 5 of TRUNA are read as underfined value. TAPRUN: Operation of prescaler TARUN: Operation of Timer A Figure 3.8.3 Registers for 16-bit Timers 92CD54I-107 2006-01-27 TMP92CD54I Timer 8 Mode Register 7 TMOD8 (00A2H) Bit symbol Read/Write After Reset Function 0 TFF9 inversion 0: Disable trigger 1: Enable trigger Invert when the UC value is captured to CAP9. 6 EQ9T9 0 R/W 5 CAP8IN W 1 Execute software capture 0: Execute 1: Don't care 4 3 2 T8CLE R/W 0 Control up-counter 0: Disable clearing 1: Enable clearing 1 T8CLK1 0 00: TI8 pin 01: T1 10: T4 11: T16 0 T8CLK0 0 CAP9T9 CAP89M1 CAP89M0 0 0 Invert when the UC value matches the value in TREG9. Note) Always read as 1. Capture timing 00: Disable INT5 occurs on rising edge. 01: TI8 TI9 INT5 occurs on rising edge. 10: TI8 TI8 INT5 occurs on falling edge. 11: TFF1 TFF1 INT5 occurs on rising edge. Timer 8 source clock Timer 8 source clock 00 01 10 11 TI8 pin T1 T4 T16 Up-counter (UC8) clear control 0 1 Disable Enable clearing by match with TREG9. Capture/Interrupt timing Capture control 00 01 10 11 Disable CAP8 at TI8 rise CAP9 at TI9 rise CAP8 at TI8 rise CAP9 at TI8 fall CAP8 at TFF1 rise CAP9 at TFF1 fall of TI8. INT5 occurs on falling edge of TI8. INT5 occurs on rising edge of TI8. INT5 control INT5 occurs on rising edge Software capture 0 1 The value in the up-counter is captured to CAP8. Don't care Figure 3.8.4 Registers for 16-bit Timers 92CD54I-108 2006-01-27 TMP92CD54I Timer A Mode Register 7 TMODA (00B2H) Bit symbol Read/Write After Reset 0 TFFB inversion 0: Disable trigger 1: Enable trigger Invert when the UC value 6 EQBTB 0 R/W 5 CAPAIN W 1 Execute software capture 0: Execute 1: Don't care 4 3 2 TACLE R/W 0 Control up-counter 0: Disable clearing 1: Enable clearing 1 TACLK1 0 00: TIA pin 01: T1 10: T4 11: T16 0 TACLK0 0 CAPBTB CAPABM1 CAPABM0 0 0 Invert when the UC value matches the value in TREGB. Function is captured to CAPB. Note) Always read as 1. Capture timing 00: Disable INT7 occurs on rising edge. 01: TIA TIB INT7 occurs on rising edge. 10: TIA TIA INT7 occurs on falling edge. 11: TFF1 TFF1 INT7 occurs on rising edge. Timer A source clock Timer A source clock 00 01 10 11 TIA pin T1 T4 T16 Up-counter clear control 0 1 Disable Enable clearing on match with TREGB. Capture/Interrupt timing Capture control 00 01 10 11 Disable CAPA at TIA rise CAPB at TIB rise CAPA at TIA rise CAPB at TIA fall CAPA at TFF1 rise CAPB at TFF1 fall of TIA. INT7 occurs on falling edge of TIA. INT7 occurs on rising edge of TIA. INT7 control INT7 occurs on rising edge Software capture 0 1 The value in the up-counter is captured to CAPA. Don't care Figure 3.8.5 Registers for 16-bit Timers 92CD54I-109 2006-01-27 TMP92CD54I Timer 8 Flip-Flop Control Register 7 TFFCR8 (00A3H) Bit symbol Read/Write After Reset 1 TFF9C1 6 TFF9C0 5 CAP9T8 4 CAP8T8 3 EQ9T8 2 EQ8T8 1 TFF8C1 0 TFF8C0 W 1 0 0 Control TFF9 00: Invert 01: Set 10: Clear 11: Don't care Note)Always read as 11 TFF8 inversion trigger 0: Disable trigger 1: Enable trigger R/W 0 0 1 W 1 Function Control TFF8 00: Invert 01: Set 10: Clear 11: Don't care Invert when Invert when Invert when Invert when the UC value the UC value the UC value the UC value Note)Always read as 11 is loaded in to CAP9. is loaded in to CAP8. matches the matches the value in value in TREG9. TREG8. TFF8 control 00 Invert 01 10 11 Set to 1 Clear to 0 Don't care TFF8 Inverted when the UC value is matched to TREG8. 0 Disable trigger 1 Enable trigger TFF8 Inverted when the UC value is matched to TREG9. 0 1 Disable trigger Enable trigger TFF8 Inverted when the UC value is loaded to CAP8. 0 1 Disable trigger Enable trigger TFF8 Inverted when the UC value is loaded to CAP9. 0 1 Disable trigger Enable trigger TFF9 control 00 01 10 11 Invert Set to 1 Clear to 0 Don't care Figure 3.8.6 Registers for 16-bit Timers 92CD54I-110 2006-01-27 TMP92CD54I Timer A Flip-Flop Control Register 7 TFFCRA (00B3H) Bit symbol Read/Write After Reset 1 TFFBC1 6 TFFBC0 5 CAPBTA 4 CAPATA 3 EQBTA 2 EQATA 1 TFFAC1 0 TFFAC0 W 1 0 0 Control TFFB 00: Invert 01: Set 10: Clear 11: Don't care Note)Always read as 11 TFFA inversion trigger 0: Disable trigger 1: Enable trigger R/W 0 0 1 W 1 Function Control TFFA 00: Invert 01: Set 10: Clear 11: Don't care Invert when Invert when Invert when Invert when the UC value the UC value the UC value the UC value Note)Always read as 11 is loaded in to CAPB. is loaded in to CAPA. matches the matches the value in value in TREGB. TREGA. TFFA control 00 Invert 01 10 11 Set to 1 Clear to 0 Don't care TFFA Inverted when the UC value matches to TREGA. 0 Disable trigger 1 Enable trigger TFFA Inverted when the UC value matches to TREGB. 0 1 Disable trigger Enable trigger TFFA Inverted when the UC value is loaded to CAPA. 0 1 Disable trigger Enable trigger TFFA Inverted when the UC value is loaded to CAPB. 0 1 Disable trigger Enable trigger TFFB control 00 01 10 11 Invert Set to 1 Clear to 0 Don't care Figure 3.8.7 Registers for 16-bit Timers 92CD54I-111 2006-01-27 TMP92CD54I Timer Register (Timer8, TimerA) Symbol TREG8L Address A8H (no RMW) A9H (no RMW) AAH (no RMW) ABH (no RMW) B8H (no RMW) B9H (no RMW) BAH (no RMW) BBH (no RMW) 7 6 5 4 W Undefined W Undefined W Undefined W Undefined W Undefined W Undefined W Undefined W Undefined TREG8H 3 2 1 0 TREG9L TREG9H TREGAL TREGAH TREGBL TREGBH Capture Register (Timer8, TimerA Symbol CAP8L Address ACH 7 6 5 4 R Undefined CAP8H ADH R Undefined CAP9L AEH R Undefined CAP9H AFH R Undefined CAPAL BCH R Undefined CAPAH BDH R Undefined CAPBL BEH R Undefined CAPBH BFH R Undefined 3 2 1 0 Figure 3.8.8 Registers for 16-bit Timers. 92CD54I-112 2006-01-27 TMP92CD54I 3.8.4 Operation in each mode (1) 16-Bit Interval Timer Mode Generating interrupts at fixed intervals In this example, the interrupt INTTR9 is set to be generated at fixed intervals. The interval time is set in the timer register TREG9. TRUN8 INTET89 TFFCR8 TMOD8 TREG9 TRUN8 7 0 X 1 0 6 0 1 1 0 54 XX 00 00 10 (** = ** ** XX 3210 -0X0 X000 0011 01** 01, 10, 11) **** **** -1X1 Stop timer 8. Set INTTR9 Interrupt Level to 4. Disable INTTR8. Disable the trigger. Select internal clock for input and disable the capture function. Set the interval time (16 bits). Start timer 8. * * 0 * * 0 Note: X = Don't care; "-" = No change (2) 16-Bit Event Counter Mode As described above, in 16-Bit Timer Mode, if the external clock (TI8 pin input) is selected as the input clock, the timer can be used as an event counter. The counter counts at the rising edge of TI8 pin input. To read the value of the counter, first perform "software capture" once, then read the captured value. TRUN8 PDCR PDFC INTET89 TFFCR8 TMOD8 TREG9 TRUN8 7 0 - X 1 0 * * 0 6 0 - 1 1 0 * * 0 5 X - 0 0 1 * * X 4 X - 0 0 0 * * X 3 - - X 0 0 * * - 2 0 - 0 0 1 * * 1 1 X - 0 1 0 * * X 0 0 1 1 0 1 0 * * 1 Stop timer 8. Set PD0 to TI8. Set INTTR9 Interrupt Level to 4. Disable INTTR8. Disable the trigger. Select TI8 as the input clock. Set the number of counts (16 bits). Start timer 8. Note: X = Don't care; "-" = No change When the timer is used as an event counter, set the prescaler in Run Mode (i.e. with TRUN8 |