 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91FY42FG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. TMP91FY42 CMOS 16-Bit Microcontrollers TMP91FY42FG 1. Outline and Features TMP91FY42F is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91FY42FG comes in a 100-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) * * * * * Instruction mnemonics are upward-compatible with TLCS-90/900 General-purpose registers and register banks 16 Mbytes of linear address space 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: 4-channels (593 ns/2 bytes at 27 MHz) (2) Minimum instruction execution time: 148 ns (at 27 MHz) RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 021023_D 060925EBP * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S This product uses the Super Flash(R) technology under the license of Silicon Storage Technology,Inc. Super Flash(R) is a registered trademark of Silicon Storage Technology,Inc. 91FY42-1 2006-11-08 TMP91FY42 (3) Built-in RAM: 16 Kbytes Built-in ROM: 256 Kbytes Flash memory 4 Kbytes mask ROM (used for booting) (4) External memory expansion * * Expandable up to 16 Mbytes (shared program/data area) Can simultaneously support 8-/16-bit width external data bus ... Dynamic data bus sizing (5) 8-bit timers: 8 channels (6) 16-bit timer/event counter: 2 channels (7) General-purpose serial interface: 2 channels * * * UART/ Synchronous mode: 2 channels IrDA ver1.0 (115.2 kbps) supported: 1 channel I2C bus mode/clock synchronous Select mode (8) Serial bus interface: 1 channel (9) 10-bit AD converter (built-in sample hold circuit) : 8 channels (10) Watchdog timer (11) Special timer for clock (12) Chip Select/Wait controller: 4 channels (13) Interrupts: 45 interrupts * * * 9 CPU interrupts: Software interrupt instruction and illegal instruction 26 internal interrupts: 10 external interrupts: Seven selectable priority levels (14) Input/Output ports: 81 pins (15) Standby function Three HALT modes: IDLE2 (programmable), IDLE1, STOP (16) Clock controller * * * * * Clock Gear function: Select a high-frequency clock (fc to fc/16) Special timer for CLOCK (fs = 32.768 kHz) VCC = 2.7 V to 3.6 V (fc max = 27 MHz, flash memory read operation) VCC = 3.0 V to 3.6 V (fc max = 27 MHz, flash memory erase/program operations) 100-pin LQFP: LQFP100-P-1414-0.50F (17) Operating voltage (18) Package Note: This LSI does not build in Clock doubler (DFM.) 91FY42-2 2006-11-08 TMP91FY42 ADTRG (P53) AN0 to AN7 (P50 to P57) CPU (TLCS-900/L1) AVCC, AVSS VREFH, VREFL TXD0 (P90) RXD0 (P91) SCLK0/ CTS0 (P92) TXD1 (P93) RXD1 (P94) SCLK1/ CTS1 (P95) SCK (P60) SO/SDA (P61) SI / SCL (P62) 10-Bit 8CH AD Converter SIO/UART/IrDA XWA XBC XDE XHL XIX XIY XIZ XSP (SIO0) SIO/UART (SIO1) Serial Bus Interface (SBI) 8-Bit Timer (TMRA0) 8-Bit Timer (TMRA1) WA BC DE HL IX IY IZ SP 32 bits SR F PC H-OSC Clock Gear Clock doubler L-OSC DVCC [3] DVSS [3] X1 X2 EMU0 EMU1 XT1 (P96) XT2 (P97) RESET AM0 AM1 ALE Port 0 Port 1 (P00 to P07) AD0 to AD7 (P10 to P17) AD8/A8 to AD15/A15 (P20 to P27) A0/A16 to A7/A23 RD (P30) WR (P31) HWR (P32) BUSRQ (P34) BUSAK (P35) R/ W (P36) BOOT (P37) SCOUT(P64), P65, P66 PA4 to PA7 (P40 to P43) CS0 to CS3 WAIT (P33) Watchdog Timer (WDT) Port 2 TA0IN (P70) TA1OUT (P71) Special timer for CLOCK Port 3 16-KB RAM 8-Bit Timer (TMRA2) TA3OUT (P72) 8-Bit Timer (TMRA3) 8-Bit Timer (TMRA4) 8-Bit Timer (TMRA5) 8-Bit Timer (TMRA6) TA7OUT (P75) 8-Bit Timer (TMRA7) 4-KB BOOT ROM 256-KB FLASH E2PROM Port 6 Port A CS/WAIT Controller (4-BLOCK) Interrupt Controller TA4IN (P73) TA5OUT (P74) 16-Bit Timer (TMRB0) 16-Bit Timer (TMRB1) NMI INT0 (P64) INT1 to INT4 (PA0 to PA3) TB0IN0/INT5 (P80) TB0IN1/INT6 (P81) TB0OUT0 (P82) TB0OUT1 (P83) TB1IN0/INT7 (P84) TB1IN1/INT8 (P85) TB1OUT0 (P86) TB1OUT1 (P87) ( ): Initial function after reset Figure 1.1 TMP91FY42F Block Diagram 91FY42-3 2006-11-08 TMP91FY42 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91FY42, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91FY42. 88 P65 DVCC P66 DVSS P50/AN0 P51/AN1 P52/AN2 89 90 91 92 93 94 87 P64/SCOUT 86 P63/INT0 85 P62/SI/SCL 84 P61/SO/SDA 83 P60/SCK 82 P43/CS3 81 P42/CS2 80 P41/CS1 79 P40/CS0 78 P37/BOOT 77 P36/R/W 76 P35/BUSAK 75 P34/BUSRQ 74 P33/WAIT 73 P32/HWR 72 P31/WR 71 P30/RD 70 P27/A7/A23 69 P26/A6/A22 68 P25/A5/A21 67 P24/A4/A20 66 P23/A3/A19 65 P22/A2/A18 P53/AN3/ADTRG 95 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC P70/TA0IN P71/TA1OUT P72/TA3OUT P73/TA4IN P74/TA5OUT P75/TA7OUT 96 97 98 99 100 1 2 3 4 5 6 7 8 9 P80/TB0IN0/INT5 10 P81/TB0IN1/INT6 11 P82/TB0OUT0 P83/TB0OUT1 12 13 Top view QFP100 64 DVCC 63 NMI 62 DVSS 61 P21/A1/A17 60 P20/A0/A16 59 P17/AD15/A15 58 P16/AD14/A14 57 P15/AD13/A13 56 P14/AD12/A12 55 P13/AD11/A11 54 P12/AD10/A10 53 P11/AD9/A9 52 P10/AD8/A8 51 P07/AD7 50 P06/AD6 49 P05/AD5 48 P04/AD4 47 P03/AD3 46 P02/AD2 45 P01/AD1 44 P00/AD0 43 ALE 42 PA7 41 PA6 40 PA5 39 PA4 38 PA3/INT4 P84/TB1IN0/INT7 14 P85/TB1IN1/INT8 15 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0 P91/RXD0 P93/TXD1 P94/RXD1 16 17 18 19 21 22 P92/SCLK0/CTS0 20 P95/SCLK1/CTS1 23 AM0 DVCC X2 DVSS X1 AM1 RESET P96/XT1 P97/XT2 EMU0 EMU1 PA0/INT1 PA1/INT2 PA2/INT3 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Figure 2.1.1 Pin assignment diagram (100-pin LQFP) 91FY42-4 2006-11-08 TMP91FY42 2.2 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions. Table 2.2.1 Pin names and functions (1/3) Pin Name P00P07 AD0AD7 P10P17 AD8AD15 A8A15 P20P27 A0A7 A16A23 P30 Number of Pins 8 8 I/O I/O I/O I/O I/O Output Functions Port 0: I/O port that allows I/O to be selected at the bit level Address and data (lower): Bits 0 to 7 of address and data bus Port 1: I/O port that allows I/O to be selected at the bit level Address and data (upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 of address bus Port 2: I/O port that allows I/O to be selected at the bit level Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus Port 30: Output port Read: Strobe signal for reading external memory This port output RD signal also case of reading internal-area by setting P3 8 I/O Output Output 1 Output Output RD P31 1 1 1 Output Output I/O Output I/O Input Port 31: Output port Write: Strobe signal for writing data to pins AD0 to AD7 Port 32: I/O port (with pull-up resistor) High Write: Strobe signal for writing data to pins AD8 to AD15 Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait ((1+N) WAIT mode) Port 34: I/O port (with pull-up resistor) Bus Request: Signal used to request Bus Release Port 35: I/O port (with pull-up resistor) Bus Acknowledge: Signal used to acknowledge Bus Release WR P32 HWR P33 WAIT P34 BUSRQ 1 1 I/O Input I/O Output P35 BUSAK P36 1 1 R/W P37 BOOT P40 I/O Output I/O Input I/O Output I/O Output I/O Output I/O Output Input Input Input Port 36: I/O port (with pull-up resistor) Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle. Port 36: I/O port (with pull-up resistor) This pin sets single boot mode. When released reset, Single boot mode is started at P37Low level. Port 40: I/O port (with pull-up resistor) Chip Select 0: Outputs 0 when address is within specified address area Port 41: I/O port (with pull-up resistor) Chip Select 1: Outputs 0 if address is within specified address area Port 42: I/O port (with pull-up resistor) Chip Select 2: Outputs 0 if address is within specified address area Port 43: I/O port (with pull-up resistor) Chip Select 3: Outputs 0 if address is within specified address area Port 5: Pin used to input port Analog input: Pin used to input to AD converter AD Trigger: Signal used to request start of AD converter (Shared with53 pin) 1 1 1 1 8 CS0 P41 CS1 P42 CS2 P43 CS3 P50P57 AN0AN7 ADTRG 91FY42-5 2006-11-08 TMP91FY42 Table 2.2.1 Pin names and functions (2/3) Pin Name P60 SCK P61 SO SDA P62 SI SCL P63 INT0 P64 SCOUT P65 P66 P70 TA0IN P71 TA1OUT P72 TA3OUT P73 TA4IN P74 TA5OUT P75 TA7OUT P80 TB0IN0 INT5 P81 TB0IN1 INT6 P82 TB0OUT0 P83 TB0OUT1 P84 TB1IN0 INT7 P85 TB1IN1 INT8 P86 TB1OUT0 P87 TB1OUT1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Number of Pins 1 I/O I/O I/O I/O Output I/O I/O Input I/O I/O Input I/O Output I/O I/O I/O Input I/O Output I/O Output I/O Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Output Port 60: I/O port Functions Serial bus interface clock in SIO Mode Port 61: I/O port Serial bus interface send data at SIO mode Serial bus interface send/recive data at I C bus mode Open-drain output mode by programmable Port 62: I/O port Serial bus interface recive data at SIO mode Serial bus interface clock I/O data at I C bus mode Open-drain output mode by programmable Port 63: I/O port Interrupt Request Pin 0: Interrupt request pin with programmable level / rising edge / falling edge Port 64: I/O port System Clock Output: Outputs fFPH or fs clock. Port 65 I/O port Port 66 I/O port Port 70I/O port 8bitt timer 0 input:: Timer 0 input Port 71I/O port 8-bit timer 1 output: Timer 0 or Timer 1 output Port 72I/O port 8bit 8-bit timer 3 output: Timer 2 or Timer 3 output Port 73: I/O port 8-bit timer 4 input: Timer 4 input Port 74: I/O port 8-bit timer 5 output: Timer 4 or Timer 5 output Port 75: I/O port 88-bit timer 7 output: Timer 6 or Timer 7 output Port 80: I/O port 16bit timer 0 input 0: 16bit Timer 0 count / capture trigger input Interrupt Request Pin 5: Interrupt request pin with programmable rising edge / falling edge. Port 81: I/O port 16bit timer 0 input 1: 16bit Timer 0 count / capture trigger input Interrupt Request Pin 6: Interrupt request on rising edge Port 82: I/O port 16bit timer 0 output 0: 16bit Timer 0 output Port 83: I/O port 16bit timer 0 output 1: 16bit Timer 0 output Port 84: I/O port 16bit timer 1 input 0: 16bit Timer 1 count / capture trigger input Interrupt Request Pin 7: Interrupt request pin with programmable rising edge / falling edge. Port 85: I/O port 16bit timer 1 input 1: 16bit Timer 1 count / capture trigger input Interrupt Request Pin 8: Interrupt request on rising edge Port 86: I/O port 16bit timer 1 output 0: 16bit Timer 1 output 16bit Port 87: I/O port 16bit timer 1 output 1: 16bit Timer 1 output 16bit 16bit 2 2 91FY42-6 2006-11-08 TMP91FY42 Table 2.2.1 Pin names and functions (3/3) Pin Name P90 TXD0 P91 RXD0 P92 SCLK0 CTS0 P93 TXD1 P94 RXD1 P95 SCLK1 CTS1 P96 XT1 P97 XT2 PA0PA3 INT1INT4 PA4PA7 ALE 4 1 1 2 1 1 1 1 1 1 1 2 3 3 I/O 4 1 1 1 1 1 1 1 Number of Pins 1 I/O I/O Output I/O Input I/O I/O Input I/O Output I/O Input I/O I/O Input I/O Input I/O Output I/O Input I/O Output Input Input Output Output Input Input Input Port 90: I/O port Functions Serial Send Data 0 (programmable open-drain) Port 91: I/O port Serial Receive Data 0 Port 92: I/O port Serial Clock I/O 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 (programmable open-drain) Port 94: I/O port (with pull-up resistor) Serial Receive Data 1 Port 95: I/O port (with pull-up resistor) Serial Clock I/O 1 Serial Data Send Enable 1 (Clear to Send) Port 96: I/O port (open-drain output) Low-frequency oscillator connection pin Port 97: I/O port (open-drain output) Low-frequency oscillator connection pin Ports A0 to A3: I/O ports Interrupt Request Pins 1 to 4: Interrupt request pins with programmable rising edge / falling edge. Ports A4 to A7: I/O ports Address Latch Enable Can be disabled to reduce noise. Non-Maskable Interrupt Request Pin: Interrupt request pin with programmable falling edge or both edge. Operation mode: Fixed to AM1 = 1, AM0 = 1 Open pin Open pin Reset: initializes TMP91FY42. (With pull-up resistor) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter GND pin for AD converter (0 V) High-frequency oscillator connection pins Power supply pins (All DVCC pins should be connected with the power supply pin.) GND pins (0 V) (All DVSS pins should be connected with the power supply pin.) NMI AM01 EMU0 EMU1 RESET VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS Note: An external DMA controller cannot access the device's built-in memory or built-in I/O devices using the BUSRQ and BUSAK signal. 91FY42-7 2006-11-08 TMP91FY42 3. Operation This following describes block by block the functions and operation of the TMP91FY42. Notes and restrictions for eatch book are outlined in 7 "Points of Note and Restrictions" at the end of this manual. 3.1 CPU The TMP91FY42 incorporates a high-performance 16-bit CPU (The 900/L1 CPU). For CPU operation, see the "TLCS-900/L1 CPU". The following describe the unique function of the CPU used in the TMP91FY42; these functions are not covered in the TLCS-900/L1 CPU section. 3.1.1 Reset When resetting the TMP91FY42 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level for at least 10 system clocks (12s at 27MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 x 1/2). When the reset is accept, the CPU: * Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<7:0> PC<15:8> * * * * Value at FFFF00H address Value at FFFF01H address PC<23:16> Value at FFFF02H address Sets the stack pointer (XSP) to 100H. Sets bits When reset is released,the CPU starts executing instructions in accordance with the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows. * * * Initializes the internal I/O registers. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Sets ALE pin to "High-Z" The CPU internal register (except to PC, SR, XSP) and internal RAM data do not change by resetting. Note: Figure 3.1.1 is a reset timing of the TMP91FY42. 91FY42-8 2006-11-08 fFPH Sampling Sampling RESET A16~A23 (P40~P43 imput mode) (P20~P27 imput mode) CS0CS3 R/W (P36 imput mode) ALE Address AD0~AD15 (P00~P07, P10~P17 imput mode) (P30 output mode) Address Address Read RD (After reset is released, startting 0 wait read cycle) Figure 3.1.1 TMP91FY42 Reset Timing Example Data-out (P00~P07, P10~P17 imput mode) (P31 output mode) (P32 imput mode) (Output mode) (Imput mode) (Imput mode) 91FY42-9 AD0~AD15 Address Write WR HWR P30P31 P32~P37, P40~P43 P00~P07, P10~P17, P20~P27, P60~P66, P70~P75, P80~P87, P90~P97, PA0~PA7 : Pull-up (Internal) TMP91FY42 2006-11-08 : High-Z TMP91FY42 3.1.2 Outline of Operation Modes There are single-chip and single-boot modes. Which mode is selected depends on the device's pin state after a reset. * * Single-chip mode: The device normally operations in this mode. After a reset, the device starts executing the internal memory program. Single-boot mode: This mode is used to rewrite the internal flash memory by serial transfer (UART). After a reset, internal boot program starts up, executing an on-board rewrite program. Table 3.1.1 Operation Mode Setup Table Operation Mode RESET Single-chip mode Single-boot mode Mode Setup Input Pin BOOT (P37) L AM0 H AM1 H H 91FY42-10 2006-11-08 TMP91FY42 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP91FY42. 000000H Internal I/O (4 Kbytes) Direct area (n) 000100H 001000H Internal RAM (16 Kbyte) 005000H 64 Kbyte area (nn) 010000H External memory FC0000H 256 Kbyte Internal ROM 16 Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Vector table (256 byte) ( = Internal area) Figure 3.2.1 Memory Map 91FY42-11 2006-11-08 TMP91FY42 3.3 Triple Clock Function and Standby Function TMP91FY42 contains (1) Clock gear, (2) Standby controller, and (3) Noise-reducing circuit. It is used for low-power, low-noise systems. This chapter is organized as follows: * 3.3.1 Block Diagram of System Clock * * * * * 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 SFRs System Clock Controller Prescaler Clock Controller Noise Reduction Circuits Standby Controller 91FY42-12 2006-11-08 TMP91FY42 The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only), (b) Dual clock mode (X1, X2, XT1 and XT2 pins). Figure 3.3.1 shows a transition figure. Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Single clock mode transition figure Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt (b) Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Instruction SLOW mode (fs/2) Dual clock mode transition fiigure Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 91FY42-13 2006-11-08 TMP91FY42 3.3.1 Block Diagram of System Clock SYSCR0 fc/16 /2 /4 /8 /16 fc/16 fFPH /2 /4 fs fFPH fSYS SYSCR1 SYSCR1 Clock gear fSYS TMRA01 toTMRA67 T0 Prescaler CPU ROM RAM TMRB0 to TMRB1 Prescaler Interrupt controller CS/WAIT controller ADC SIO0~SIO1 Prescaler WDT I/O ports SBI T Prescaler Special timer for CLOCK fs Binary counter SYSCR2 fFPH SCOUT Figure 3.3.2 Block Diagram of System Clock Note: TMP91FY42 does not built-in Clock Doubler (DFM). 91FY42-14 2006-11-08 TMP91FY42 3.3.2 SFRs 7 SYSCR0 Bit symbol (00E0H) Read/Write After reset Function XEN 1 6 XTEN 1 5 RXEN 1 4 RXTEN 0 Lowfrequency oscillator (fs) after release of STOP mode 3 RSYSCK R/W 0 2 WUEF 0 1 PRCK1 0 00: fFPH (Note 2) 01: Reserved 10: fc/16 11: Reserved 0 PRCK0 0 HighLowHighfrequency frequency frequency oscillator (fc) oscillator (fs) oscillator (fc) after release 0: Stop 0: Stop 1: Oscillation 1: Oscillation of STOP mode Selects clock Warm-up after release timer of STOP 0: Write mode don't 0: fc care 1: fs 1: Write start timer 0: Read end warm up Select prescaler clock 0: Stop 0: Stop 1: Oscillation 1: Oscillation (Note 1) 1: Read do not end warm up 7 SYSCR1 (00E1H) Bit symbol Read/Write After reset Function 6 5 4 3 SYSCK 0 2 GEAR2 R/W 1 1 GEAR1 0 0 GEAR0 0 Select gear value of high frequency (fc) Select system clock 000: fc 0: fc 001: fc/2 1: fs 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (00E2H) Bit symbol Read/Write After reset Function 6 SCOSEL 0 Selects SCOUT 0: fs 1: fFPH 5 WUPTM1 1 Warm-up timer 00: Reserved 4 WUPTM0 R/W 0 3 HALTM1 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 1 1 0 DRVE R/W 0 Pin state control in STOP/IDLE1 mode 0: I/O off 1: Remains the state before halt 01: 28/inputted frequency 10:214/inputted frequency 11:216/inputted frequency Note 1: SYSCR1 Figure 3.3.3 SFR for System Clock 91FY42-15 2006-11-08 TMP91FY42 7 DFMCR0 Bit symbol (00E8H) Read/Write After reset Function ACT1 R/W 0 6 ACT10 0 5 DLUPFG R 0 4 DLUPTM R/W 0 3 2 1 0 Always write "0" 7 DFMCR1 Bit symbol (00E9H) Read/Write After reset Function - 6 - 5 - 4 - 3 - 2 - 1 - 0 - R/W 0 0 0 1 0 0 1 1 Don't access this register Figure 3.3.4 SFR for DFM Note: TMP91FY42 does not built-in Clock Doubler (DFM). 7 EMCCR0 (00E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON 6 - 0 Always write "0" 5 - 1 Always write "1" 4 - 0 Always write "0" 3 ALEEN R/W 0 0: ALE output disable 1: ALE output enable 2 EXTIN 0 1 DRVOSCH 0 DRVOSCL 1 1 fs oscillator driver ability 1: Normal 0: Weak 1: fc external fc oscillator clock driver ability 1: Normal 0: Weak EMCCR1 (00E4H) Bit symbol Read/Write After reset Function Note1: When restarting the oscillator from the stop oscillation state (e.g. restarting the oscillator in STOP mode), set EMCCR0 Figure 3.3.5 SFR for Noise Reducing 91FY42-16 2006-11-08 TMP91FY42 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 01 (2 /frequency) 10 (2 /frequency) 11 (2 /frequency) 16 14 8 Change to NORMAL Mode 9.0 [s] Change to SLOW Mode 7.8 500 2000 [ms] [ms] [ms] at fOSCH = 27 MHz, fs = 32.768 kHz 0.607 [ms] 2.427 [ms] 91FY42-17 2006-11-08 TMP91FY42 Example 1: SYSCR0 SYSCR1 SYSCR2 WUP: Setting the clock Changing from high frequency (fc) to low frequency (fs). EQU 00E0H EQU 00E1H EQU 00E2H LD (SYSCR2), -X11- - X -B ; Sets warm-up time to 216/fs. SET 6, (SYSCR0) ; Enables low-frequency oscillation. SET 2, (SYSCR0) ; Clears and starts warm-up timer. BIT 2, (SYSCR0) ; Detects stopping of warm-up timer. JR NZ, WUP ; SET 3, (SYSCR1) ; Changes fSYS from fc to fs. RES 7, (SYSCR0) ; Disables high-frequency oscillation. X: Don't care, -: No change Warm-up timer End of warm-up timer Counts up by fSYS Counts up by fs fc fs Enables low frequency Clears and starts warm-up timer Chages fSYS from fc to fs End of warm-up timer Disables high frequency 91FY42-18 2006-11-08 TMP91FY42 Example 2: SYSCR0 SYSCR1 SYSCR2 WUP: Setting the clock Changing from low frequency (fs) to high frequency (fc). EQU 00E0H EQU 00E1H EQU 00E2H LD (SYSCR2), -X10- - - -B ; Sets warm-up time to 214/fc. SET 7, (SYSCR0) ; Enables high-frequency oscillation. SET 2, (SYSCR0) ; Clears and starts warm-up timer. BIT 2, (SYSCR0) ; Detects stopping of warm-up timer. JR NZ, WUP ; RES 3, (SYSCR1) ; Changes fSYS from fs to fc. RES 6, (SYSCR0) ; Disables low-frequency oscillation. X: Don't care, -: No change Warm-up timer End of warm-up timer Counts up by fSYS Counts up by fOSCH fs fc Enables high frequency Clears and starts warm-up timer Chages fSYS from fs to fc End of warm-up timer Disables low frequency 91FY42-19 2006-11-08 TMP91FY42 (2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1 Example 3: SYSCR1 Changing to a high-frequency gear EQU 00E1H LD (SYSCR1), XXXX0000B ; Changes fSYS to fc/2. X: Don't care (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 (Example) SYSCR1 EQU LD LD 00E1H (SYSCR1), XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction. Instruction to be executed after clock gear has changed. (3) Internal colck pin output function P64/SCOUT pin outputs the internal clocks fFPH or fs. The port 6 coutrol register P6CR Table 3.3.2 SCOUT Pin States in the Operation Modes Operation Mode SCOUT NORMAL, SLOW HALT Mode IDLE2 Outputs fs clock IDLE1 STOP Fixed to "0" or "1" 91FY42-20 2006-11-08 TMP91FY42 3.3.4 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA67, TMRB0 to TMRB1, SIO0 to SIO1,SBI) there is a prescaler which can divide the clock. The T clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 2. The setting of the SYSCR0 3.3.5 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator] (4) Disables Output for ALE-pin (4) Runaway provision with SFR protection register The above functions are performed by making the appropriate settings in the EMCCR0 to EMCCR1 registers. (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 Resonator C2 X2 pin X1 pin Enable oscillation (STOP + EMCCR0 (Setting method) The drivability of the oscillator is reduced by writing 0 to EMCCR0 91FY42-21 2006-11-08 TMP91FY42 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin Enable oscillation EMCCR0 C1 Resonator (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0 (3) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation (STOP + EMCCR0 EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing 1 to EMCCR0 Note: Do not write EMCCR0 91FY42-22 2006-11-08 TMP91FY42 (4) Disables Output for ALE-pin (Purpose) Disables output ALE pulse for reducing noise when CPU does not access to external area. (Block diagram) EMCCR0 (Setting method) ALE pin is set to high-impedance by writing "0" to EMCCR0 To EMCCR1 Write except "1FH Write "1FH" Protect register EMCCR0 S R Q Write signal to the SFR which is disables Write signal to SFR Write signal to the othre SFR (Setting method) The protect-status is ON by writing except "1FH" Codes to EMCCR1 register, and CPU is disabled to write-operation to the specific-SFR. The protect-status is OFF by writing "1FH" code to EMCCR1.The protect-status is set to EMCCR0 91FY42-23 2006-11-08 TMP91FY42 3.3.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 TMRA01 TMRA23 TMRA45 TMRA67 TMRB0 TMRB1 SIO0 SIO1 SBI AD converter WDT SFR TA01RUN b. IDLE1: Only the oscillator and the Special timer for CLOCK continue to operate. c. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 3.3.4. Table 3.3.4 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA01~TMRA67, TMRB0~TMRB1 SIO0~SIO1, SBI AD converter WDT Special timer for CLOCK Interrupt controller Operational available Operate Available to select operation block Stop IDLE2 11 Stop IDLE1 10 STOP 01 See Table 3.3.7, Table 3.3.8 Keep the state when the HALT instruction was executed. Block 91FY42-24 2006-11-08 TMP91FY42 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register 91FY42-25 2006-11-08 TMP91FY42 Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT mode NMI INTWD Source of halt state clearance Interrupt Enabled (Interrupt level) (Interrupt mask) Interrupt Disabled (Interrupt level) < (Interrupt mask) IDLE2 (Note2) IDLE1 STOP x x x x x x x *1 IDLE2 - - IDLE1 STOP - - - - x *1 INT0INT4 (Note 1) INTRTC Interrupt x x x x x x x x x x x x x x x x x x x *1 x x x x x x x INT5INT8 INTTA0INTTA7 INTTB00, INTTB01, INTTB10, INTTB11,INTTBOF0, INTTBOF1 INTRX0INTRX1, INTTX0INTTX1 INTSBI INTAD RESET Initialize LSI. : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. x: It can not be used to release the HALT mode . -: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. Note2: When the external interrupts INT5 to INT8 are used during IDLE2 mode, set to 1 for TB0RUN (Example releasing IDLE1 mode) An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH INT0 LD LD LD EI LD HALT (P6FC), 08H (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 88H ; Sets P63 to INT0. ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets interrupt level to 5 for CPU. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 91FY42-26 2006-11-08 TMP91FY42 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0~A23 ALE AD0~AD15 RD WR Address Data Address Address Data Interrupt for release IDLE2 mode Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt b. IDLE1 mode In IDLE1 mode, only the internal oscillator and the Special timer for CLOCK continue to operate. The system clock in the MCU stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.3.7 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0A23 ALE AD0AD15 RD WR Address Data Address Data Interrupt for release IDLE1 mode Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91FY42-27 2006-11-08 TMP91FY42 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 Warm-up timer X1 A0A23 ALE AD0AD15 RD WR Address Data Address Data Interrupt for release STOP mode Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.6 Sample Warm-up Times after Clearance of STOP Mode at fOSCH = 27 MHz, fs = 32.768 kHz SYSCR0 0 (fc) 1 (fs) SYSCR2 9.0 s 7.8 ms 8 10 (214) 0.607 ms 500 ms 11 (216) 2.427 ms 2000 ms 91FY42-28 2006-11-08 TMP91FY42 * (Setting example) * The STOP mode is entered when the low frequency operates, and high frequency operates after releasing due to NMI. Address SYSCR0 SYSCR1 SYSCR2 8FFDH 9000H 9002H 9005H NMI EQU EQU EQU LD LD LD HALT 00E0H 00E1H 00E2H (SYSCR1), 08H (SYSCR2), -X1001X1B (SYSCR0), 011000 - -B ; fSYS = fs/2. 14 ; Sets warm-up time to 2 /fOSCH. ; Operates high-frequency after released. Clears and starts hit warm-up timer (High frequency) End NMI interrupts routine 9006H LD XX, XX RETI * -: No change 91FY42-29 2006-11-08 TMP91FY42 Table 3.3.7 Input buffer state table Input Buffer State Port Name Input Function Name When the CPU is operating When Used as function Pin ON upon external read - ON P33 P34 P35-P37 P40-43 P50-52, P54-57 P53 WAIT During Reset In HALT mode (IDLE2) When Used as function Pin OFF OFF In HALT mode (STOP) When Used as Input Port When Used as Input Port When Used as function Pin OFF When Used as Input Port When Used as function Pin OFF When Used as Input Port P00-07 P10-17 P20-27 P32 AD0-AD7 AD8-AD15 - - OFF - OFF - OFF OFF - *1 *1 OFF *1 ON BUSRQ ON ON ON - - ON ON - - - - - OFF *1 *1 *2 OFF ADTRG SCK SDA SCL,SI INT0 - - ON upon port read OFF OFF ON *2 P60 P61 P62 P63 P64-66 P70 P73 P71-72, P74-75 P80 P81 P84 P85 P82-83, P86-87 P90,P93 P91 P92 P94 P95 P96 P97 PA0 PA1 PA2 PA3 PA4-A7 NMI , RESET , ON ON ON OFF ON - - - ON TA0IN TA4IN - ON - ON - ON - OFF - INT5,TB0IN0 INT6,TB0IN1 INT7,TB1IN0 INT8,TB1IN1 - - ON ON ON ON ON ON ON OFF - - - - RXD0 SCLK0, CTS0 RXD1 SCLK1, CTS1 For XT1 oscillator For port - OFF ON ON OFF ON OFF - ON OFF OFF OFF - OFF OFF ON - OFF ON - INT1 INT2 INT3 INT4 - - ON OFF ON ON OFF ON OFF ON - - - - - - - - AM0,AM1 X1 - ON ON - ON - ON ON - - OFF OFF ON: The buffer is always turned on. A current flow the input buffer if the input pin is not driven. OFF: The buffer is always turned off. -: No applicable *1: Port having a pull-up/pull-down resistor. *2: AIN input does not cause a current to flow through the buffer. 91FY42-30 2006-11-08 TMP91FY42 Table 3.3.8 Output buffer state table Input Buffer State Port Name Output Function Name When the CPU is operating When Used as function Pin ON upon external write During Reset In HALT mode (IDLE2) When Used as function Pin OFF In HALT mode (STOP) When Used as output Port When Used as output Port When Used as function Pin OFF When Used as output Port When Used as function Pin When Used as output Port P00-07 P10-17 P20-27 P30 P31 P32 P33-34,37 P35 P36 P40 P41 P42 P43 P60 P61 P62 P63,65-66 P64 P70,73 P71 P72 P74 P75 P80-81, P84-85 P82 P83 P86 P87 P90 P91,94 P92 P93 P95 P96 P97 PA0-A7 ALE X2 AD0-AD7 AD8-AD15 A8-A15 A0-A7 A16-A23 RD WR HWR OFF OFF ON ON *1 - - - - ON ON - BUSAK *1 *1 *1 *1 *1 *1 *1 R/W CS0 CS1 CS2 CS3 SCK SDA,SO SCL - SCOUT - TA1OUT TA3OUT TA5OUT TA7OUT ON ON ON OFF ON - ON - - ON - ON - ON - ON - OFF - OFF OFF ON ON ON OFF - - - - - TB0OUT0 TB0OUT1 TB1OUT0 TB1OUT1 TXD0 - SCLK0 TXD1 SCLK1 - For XT2 oscillator For port - - - ON ON ON OFF - - - - ON ON OFF ON OFF ON - ON - ON - OFF - ON OFF - ON OFF ON - ON OFF - ON OFF ON - OFF - ON Output "H" level OFF ON - OFF - ON Output "H" level - ON: The buffer is always turned on. When the bus is released, however, output buffers for some pins are turned off. OFF: The buffer is always turned off. -: Not applicable *1: Port having a pull-up/pull-down resistor 91FY42-31 2006-11-08 TMP91FY42 3.4 Interrupts Interrupts are controlled by the CPU interrupt mask register SR A (Fixed) individual interrupt vector number is assigned to each interrupt. One of six (Variable) priority level can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at 7 as the highest level. When an interrupt is generated, the interrupt controller sends the piority of that interrupt to the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register 91FY42-32 2006-11-08 TMP91FY42 Interrupt processing Micro DMA soft start request Yes Interrupt specified by micro DMA start vector? No Clear interrupt request flag Interrupt vector value V read Interrupt request F/F clear General-purpose interrupt processing Data transfer by micro DMA PUSH PC PUSH SR SR Count Count - 1 Micro DMA processing Count = 0 No Yes Clear vector register generating micro DMA transfer and interrupt (INTTC0 to INTTC3) PC (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.4.1 Overall Interrupt Processing Flow 91FY42-33 2006-11-08 TMP91FY42 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: The smaller vector value has the higher priority level.) (2) The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (Indicated by XSP). (3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask register 91FY42-34 2006-11-08 TMP91FY42 Table 3.4.1 TMP91FY42 Interrupt Vectors Table Default Priority 1 2 3 4 5 6 7 8 9 10 - 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Maskable Non maskable Type Interrupt Source and Source of Micro DMA Request Reset or "SWI 0" instruction "SWI 1" instruction INTUNDEF: Illegal instruction or "SWI 2" instruction "SWI 3" instruction "SWI 4" instruction "SWI 5" instruction "SWI 6" instruction "SWI 7" instruction Vector Value (V) 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H Vector Micro DMA Reference Start Vector Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H : FFFFFCH - - - - - - - - - - - 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H - - - - - : - NMI pin INTWD: Watchdog timer Micro DMA (MDMA) INT0 pin INT1 pin INT2 pin INT3 pin INT4 pin INT5pin INT6 pin INT7 pin INT8 pin INTTA0: INTTA1: INTTA2: INTTA3: INTTA4: INTTA5: INTTA6: INTTA7: 8-bit timer 0 8-bit timer 1 8-bit timer 2 8-bit timer 3 8-bit timer 4 8-bit timer 5 8-bit timer 6 8-bit timer 7 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H : 00FCH INTTB00: 16-bit timer 0 (TB0RG0) INTTB01: 16-bit timer 0 (TB0RG1) INTTB10: 16-bit timer 1 (TB0RG0) INTTB11: 16-bit timer 1 (TB0RG1) INTTBOF0: 16-bit timer 0 (Over-flow) INTTBOF1: 16-bit timer 1 (Over-flow) INTRX0: INTTX0: INTRX1: INTTX1: INTSBI: INTAD: INTTC0: INTTC1: INTTC2: INTTC3: : (Reserved) Serial reception (Channel 0) Serial transmission (Channel 0) Serial reception (Channel 1) Serial transmission (Channel 1) SBI interrupt AD conversion end Micro DMA end (Channel 0) Micro DMA end (Channel 1) Micro DMA end (Channel 2) Micro DMA end (Channel 3) INTRTC: Special timer for clock (Reserved) 91FY42-35 2006-11-08 TMP91FY42 3.4.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91FY42 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (Level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. Micro. The micro DMA has 4 channels and is possible continuous transmission by specifing the say later burst mode. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes to a standby mode by HALT instruction, the requirement of micro DMA will be ignored (Pending). (1) Micro DMA operation When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite of any interrupt source's level. The micro DMA is ignored on Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in the Figure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 91FY42-36 2006-11-08 TMP91FY42 If a micro DMA request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel 0 (High) > Channel 3 (Low)). While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (The upper 8 bits of the 32 bits are not valid). Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One word) transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/destination addresses are increased, decreased, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the transfer modes, see 3.4.2 (4) "Detailed description of the transfer mode register". As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 30 interrupts shown in the micro DMA start vectors of Table 3.4.1 and by the micro DMA soft start, making a total of 31 interrupts. Figure 3.4.2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer source/transfer destination addresses both even-numberd values.) 1 state (Note 1) DM2 DM3 DM4 DM5 DM6 (Note 2) DM7 DM8 DM1 X1 A0 to A23 RD WR / HWR Transfer source address Transfer destination address D0 to D15 Input Output Figure 3.4.2 Timing for Micro DMA Cycle States 1 to 3: Instruction fetch cycle (gets next address code). If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycle State 6: Dummy cycle (The address bus remains unchanged from state 5) States 7 to 8: Micro DMA write cycle Note 1: If the source address area is an 8-bit bus, it is increased by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. Note 2: If the destination address area is an 8-bit bus, it is increased by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. 91FY42-37 2006-11-08 TMP91FY42 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91FY42 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing "1" to each bit of DMAR register causes micro DMA once (If write "0" to each bit, micro DMA doesn't operate). At the end of transfer, the corresponding bit of the DMAR register which support the end channel are automatically cleared to "0". Only one-channel can be set for DMA request at once. (Do not write "1" to plural bits.) When writing again "1" to the DMAR register, check whether the bit is "0" before writing "1". If read "1", micro DMA transfer isn't started yet. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is "0" after start up of the micro DMA. If execute soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn't change. Don't use Read-modify-write instruction to avoid writing to other bits by mistake. Symbol Name DMA DMAR request register Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 0 2 DMAR2 0 R/W 1 DMAR1 0 0 DMAR0 0 DMA request (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers in CPU. Data setting for these registers is done by an LDC cr, r instruction. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0 DMA counter register 0 DMA mode register 0 : Only use LSB 24 bits : 1 to 65536 DMA destination address register 0 : Only use LSB 24 bits Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits DMA source address register 3 DMA destination address register 3 DMA counter register 3 DMA mode register 3 91FY42-38 2006-11-08 TMP91FY42 (4) Detailed description of the transfer mode register 8 bits DMAM0 to DMAM3 0 0 0 Mode Note: When setting a value in this register, write 0 to the upper 3 bits. Number of Transfer Bytes 000 (Fixed) 01 10 001 00 01 10 010 00 01 10 011 00 01 10 100 00 01 10 101 00 Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Counter mode 000 00 Byte transfer Mode Description Transfer destination address INC mode ............................................. I/O to memory (DMADn+) (DMASn) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer destination address DEC mode ............................................. I/O to memory (DMADn-) (DMASn) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer source address INC mode ............................................. Memory to I/O (DMADn) (DMASn+) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer source address DEC mode ............................................. Memory to I/O (DMADn) (DMASn-) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Fixed address mode ...................................................... I/O to I/O (DMADn) (DMASn-) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Minimum Number of Execution Time Execution States at fc = 27 MHz 8 states 593 ns 12 states 889 ns 8 states 12 states 593 ns 889 ns 8 states 12 states 593 ns 889 ns 8 states 12 states 593 ns 889 ns 8 states 12 states 593 ns 889 ns ................... for counting number of times interrupt is generated DMASn DMASn + 1 DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. 5 states 370 ns Note 1: "n" is the corresponding micro DMA channels 0 to 3 DMADn+/DMASn+: Post-increment (Increment register value after transfer) DMADn-/DMASn-: Post-decrement (Decrement register value after transfer) The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC) addresses. Note 2: Execution time is under the condition of: 16-bit bus width (Both translation and destination address area)/0 waits/fc = 27 MHz/selected high-frequency mode (fc x 1) Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the above table. 91FY42-39 2006-11-08 TMP91FY42 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 45 interrupt channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: * * * * * when reset occurs when the CPU reads the channel vector after accepted its interrupt when executing an instruction that clears the interrupt (Write DMA start vector to INTCLR register) when the CPU receives a micro DMA request (when micro DMA is set) when the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are generated at the same time, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simulateous interrupts and its vector address to the CPU. The CPU compares the priority value 91FY42-40 2006-11-08 Interrupt controller CPU 1 NMI V = 20H V = 24H RESET interrupt vector read Interrupt mask F/F RESET Interrupt request signal to CPU IFF2:0 3 3 INTRQ2 to 0 3 Interrupt level detect EI1 to 7 DI Interrupt request F/F S Q R INTWD D CLR 6 Q Priority setting register Dn Dn + 1 Dn + 2 Decoder Y1 A Y2 B Y3 C Y4 Y5 Y6 Dn + 3 Priority encoder 1 1 2 Highest A 7 B 3 priority 6 4 interrupt C 5 level select 6 7 if INTRQ2 to 0 IFF 2 to 0 then 1. D0 D1 32 Interrupt vector generator D2 D3 D4 D5 D6 D7 Interrupt request signal INT0 R Interrupt request F/F Interrupt vector read Micro DMA acknowledge Reset Interrupt request F/F S Q INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INTTA0 Interrupt vector read V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH During IDLE1 During STOP Figure 3.4.3 Block Diagram of Interrupt Controller 91FY42-41 V = 9CH V = A0H V = A4H V = A8H V = ACH 4 input OR 34 Soft start 4 DQ CLR INTTC0 S 6 Selector 0 1 DMA0V DMA1V DMA2V DMA3V 2 3 A B Micro DMA channel priority encoder 2 HALT release RESET INT0, 1, 2, 3, 4, RTC NMI Micro DMA request if IFF = 7 then 0 2 Micro DMA counter 0 interrupt INTAD INTTC0 INTTC1 INTTC2 INTTC3 Micro DMA start vector setting register D5 D4 D3 D2 D1 D0 RESET Micro DMA channel specification TMP91FY42 2006-11-08 TMP91FY42 (1) Interrupt level setting registers Symbol Name INT0 & Address 7 IADC R 0 6 INTAD IADM2 0 INT2 I2M2 0 INT4 I4M2 0 INT6 5 IADM1 R/W 0 I2M1 R/W 0 I4M1 R/W 0 4 IADM0 0 I2M0 0 I4M0 0 3 I0C R 0 I1C R 0 I3C R 0 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INT5 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 0 I0M0 0 I1M0 0 I3M0 0 INTE0AD INTAD 90H enable INT1 & INTE12 INT2 enable 91H I2C R 0 INT3& INTE34 INT4 enable 92H I4C R 0 INT5 & INTE56 INT6 enable 93H I6C R 0 I6M2 I6M1 R/W I6M0 I5C R I5M2 I5M1 R/W I5M0 0 INT8 0 0 0 0 INT7 0 0 INT7 & INTE78 INT8 enable 94H I8C R 0 I8M2 I8M1 R/W I8M0 I7C R I7M2 I7M1 R/W I7M0 0 ITA1M2 0 ITA3M2 0 ITA5M2 0 0 ITA1M1 R/W 0 ITA3M1 R/W 0 ITA5M1 R/W 0 0 ITA1M0 0 ITA3M0 0 ITA5M0 0 0 ITA0C R 0 ITA2C R 0 ITA4C R 0 0 ITA0M2 0 ITA2M2 0 ITA4M2 0 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITA4M1 R/W 0 0 ITA0M0 0 ITA2M0 0 ITA4M0 0 INTTA0 & INTETA01 INTTA1 INTTA1 (TMRA1) 95H ITA1C R 0 INTTA0 (TMRA0) enable INTTA2 & INTETA23 INTTA3 INTTA3 (TMRA3) 96H ITA3C R 0 INTTA2 (TMRA2) enable INTTA4 & INTETA45 INTTA5 INTTA5 (TMRA5) 97H ITA5C R 0 INTTA4 (TMRA4) enable INTTA7 (TMRA7) INTTA6 & INTETA67 INTTA7 INTTA6 (TMRA6) ITA7M0 ITA6C R 0 0 0 ITA6M2 ITA6M1 R/W 0 0 ITA6M0 98H ITA7C R 0 ITA7M2 ITA7M1 R/W enable 0 0 Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91FY42-42 2006-11-08 TMP91FY42 Symbol & Name INTTB00 Address 7 ITB01C R 0 ITB11C R 0 ITF1C R 0 ITX0C R 0 6 ITB01M2 5 ITB01M1 4 ITB01M0 3 ITB00C R 0 ITB10C R 0 ITF0C R 0 IRX0C R 0 IRX1C R 0 ISBIC R 0 ITC0C R 0 ITC2C R 0 2 ITB00M2 1 ITB00M1 0 ITB00M0 INTTB01 (TMRB0) 99H R/W 0 0 0 INTTB11 (TMRB1) 9AH ITB11M2 ITB11M1 ITB11M0 INTTB00 (TMRB0) R/W 0 0 0 INTTB10 (TMRB1) ITB10M2 ITB10M1 ITB10M0 INTETB0 INTTB01 enable INTTB10 INTETB1 & INTTB11 enable INTTBOF0 & R/W 0 ITF1M2 0 INTTX0 ITX0M2 0 INTTX1 ITX1M2 0 INTRTC IRTCM2 0 INTTC1 ITC1M2 0 INTTC3 ITC3M2 0 0 ITF1M1 R/W 0 ITX0M1 R/W 0 ITX1M1 R/W 0 IRTCM1 R/W 0 ITC1M1 R/W 0 ITC3M1 R/W 0 0 0 ITC3M0 0 ITC1M0 0 IRTCM0 0 ITX1M0 0 ITX0M0 0 ITF1M0 INTTBOF1 (TMRB1 Over-flow) R/W 0 ITF0M2 0 INTRX0 IRX0M2 0 INTRX1 IRX1M2 0 INTSBI ISBIM2 0 INTTC0 ITC0M2 0 INTTC2 ITC2M2 0 ITC2M1 R/W 0 0 ITC2M0 ITC0M1 R/W 0 0 ITC0M0 ISBIM1 R/W 0 0 ISBIM0 IRX1M1 R/W 0 0 IRX1M0 IRX0M1 R/W 0 0 IRX0M0 0 ITF0M1 R/W 0 0 0 ITF0M0 INTTBOF0 (TMRB0 Over-flow) INTETB01V INTTBOF1 enable (Over flow) 9BH INTRX0 & INTES0 INTTX0 enable 9CH INTRX1 & INTES1 INTTX1 enable 9DH ITXT1C R 0 INTSBI & INTES2RTC RTC 9EH IRTCC R 0 enable INTTC0 & INTETC01 INTTC1 enable A0H ITC1C R 0 INTTC2 & INTETC23 INTTC3 enable A1H ITC3C R 0 Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91FY42-43 2006-11-08 TMP91FY42 (2) External interrupt control Symbol Name Address 7 - 0 6 I4EDGE 0 0: Rising 1: Falling 5 I3EDGE 0 0: Rising 1: Falling 4 I2EDGE W 3 I1EDGE 0 0: Rising 1: Falling 2 I0EDGE 0 0: Rising 1: Falling 1 I0LE 0 0: Edge 1: Level 0 NMIREE 0 even on rising/ falling edge of NMI Interrupt IIMC input mode control 0 0: Rising 1: Falling 8CH (Prohibit RMW) Always write 0 INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 mode 1: Operates INT0 level enable 0 1 0 1 edge detect INT H level INT INT request generation at falling edge INT request generation at rising/falling edge NMI rising edge enable (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH: Clears interrupt request flag INT0. Symbol Name Address Interrupt INTCLR clear control 88H (Prohibit RMW) 7 6 5 CLRV5 0 4 CLRV4 0 3 CLRV3 W 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 Interrupt vector (4) Micro DMA start vector registers This register assigns micro DMA processing to which interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the higher number (Micro DMA chaining). 91FY42-44 2006-11-08 TMP91FY42 Symbol Name DMA0 Address 7 6 5 DMA0V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 R/W 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA0V start vector 80H 0 DMA1V5 DMA0 start vector DMA1 DMA1V start vector 81H R/W 0 DMA2V5 82H 0 DMA3V5 83H 0 DMA1 start vector DMA2 DMA2V start vector R/W DMA2 start vector DMA3 DMA3V start vector R/W DMA3 start vector (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches zero after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to 1 specifies a burst. Symbol Name DMA DMAR software request register DMA DMAB burst register 8AH 0 0 Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 0 DMAB3 2 DMAR2 0 DMAB2 R/W 1 DMAR1 0 DMAB1 R/W 0 0 DMAR0 0 DMAB0 0 1: DMA software request 1. DMA burst request 91FY42-45 2006-11-08 TMP91FY42 (6) Attention point The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag (Note) between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0008H and reads the interrupt vector address FFFF08H. To avoid the avobe plogram, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1-instructions (e.g., "NOP" x 1 times). In the case of changing the value of the interrupt mask register INT0 Level Mode In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H; Switches interrupt input mode from level mode to edge mode. LD (INTCLR), 0AH; Clears interrupt request flag. NOP EI ; Wait EI instruction INTRX The interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag. INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input change from high to low after interrupt request has been generated in level mode. (H L) INTRX: Instruction which read the receive buffer 91FY42-46 2006-11-08 TMP91FY42 3.5 Port Functions The TMP91FY42 features 81-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 list the functions of each port pin. Table 3.5.2 list I/O registers and their specifications. Table 3.5.1 Port Functions (1/2) (R: PU = with programmable pull-up resistor) Port Name Port 0 Port 1 Port 2 Port 3 Pin Name P00P07 P10P17 P20P27 P30 P31 P32 P33 P34 P35 P36 P37 Number of Pins 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 Direction I/O I/O I/O Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - - - - PU PU PU PU PU PU PU PU PU PU - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Direction Setting Unit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Name for Built-in Function AD0 to AD7 AD8 to AD15/A8 to A15 A16 to A23/A0 to A7 WR HWR WAIT BUSRQ BUSAK R/W Port 4 P40 P41 P42 P43 CS0 CS1 CS2 CS3 Port 5 Port 6 P50 to P57 P60 P61 P62 P63 P64 P65 P66 AN0 to AN7, ADTRG (P53) SCK SO/SDA SI/SCL INT0 SCOUT Port 7 P70 P71 P72 P73 P74 P75 TA0IN TA1OUT TA3OUT TA4IN TA5OUT TA7OUT TB0IN0/INT5 TB0IN1/INT6 TB0OUT0 TB0OUT1 TB1IN0/INT7 TB1IN1/INT8 TB1OUT0 TB1OUT1 TXD0 RXD0 SCLK0/ CTS0 TXD1 RXD1 SCLK1/ CTS1 XT1 XT2 INT1 to INT4 Port 8 P80 P81 P82 P83 P84 P85 P86 P87 Port 9 P90 P91 P92 P93 P94 P95 P96 P97 Port A PA0 to PA3 PA4 to PA7 91FY42-47 2006-11-08 TMP91FY42 Table 3.5.2 I/O Registers and Specifications (1/3) Port Port 0 Pin Name P00 to P07 Specification Input port Output port AD0 to AD7 bus (Note 1) After reset I/O Register Pn x x x PnCR 0 1 x 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 None 1 1 0 None 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 None 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 None None PnFC Port 1 P10 to P17 Input port Output port AD8 to AD15 bus (Note 1) A8 to A15 Input port Output port A0 to A7 output A16 to A23 output x x x x Port 2 P20 to P27 x x x x Port 3 P30 Output port Outputs RD only when accessing external space Always RD output x 1 0 P31 Output port Outputs WR only when accessing external space x x 0 P32 to P37 Input port (without PU) Input port (with PU) Output port 1 x x 0 1 0 1 x x 0 P32 P33 HWR output WAIT input (without PU) WAIT input (with PU) P34 P35 P36 Port 4 P40 to P43 BUSRQ input (without PU) BUSRQ input (with PU) BUSAK output R / W output Input port (without PU) Input port (with PU) Output port 1 x x x x x P40 P41 P42 P43 Port 5 P50 to P57 P53 Port 6 P60 to P66 CS0 output CS1 output CS2 output CS3 output Input port AN0 to AN7 input ADTRG input x x x Input port Output port x x x x x 0 1 0 1 0 1 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 P60 SCK input SCK output P61 SDA input SDA output SO output (Note 2) x x x x P62 SI input SCL input SCL output (Note 2) x x x P63 P64 INT0 input SCOUT output 91FY42-48 2006-11-08 TMP91FY42 Table 3.5.3 I/O Registers and Specifications (2/3) Port Port 7 Pin Name P70 to P75 P70 P71 P72 P73 P74 P75 Specification Input port Output port TA0IN input TA1OUT output TA3OUT output TA4IN input TA5OUT output TA7OUT output Input port Output port TB0IN0, INT5 input TB0IN1, INT6 input TB0OUT0 output TB0OUT1 output TB1IN0, INT7 input TB1IN1, INT8 input TB1OUT0 output TB1OUT1 output Input port Output port TXD0 output RXD0 input SCLK0 input SCLK0 output CTS0 input After reset I/O Register Pn x x x x x x x x PnCR 0 1 0 1 1 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 1 1 1 None PnFC 0 0 None 1 1 None 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 None 0 1 0 1 None 0 1 0 Port 8 P80 to P87 P80 P81 P82 P83 P84 P85 P86 P87 x x x x x x x x x x Port 9 P90 to P95 P90 P91 P92 x x x x x x x x x x x x x P93 P94 P95 TXD1 output RXD1 input SCLK1 input SCLK1 output CTS1 input P96 to P97 Input port Output port XT1 to XT2 (Note 3) x x x x x x x x Port A PA0 to PA7 PA0 PA1 PA2 PA3 Input port Output port INT1 input INT2 input INT3 input INT4 input X: Don't care Note 1: There is not port settting for changing AD0 to AD7 pins. It function is changed automatically by accsessing external area. Note 2: When P61/P62 are used as SDA/SCL open-drain outputs, P60DE 91FY42-49 2006-11-08 TMP91FY42 * Note about bus release and programmable pull-up I/O port pins When the bus is released (e.g., when BUSAK = 0), the output buffers for AD0 to AD15, A0 to A23, and the control signals ( RD , WR , HWR , R / W and CS0 to CS3 ) are off and are set to high-impedance. However, the output of built-in programmable pull-up resistors are kept before the bus is released. These programmable pull-up resistors can be selected ON/OFF by programmable when they are used as the input ports. When they are used as output ports, they cannot be turned ON/OFF in software. Table 3.5.4 shows the pin states after the bus has been released. Table 3.5.4 Pin states (after bus release) Pin Name P00~P07 (AD0~AD7) P10~P17 (AD8~AD15/A8~A15) P20~P27 (A16~A23) P30 ( RD ) P31 ( WR ) P32 ( HWR ) P37 P36 (R/ W ) P40 ( CS0 ) P41 ( CS1 ) P42 ( CS2 ) P43 ( CS3 ) First sets all bits to high then sets them to High-impedance (HZ). Output buffer is OFF. The programmable pull up resistor is ON irrespective of the output. The state is not changed. (Don't become to high-impedance (HZ)). Become high-impedance (HZ). The Pin State (when the bus is released) Port Mode Function Mode 91FY42-50 2006-11-08 TMP91FY42 Figure 3.5.1 shows an example external interface circuit when the bus release function is used. When the bus is released, neither the internal memory nor the internal I/O can be accessed. However, the internal I/O continues to operate. As a result, the watchdog timer also continues to run. Therefore, the bus release time must be taken into account and care must be taken when setting the detection time for the WDT. P30 ( RD ) P31 ( WR ) P32 ( HWR ) P36 ( R / W ) P40 ( CS0 ) P41 ( CS1 ) P42 ( CS2 ) P43 ( CS3 ) System control bus P20 (A16) Address bus (A23A16) P27 (A23) Figure 3.5.1 Interface Circuit Example (Using bus release function) The above circuit is necessary to set the signal level when the bus is released. A reset sets P30 ( RD ) and P31 ( WR ) to output, and P40 ( CS0 ), P41 ( CS1 ), P42 ( CS2 ), P43 ( CS3 ) P32 ( HWR ) and P35 ( BUSAK ) to input with pull-up resistor. 91FY42-51 2006-11-08 TMP91FY42 3.5.1 Port 0 (P00 to P07) Port 0 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P0CR. Resetting resets all bits of the output latch P0, the control register P0CR to 0 and sets port 0 to input mode. In addition to functioning as a general-purpose I/O port, port 0 can also function as an Address data bus (AD0 to AD7). When external memory is accesed, the port automatically functions as the Address data bus (AD0 to AD7) and all bits of P0CR are cleared to 0. Reset Direction control (on bit basis) P0CR write Internal data bus Output latch Output buffer P0 write S B Port 0 P00P07 (AD0AD7) Selector P0 read A Figure 3.5.2 Port 0 Port 0 Register 7 P0 (0000H) Bit symbol Read/Write After reset P07 6 P06 5 P05 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 Data from external port (Output latch register is cleared to 0.) Port 0 Control Register 7 P0CR (0002H) Bit symbol Read/Write After reset Function 0 P07C 6 P06C 0 5 P05C 0 4 P04C W 0 0: Input 3 P03C 0 1:Output 2 P02C 0 1 P01C 0 0 P00C 0 Port 0 input/output settings Note 1: Read-modify-write is prohibited for P0CR. Note 2: When accessing external, P0CR is AD0 to AD7 and it is cleared to 0. Figure 3.5.3 Register for Port 0 91FY42-52 2006-11-08 TMP91FY42 3.5.2 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR and the function register P1FC. Resetting resets all bits of the output latch P1, the control register P1CR and the function register P1FC to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 can also function as an Address data bus (AD8 to AD15) and Address bus (A8 to A15). Reset Direction control (on bit basis) P1CR write Function control (on bit basis) Internal data bus P1FC write Output latch Output buffer P1 write S B Port 1 P10P17 (AD8AD15/A8A15) Selector P1 read A Figure 3.5.4 Port 1 91FY42-53 2006-11-08 TMP91FY42 Port 1 Register 7 P1 P0 (0001H) (0000H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to 0.) Port 1 Control Register 7 P1CR (0004H) Bit symbol Read/Write After reset Function 0 P17C 6 P16C 0 5 P15C 0 4 P14C W 0 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 Port 1 function settings Port 1 Function Register 7 P1FC (0005H) Bit symbol Read/Write After reset Function 0 P17F 6 P16F 0 5 P15F 0 4 P14F W 0 3 P13F 0 2 P12F 0 1 P11F 0 0 P10F 0 Port 1 function settings Port 1 function settings Note 1: Read-modify-write is prohibited for P1CR and P1FC. Note 2: Figure 3.5.5 Register for Port 1 91FY42-54 2006-11-08 TMP91FY42 3.5.3 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P2CR and the function register P2FC. In addition to functioning as a general-purpose I/O port, port 2 can also function as an address bus (A0 to A7) and (A16 to A23). A16A23 A0A7 Reset B Selector A S Direction control (on bit basis) P2CR write Function control (on bit basis) Internal data bus P2FC write S Output latch A Selector B Output buffer P2 write S B Port 2 P20P27 (A0A7/A16A23) Selector P2 read A Figure 3.5.6 Port 2 91FY42-55 2006-11-08 TMP91FY42 Port 2 Register 7 P2 P0 (0006H) (0000H) Bit symbol Read/Write After reset P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Data from external port (Output latch register is set to 1.) Port 2 Control Register 7 P2CR (0008H) Bit symbol Read/Write After reset Function 0 P27C 6 P26C 0 5 P25C 0 4 P24C W 0 3 P23C 0 2 P22C 0 1 P21C 0 0 P20C 0 Port 2 function settings Port 2 Function Register 7 P2FC (0009H) Bit symbol Read/Write After reset Function 0 P27F 6 P26F 0 5 P25F 0 4 P24F W 0 3 P23F 0 2 P22F 0 1 P21F 0 0 P20F 0 Port 2 function settings Port 2 function settings Note 1: Read-modify-write is prohibited for P2CR and P2FC. Note 2: Figure 3.5.7 Register for Port 2 91FY42-56 2006-11-08 TMP91FY42 3.5.4 Port 3 (P30 to P37) Port 3 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set using control register P3CR and function register P3FC. Resetting set all bits of output latch P3 to "1", and control register P3CR (Bits 0 and 1 are unused), and function register P3FC to "0". Resetting also outputs 1 frim P30 and P31, sets P32 to P37 to input mode, and connects a pull-up resistor. In addition to functioning as a general-purpose I/O port, Port 3 also functions as an I/O for the CPU's control/status signal. When P30 pin is defined as RD signal output mode ( 91FY42-57 2006-11-08 TMP91FY42 Reset Function control (on bit basis) Internal data bus P3FC write S Selector S Output latch P3 write RD , WR A B P30( RD ) Output buffer P31( WR ) P3 read Reset Direction control (on bit basis) P3C write Function control Internal data bus (on bit basis) P3FC write S Selector S Output latch P3 write HWR , BUSAK , R/ W P-ch A B Programable Pull-up P32( HWR ) Output buffer P35( BUSAK ) P36(R/ W ) P37 S B Selector P3 read A Figure 3.5.8 Port 3 (P30, P31, P32, P35, P36, P37) 91FY42-58 2006-11-08 TMP91FY42 Reset Direction control (on bit basis) P3CR write Internal data bus S Output latch P3 write S B Selector P3 read A P-ch Programable Pull-up P33 ( WAIT ) Output buffer Internal WAIT Reset Direction control (on bit basis) P3CR write Function control Internal data bus (on bit basis) P3FC write S Output latch P3 write S B Selector P3 read A P-ch Programable Pull-up P34 ( BUSRQ ) Internal BUSRQ Figure 3.5.9 Port 3 (P33, P34) 91FY42-59 2006-11-08 TMP91FY42 Port 3 register 7 P3 (0007H) Bit symbol Read/Write After reset Function P37 6 P36 5 P35 4 P34 R/W 3 P33 2 P32 1 P31 1 0 P30 1 Data from external port (Output latch register is set to 1.) 0 (Output latch register) : Pull-up resistor OFF 1 (Output latch register): Pull-up resistor ON Port 3 Control register 7 P3CR (000AH) Bit symbol Read/Write After reset Function 0 P37C 6 P36C 0 0: Input 5 P35C W 0 4 P34C 0 1: Output 3 P33C 0 2 P32C 0 1 0 I/O setting 0 Input 1 Output Port 3 Function register 7 P3FC (000BH) Bit symbol Read/Write After reset Function 0 Always write "0" - 6 P36F W 0 0: Port 1: R/ W 5 P35F 0 0: Port 1: BUSAK 4 P34F 0 0: Port 1: BUSRQ 3 2 P32F 0 0: Port 1: HWR 1 P31F W 0 0: Port 1: WR 0 P30F 0 0: Port 1: RD P30 ( RD ) function setting 0 "0" output Always RD output (for pseudo SRAM 1 "1" output RD output only for external access P3FC BUSAK setting 1 0 0 1 P3FC 1 1 P31 ( WR ) function setting 0 "0" output access 1 "1" output 1 1 WR output only for external HWR setting P3FC 1 P3CR Figure 3.5.10 Register for Port 3 91FY42-60 2006-11-08 TMP91FY42 3.5.5 Port 4 (P40P43) Port 4 is a 4-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P4CR and function register P4FC. Resetting, set P40 to P43 of output register to "1", the control register P4CR and function register P4FC reset to "0" and sets port 4 to input mode with pull-up resistor. In addition to functioning as a general-purpose I/O port, port 4 can also function as chip select output signal ( CS0 to CS3 ). Reset Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write S Selector S Output latch A B P4 write S P40 ( CS0 ), Output buffer P41 ( CS1 ), P42 ( CS2 ), P43 ( CS3 ) Programmable P-ch pull up Internal data bus CS0 , CS1 , CS2 , CS3 B Selector P4 read A Figure 3.5.11 Port4 91FY42-61 2006-11-08 TMP91FY42 Port 4 Register 7 Bit symbol Read/Write P4 (000CH) After reset Function 6 5 4 3 P43 2 P42 R/W 1 P41 0 P40 Data from external port (Output latch register is set to "1") 0 (Output latch register): Pull-up resistor OFF 1 (Output latch register): Pull-up resistor ON Port 4 Control Register 7 P4CR (000EH) Bit symbol Read/Write After reset 0 0 0: Input 6 5 4 3 P43C 2 P42C W 1 P41C 0 1: Output 0 P40C 0 Input/Output setting 0 Input 1 Output Port 4 Function Register 7 P4FC (000FH) Bit symbol Read/Write After reset Function 0 0 6 5 4 3 P43F 2 P42F W 1 P41F 0 0 P40F 0 0: Port 1: CS 0 Port (P40) 1 CS0 0 Port (P41) 1 CS1 0 Port (P42) 1 CS2 0 Port (P43) 1 Note 1: Note 2: Read-modify-write instructions are prohibited for registers, P4CR and P4FC. When port 4 is used in Input mode, the P4 register controls the internal pull-up resistor. Read-modify-write instruction is prohibited in Input mode or I/O mode. Setting the internal pull-up resistor may be depend on the states of the input pin. Note 3: When output chip select signal ( CS0 to CS3 ), set bit of control register P4CR to "1" after set bit of function register P4FC to "1". Note 4: Output latch register is set to "1", and pull-up resistor is connected. CS3 Figure 3.5.12 Register for Port 4 91FY42-62 2006-11-08 TMP91FY42 3.5.6 Port 5 (P50 to P57) Port 5 is an 8-bit input port and can also be used as the analog input pin for the AD converter. P53 can also be used as AD trigger input pin for AD converter. Internal data bus Port 5 Port 5 read P50P57 (AN0AN7) Analog input ADTRG (P53 only) Figure 3.5.13 Port 5 Port 5 Register 7 P5 (000DH) Bit symbol Read/Write After reset P57 6 P56 5 P55 4 P54 R 3 P53 2 P52 1 P51 0 P50 Data from external port Figure 3.5.14 Register for Port 5 Note: The input channel selection of AD converter and the permission of AD trigger input of P53 set by AD converter mode register ADMOD1. 91FY42-63 2006-11-08 TMP91FY42 3.5.7 Port 6 (P60 to P66) Port 6 are 7-bit general-purpose I/O ports. Resetting set to input port. All bits of output latch register P6 are set to "1". In addition to functioning as an I/O port, port 6 can also function as input or output function of serial bus interface. This function enable each function by writing "1" to applicable bit of Port 6 function register P6FC. Resetting, P6CR and P6FC reset to "0", all bit set input port. (1) Port 60 (SCK) In addition to functioning as an I/O port, port 60 can also function as clock SCK I/O port in SIO mode of serial bus interface. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P6FC write S Output latch P6 write SCK output A S P60 (SCK) B SB Selector P6 read A SCK input Internal data bus Selector Figure 3.5.15 Port 60 91FY42-64 2006-11-08 TMP91FY42 (2) Port 61 (SO/SDA) In addition to functioning as an I/O port, port 61 can also function as data SDA I/O port in I2C mode or data SO output pin in SIO mode of serial bus interface. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P6FC write S Output latch P6 write SO output SDA output SB Selector P6 read SDA input A B Open-drain possible: ODE Internal data bus A S P61 (SO/SDA) Selector Figure 3.5.16 Port 61 91FY42-65 2006-11-08 TMP91FY42 (3) Port 62 (SI/SCL) In addition to functioning as an I/O port, port 62 can also function as data receiving pin in SIO mode or clock SCL I/O pin in I2C bus mode of serial bus interface. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P6FC write S Output latch P6 write SCL output B Internal data bus A S P62 (SI/SCL) Open-drain possible: ODE Selector Selector P6 read SI input SCL input A Figure 3.5.17 Port 62 91FY42-66 2006-11-08 TMP91FY42 (4) Port 63 (INT0) In addition to functioning as an I/O port, port 63 can also function as INT0 input pin of external interrupt. Reset Direction control (on bit basis) P6CR write Internal data bus Function control (on bit basis) P6FC write S Output latch P6 write SB Selector P6 read A Select level/edge & Select rising/falling IIMC INT0 Figure 3.5.18 Port 63 91FY42-67 2006-11-08 TMP91FY42 (5) Port 64 (SCOUT) In addition to functioning as an I/O port, port 64 can also function as SCOUT output pin for outputs internal clock. Reset Directin control (on bit basis) P6CR write Functin control Internal data bus (on bit basis) P6FC S Output latch P6 write S B Selector P6 read fs clock fFPH clock A Selector B S SYSCR2 A Figure 3.5.19 Port 64 (6) Port 65, 66 Port 65 and 66 functions as input or output ports. Reset Direction control (on bit basis) Internal data bus P6CR write S Output latch P6 write S B P65 P66 Selector P6 read A Figure 3.5.20 65, 66 91FY42-68 2006-11-08 TMP91FY42 Port 6 Registers 7 P6 (0012H) Bit symbol Read/Write After reset 6 P66 5 P65 4 P64 3 P63 R/W 2 P62 1 P61 0 P60 Data from external port (Output latch register is set to "1") Port 6 Control Register 7 P6CR (0014H) Bit symbol Read/Write After reset Function 0 0 0 0: Input 6 P66C 5 P65C 4 P64C 3 P63C W 0 1: Output 2 P62C 0 1 P61C 0 0 P60C 0 Port6 I/O setting 0 Input 1 Output Port 6 Function Register 7 P6FC (0015H) Bit symbol Read/Write After reset Function 0 0: Port 0 0: Port 6 5 4 P64F 3 P63F 2 P62F W 0 0: Port 1: SCL output 1 P61F 0 0: Port 1: SDA/SO output 0 P60F 0 0: Port 1: SCK output 1: SCOUT 1: INT0 output input P60 SCK output setting P6FC P61 SDA/SO output setting P6FC 1 1 1 0 P64 SCOUT output setting P6FC Note: Read-modify-write instructions are prohibited for registers P6CR and P6FC. 91FY42-69 2006-11-08 TMP91FY42 Open-drain Output Setting Register 7 ODE (002FH) Bit symbol Read/Write After reset Function 0 1:Open -drain 0 1:Open -drain 6 5 4 3 ODE62 2 ODE61 R/W 1 ODE93 0 1:Open -drain 0 ODE90 0 1:Open -drain 0: Tri-state 0: Tri-state 0: Tri-state 0: Tri-state Port61 Open-drain output 0 Tri-state output 1 Open-drain output Port62 Open-drain output 0 Tri-state output 1 Open-drain output Figure 3.5.21 Register for Port 6 91FY42-70 2006-11-08 TMP91FY42 3.5.8 Port 7 (P70 to P75) Port 7 is a 6-bit general-purpose I/O port. Resetting set to input port. In addition to functioning as a I/O port, port 70 and 73 can also function as clock input pin TA0IN, TA4IN of 8-bit timer 0, 4 and port 71, 72, 74 and 75 can also function 8-bit timer output pin TA1OUT, TA3OUT, TA5OUT and TA7OUT. This timer output function enable each function by writing "1" to applicable bit of Port 7 function register P7FC. Resetting, P7CR and P7FC reset to "0", all bit set input port. Reset Direction control (on bit basis) P7CR write S Output latch P7 write P7 read TA0IN TA4IN Internal data bus P70 (TA0IN) P73 (TA4IN) S B Selector A Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write S Output latch A P7 write Timer F/F OUT TA1OUT: TMRA01 TA3OUT: TMRA23 TA5OUT: TMRA45 TA7OUT: TMRA67 S P71 (TA1OUT) P72 (TA3OUT) P74 (TA5OUT) P75 (TA7OUT) Selector B B Selector P7 read SA Figure 3.5.22 Port 7 91FY42-71 2006-11-08 TMP91FY42 Port 7 Register 7 P7 (0013H) Bit symbol Read/Write After reset 6 5 P75 4 P74 3 P73 R/W 2 P72 1 P71 0 P70 Data from external port (Output latch register is set to "1".) Port 7 Control Register 7 P7CR (0016H) Bit symbol Read/Write After reset Function 0 0 0 0: Input 6 5 P75C 4 P74C 3 P73C W 2 P72C 0 1: Output 1 P71C 0 0 P70C 0 Port 7 I/O setting 0 Input 1 Output Port 7 Function Register 7 P7FC (0017H) Bit symbol Read/Write After reset Function 0 0: Port 1: TA7OUT 6 5 P75F W 4 P74F 0 0: Port 1: TA5OUT 3 2 P72F W 0 0: Port 1: TA3OUT 1 P71F 0 0: Port 1: TA1OUT 0 P71 timer out 1 output setting P7FC P72 timer out 3 output setting P7FC P74 timer out 5 output setting P7FC P75 timer out 7 output setting P7FC Note 1: Note 2: Read-Modify-Write instructions are prohibited for the registers P7CR and P7FC. P70/TA0IN and P73/TA4IN pin does not have a register changing Port/Function. For example, when it is used as an input port, the input signal is inputted to 8-bit timer. Figure 3.5.23 Register for Port 7 91FY42-72 2006-11-08 TMP91FY42 3.5.9 Port 8 (P80 to P87) Port 8 is an 8-bit general-purpose I/O port. Resetting set to input port. All bits of output latch register P8 are set to "1". In addition to functioning as an I/O port, port 8 can also function as clock input of 16-bit timer, output of 16-bit timer F/F and input function of INT5 to INT8. This function enable each function by writing "1" to applicable bit of port 8 function register P8FC. Resetting, P8CR and P8FC reset to "0", all bits set input port. (1) P80 to P87 Reset Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write S Output latch SB P8 write Selector Internal data bus TB0IN0, INT5 TB0IN1, INT6 TB1IN0, INT7 TB1IN1, INT8 P8 read Reset Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write S Output latch AS A P80 (TB0IN0/INT5) P81 (TB0IN1/INT6) P84 (TB1IN0/INT7) P85 (TB1N1/INT8) Selector B B Selector Timer F/F OUT TB0OUT0: TMRB0 TB0OUT1:TMRB0 TB1OUT0: TMRB1 TB1OUT1: TMRB1 P8 write P8 read SA P82 (TB0OUT0) P83 (TB0OUT1) P86 (TB1OUT0) P87 (TB1OUT1) Figure 3.5.24 Port 8 (P80 to P87) 91FY42-73 2006-11-08 TMP91FY42 Port 8 Register 7 P8 (0018H) Bit symbol Read/Write After reset P87 6 P86 5 P85 4 P84 R/W 3 P83 2 P82 1 P81 0 P80 Data from external port (Output latch register is set to "1".) Port 8 Control Register 7 P8CR (001AH) Bit symbol Read/Write After reset Function 0 0 0 0 0: Input P87C 6 P86C 5 P85C 4 P84C W 3 P83C 0 1: Output 2 P82C 0 1 P81C 0 0 P80C 0 Port 8 I/O setting 0 Input 1 Output Port 8 Function Register 7 P8FC (001BH) Bit symbol Read/Write After reset Function 0 0: Port 6 P86F 0 0: Port 5 P85F 0 0: Port INT8 input 4 P84F W 0 0: Port 1: TB1IN0 INT7 input 3 P83F 0 0: Port 2 P82F 0 0: Port 1 P81F 0 0: Port 0 P80F 0 0: Port P87F 1: TB1OUT1 1: TB1OUT0 1: TB1IN1 1: TB0IN0 1: TB0OUT1 1: TB0OUT0 1: TB0IN1 INT5 input INT6 input P82 TB0OUT0 output setting P8FC P83 TB0OUT1 output setting P8FC P86 TB1OUT0 output setting P8FC P87 TB1OUT1 output setting P8FC Note: Read-modify-write instructions are prohibited for registers P8CR and P8FC. Figure 3.5.25 Register for Port 8 91FY42-74 2006-11-08 TMP91FY42 3.5.10 Port 9 (P90 to P97) Ports 90 to 95 Ports 90 to 95 are a 6-bit general-purpose I/O port. Resetting set to input port. All bits of output latch register are set to "1". In addition to functioning as a I/O port, port 90 to 95 can also function as I/O of SIO0, SIO1. This function enable each function by writing "1" to applicable bit of port 9 function register P9FC. Resetting, P9CR and P9FC reset to "0", all bits set input port. Ports 96 to 97 Ports 96 to 97 are a 2-bit general-purpose I/O port. Case of output port, this is open drain output. Resetting, output latch register and control register set to "1", and set to "High-Z" (High impedance). In addition to functioning as a I/O port, ports 96 to 97 can also function as low-frequency oscilator connection pin (XT1 and XT2) during using low speed clock function. Therefore, dual clock function can use by setting of system clock control registers SYSCR0 and SYSCR1. (1) Ports 90 and 93 (TXD0 and TXD1) In addition to functioning as an I/O port, Ports 90 and 93 can also function as TXD output pin of serial channel. And P90 and P93 have a programmable open-drain function which can be controlled by the ODE Reset Direction control (on bit basis) P9CR write Internal data bus Function control (on bit basis) P9FC write S Output latch P9 write TXD0, A S P90 (TXD0) P93 (TXD1) Selector B SB Selector P9 read A Open-drain Possible ODE Figure 3.5.26 Ports 90 and 93 91FY42-75 2006-11-08 TMP91FY42 (2) Ports 91 and 94 (RXD0 and RXD1) In addition to functioning as an I/O port, ports 91 and 94 can also function as RXD input pin of serial channel. Reset Direction control (on bit basis) Internal data bus P9CR write S Output latch P9 write P9 read S B P91 (RXD0) P94 (RXD1) Selector A RXD0, Figure 3.5.27 Ports 91 and 94 (3) Ports 92 and 95 ( CTS0 /SCLK0, CTS1 /SCLK1) In addition to functioning as an I/O port, ports 92 and 95 can also function as CTS input pin or SCLK I/O pin of serial channel. Reset Direction control P9CR write Function control (on bit basis) P9FC write S Output latch P9 write SCLK0, 1 output A S P92 (SCLK0/ CTS0 ) P95 (SCLK1/ CTS1 ) Selector B Internal data bus SB Selector P9 read CTS0 , CTS1 A SCLK0, SCLK1 input Figure 3.5.28 Port 92, 95 91FY42-76 2006-11-08 TMP91FY42 (4) Ports 96 (XT1) and 97 (XT2) In addition to functioning as an I/O port, ports 96 and 97 can also function as low frequency oscillator connection pins. Reset S Direction control P9CR write S Output latch Output buffer (Open-drain output) Low-frequency oscillation enable P96 (XT1) P9 write S B Selector A P9 read Internal data bus (ON at 1) S Direction control (on bit basis) P9CR write S Output latch Output buffer P9 write S B Selector A P9 read (Open-drain output) Low-frequency clock P97 (XT2) Figure 3.5.29 Ports 96 and 97 91FY42-77 2006-11-08 TMP91FY42 Port 9 Registers 7 P9 (0019H) Bit symbol Read/Write After reset 1 1 P97 6 P96 5 P95 4 P94 R/W 3 P93 2 P92 1 P91 0 P90 Data from external port (Output latch register is set to "1".) Port 9 Control Register 7 P9CR (001CH) Bit symbol Read/Write After reset Function 1 1 0 0 0: Input P97C 6 P96C 5 P95C 4 P94C W 3 P93C 0 1: Output 2 P92C 0 1 P91C 0 0 P90C 0 Port9 I/O setting 0 Input 1 Note: Ports 96 and 97 are open-drain output pins. Output Port 9 Function Register P9FC (001DH) 7 Bit symbol Read/Write After reset Function 6 5 P95F W 0 0: Port 1: SCLK1 output 4 3 P93F W 0 0: Port 1: TXD1 2 P92F 0 0: Port 1: SCLK0 output 1 0 P90F W 0 0: Port 1: TXD0 P90 TXD0 output setting P9FC 1 1 1 1 1 1 1 1 91FY42-78 2006-11-08 TMP91FY42 Open-drain Output Setting Register 7 ODE (002FH) Bit symbol Read/Write After reset Function 0 1:Open -drain 0 1:Open -drain 6 5 4 3 ODE62 2 ODE61 R/W 1 ODE93 0 1:Open -drain 0 ODE90 0 1:Open -drain 0: Tri-state 0: Tri-state 0: Tri-state 0: Tri-state Port90 Open-drain output 0 Tri-state output 1 Open-drain output Port93 Open-drain output 0 Tri-state output 1 Open-drain output Figure 3.5.30 Register for Port 9 91FY42-79 2006-11-08 TMP91FY42 3.5.11 Port A (PA0PA7) Port A is an 8-bit general-purpose I/O port. I/Os can be set on a bit basis by control register PACR. After reset, PACR is reset to 0 and port A is set to an input port. Port A0 o A3 can also function as inputs for INT1 to INT4. Reset Direction control (on bit basis) PACR write Internal data bus S Output latch PA0PA3 (INT1INT4) PA write S B Selector A PA read INT1 INT4 Rising/Falling edge detection PAFC IIMC< I1EDGE, I2EDGE, I3EDGE, I4EDGE> Figure 3.5.31 Port A0A3 91FY42-80 2006-11-08 TMP91FY42 Reset R Direction contro (on bit basis) PACR write Internal data bus S Output latch PA4PA7 PA write B Selector A PA read S Figure 3.5.32 Port A4A7 91FY42-81 2006-11-08 TMP91FY42 Port A register 7 PA (001EH) Bit symbol Read/Write After reset PA7 6 PA6 5 PA5 4 PA4 R/W 3 PA3 2 PA2 1 PA1 0 PA0 Data from external port (Output latch register is set to "1") Port A control register 7 PACR (0020H) Bit symbol Read/Write After reset Function 0 PA7C 6 PA6C 0 5 PA5C 0 0: Input 4 PA4C W 0 3 PA3C 0 1: Output 2 PA2C 0 1 PA1C 0 0 PA0C 0 Port A function register 7 PAFC (0021H) Bit symbol Read/Write After reset Function 0 - 6 - 0 5 - 0 4 - W 0 3 PA3F 0 0: Port 1: INT4 input 2 PA2F 0 0: Port 1: INT3 input 1 PA2F 0 0: Port 1: INT2 input 0 PA0F 0 0: Port 1: INT1 input Always write "0" PA0 INT1 input setting PAFC PA1 INT2 input setting PAFC PA2 INT3 input setting PAFC PA3 INT4 input setting PAFC Note: Read-modify-write is prohibited for registers PACR and PAFC. Figure 3.5.33 Register for Port A 91FY42-82 2006-11-08 TMP91FY42 3.6 Chip Select/Wait Controller On the TM91FY42, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 and others). The pins CS0 to CS3 (which can also function as port pins P40 to P43) are the respective output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to be output, the port 4 function register P4FC must be set. TMP91FY42 supports connection of external ROM and SRAM. The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3. The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin controlling these states is the bus wait request pin ( WAIT ). 3.6.1 Specifying an Address Area The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to MSAR3) and memory address mask registers (MAMR0 to MAMR3). At each bus cycle, a compare operation is performed to determine if the address on the specified a location in the CS0 to CS3 area. If the result of the comparison is a match, this indicates an access to the corresponding CS area. In this case, the CS0 to CS3 pin outputs the chip select signal and the bus cycle operates in accordance with the settings in chip select/wait control register B0CS to B3CS. (See 3.6.2 "Chip Select/Wait Control Registers".) 91FY42-83 2006-11-08 TMP91FY42 (1) Memory start address registers Figure 3.6.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper 8 bits (A23 to A16) of the start address in Memory Start Address Registers (for areas CS0 to CS3) 7 MSAR0 (00C8H) MSAR2 (00CCH) MSAR1 Bit symbol (00CAH) Read/Write MSAR3 After reset (00CEH) Function S23 1 6 S22 1 5 S21 1 4 S20 R/W 1 3 S19 1 2 S18 1 1 S17 1 0 S16 1 Determines A23 to A16 of start address. Sets start addresses for areas CS0 to CS3. Figure 3.6.1 Memory Start Address Register Address 000000H 64 Kbytes Start address Value in start address register (MSAR0 to MSAR3) 000000H ...................... 00H 010000H ...................... 01H 020000H ...................... 02H 030000H ...................... 03H 040000H ...................... 04H 050000H ...................... 05H 060000H ...................... 06H to to FFFFFFH FF0000H ...................... FFH Figure 3.6.2 Relationship between Start Address and Start Address Register Value 91FY42-84 2006-11-08 TMP91FY42 (2) Memory address mask registers Figure 3.6.3 shows the memory address mask registers. Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set in memory start address registers MAMR0 to MAMR3. The compare operation used to determine if an address is in the CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to 0 in these registers. Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0 to CS3 areas. Accordingly, the size that can be each area is different. Memory Address Mask Register (for CS0 area) 7 MAMR0 (00C9H) Bit symbol Read/Write After reset Function 1 1 1 1 Sets size of CS0 area V20 6 V19 5 V18 4 V17 R/W 3 V16 1 2 V15 1 1 V14 to V9 1 0 V8 1 0: Used for address compare Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes Memory Address Mask Register (CS1) 7 MAMR1 (00CBH) Bit symbol Read/Write After reset Function 1 1 1 1 Sets size of CS1 area V21 6 V20 5 V19 4 V18 R/W 3 V17 1 2 V16 1 1 V15 to V9 1 0 V8 1 0: Used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2, CS3) 7 MAMR2 (00CDH) MAMR3 Bit symbol (00CFH) Read/Write After reset Function V22 1 6 V21 1 5 V20 1 4 V19 R/W 1 3 V18 1 2 V17 1 1 V16 1 0 V15 1 Sets size of CS2 or CS3 area 0: Used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.6.3 Memory Address Mask Registers 91FY42-85 2006-11-08 TMP91FY42 (3) Setting memory start addresses and address areas Figure 3.6.4 show an example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas. Set 01H in memory start address register MSAR0 0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H Memory end address CS0 area size (64 Kbytes) H Memory start address V14 to V9 V8 S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0 0 0 0 0 0 0 1 0 1 V20 V19 V18 V17 V16 V15 MSMR0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 1 1 1 1 H 1 1 1 1 1 1 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.6.4 Example Showing How to Set the CS0 Area After a reset, MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to FFH. B0CS 91FY42-86 2006-11-08 TMP91FY42 (4) Address area size specification Table 3.6.1 shows the relationship between CS area and area size. "" indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using a combination indicated by "", set the start address mask register in the desired steps starting from 000000H. If the CS2 area is set to 16-Mbytes or if two or more areas overlap, the smaller CS area number has the higher priority. Example: To set the area size for CS0 to 128 Kbytes: a. Valid start addresses 000000H 020000H 040000H 060000H 128 Kbytes 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. b. Invalid start addresses 000000H 010000H 030000H 050000H 64 Kbytes 128 Kbytes 128 Kbytes This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address. Table 3.6.1 Valid Area Sizes for Each CS Area Size (Bytes) 256 CS Area CS0 CS1 CS2 CS3 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M Note: "" indicates areas that cannot be set by memory start address register and address mask register combinations. 91FY42-87 2006-11-08 TMP91FY42 3.6.2 Chip Select/Wait Control Registers Figure 3.6.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 and others) are set in their respective chip select/wait control registers, B0CS to B3CS and BEXCS. 91FY42-88 2006-11-08 TMP91FY42 7 B0CS (00C0H) Readmodifywrite instructions are prohibited. 6 5 B0OM1 0 4 B0OM0 0 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits 2 B0W2 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 1 B0W1 0 0 B0W0 0 100: Reserved 101: 3 waits 111: 8 waits Bit symbol Read/Write After reset Function B0E W 0 0: Disable 1: Enable Chip select output waveform selection 00: For ROM/SRAM 01: 10: 11: Don't care B1OM0 0 010: (1 + N) waits 110: 4 waits B1CS (00C1H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Function B1E W 0 0: Disable 1: Enable B1OM1 0 B1BUS W 0 Data bus width 0: 16 bits 1: 8 bits B1W2 0 B1W1 0 B1W0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: 11: Don't care B2OM0 W 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 100: Reserved 101: 3 waits 111: 8 waits B2W1 0 B2W0 0 100: Reserved 101: 3 waits 111: 8 waits B3W1 0 B3W0 0 100: Reserved 101: 3 waits 111: 8 waits BEXW1 W 0 BEXW0 0 100: Reserved 101: 3 waits 111: 8 waits 010: (1 + N) waits 110: 4 waits B2CS (00C2H) Bit symbol Read/Write After reset B2E 1 0: Disable 1: Enable B2M 0 CS2 area selection area 1: CS area B2OM1 0 B2BUS 0 Data bus width 0: 16 bits 1: 8 bits B2W2 0 Readmodifywrite instructions are prohibited. Functions Chip select output waveform selection 01: 10: 11: B3OM1 0 Don't care B3OM0 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 0: 16-Mbyte 00: For ROM/SRAM 010: (1 + N) waits 110: 4 waits B3CS (00C3H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Functions B3E W 0 0: Disable 1: Enable B3BUS W 0 Data bus width 0: 16 bits 1: 8 bits B3W2 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: 11: Don't care Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 010: (1 + N) waits 110: 4 waits BEXCS (00C7H) Bit symbol Read/Write After reset BEXBUS 0 Data bus width 0: 16 bits 1: 8 bits BEXW2 0 Readmodifywrite instructions are prohibited. Functions Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 010: (1 + N) waits 110: 4 waits Master enable bit 0 1 Enable Disable Chip select output waveform selection 00 For ROM/SRAM 01 10 Don't care 11 Number of address area waits (See 3.6.2, (3) Wait control.) Data bus width selection 0 1 16-bit data bus 8-bit data bus CS2 area selection 0 1 16-Mbyte area Specified address area Figure 3.6.5 Chip Select/Wait Control Registers 91FY42-89 2006-11-08 TMP91FY42 (1) Master enable bits Bit 7 ( Table 3.6.2 Dynamic Bus Sizing Operand Data Operand Start Memory Data Bus Width Address Bus Width 8 bits 2n + 0 (Even number) 2n + 1 (Odd number) 16 bits 2n + 0 (Even number) 16 bits 2n + 1 (Odd number) 16 bits 32 bits 2n + 0 (Even number) 8 bits 8 bits 8 bits 16 bits 8 bits 16 bits 8 bits CPU Address 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 CPU Data D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 16 bits 2n + 1 (Odd number) 8 bits 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 16 bits 2n + 1 2n + 2 2n + 4 Note: xxxxx indicates that the input data from these bits are ignored during a read. During a write, indicates that the bus for these bits goes too high impedance; also, that the write strobe signal for the bus remains inactive. 91FY42-90 2006-11-08 TMP91FY42 (3) Wait control Bits 0 to 2 ( Table 3.6.3 Wait Operation Settings 000 001 010 Number of Waits 2 1 (1 + N) Wait Operation Inserts a wait of 2 states, irrespective of the WAIT pin state. Inserts a wait of 1 state, irrespective of the WAIT pin state. Samples the state of the WAIT pin after inserting a wait of 1 state. If the WAIT pin is low, the waits continue and the bus cycle is extended until the pin goes high. 011 100 101 110 111 0 Reserved 3 4 8 Ends the bus cycle without a wait, regardless of the WAIT pin state. Invalid setting Inserts a wait of 3 states, irrespective of the WAIT pin state. Inserts a wait of 4 states, irrespective of the WAIT pin state. Inserts a wait of 8 states, irrespective of the WAIT pin state. A reset sets these bits to 000 (2 waits). (4) Bus width and wait control for an area other than CS0 to CS3 The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Setting B2CS 91FY42-91 2006-11-08 TMP91FY42 (6) Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: 1. 2. 3. Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. Set the memory address mask registers MAMR0 to MAMR3. Set the sizes of CS0 to CS3. Set the chip select/wait control registers B0CS to B3CS. Set the chip select output waveform, data bus width, number of waits and master enable/disable status for CS0 to CS3 . The CS0 to CS3 pins can also function as pins P40 to P43. To output a chip select signal using one of these pins, set the corresponding bit in the port 4 function register P6FC to 1. If a CS0 to CS3 address is specified which is actually an internal I/O and RAM area address, the CPU accesses the internal address area and no chip select signal is output on any of the CS0 to CS3 pins. Setting example: In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is set to 0. MSAR0 = 01H MAMR0 = 07H B0CS = 83H Start address: 010000H Address area: 64 Kbytes ROM/SRAM, 16-bit data bus, 0 waits, CS0 area settings enabled. 91FY42-92 2006-11-08 TMP91FY42 3.6.3 Connecting External Memory Figure 3.6.6 shows an example of how to connect external memory to the TMP91FY42. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. 74AC573 TMP91FY42 D Q Address bus CS CS Upper byte ROM Lower byte ROM LE CS0 CS1 CS2 CS 8 bit width RAM CS 8 bit width I/O D Q OE ALE AD8 AD15 AD0 AD7 RD WR LE OE OE WE OE WE Figure 3.6.6 Example of External Memory Connection (ROM uses 16-bit bus; RAM and I/O use 8-bit bus.) A reset clears all bits of the port 4 control register P4CR and the port 4 function register P4FC to 0 and disables output of the CS signal. To output the CS signal, the appropriate bit must be set to 1. 91FY42-93 2006-11-08 TMP91FY42 3.7 8-Bit Timers (TMRA) The TMP91FY42 features 8 channel (TMRA0 to TMRA7) built-in 8-bit timers. These timers are paired into 4 modules: TMRA01, TMRA23, TMRA45 and TMRA67. Each module consists of 8 channels and can operate in any of the following 4 operating modes. * * * * 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant period) Figure 3.7.1 to Figure 3.7.3 show block diagrams for TMRA01, TMRA23, TMRA45 and TMRA67. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flop condition are controlled by 5-byte registers. We call control registers SFRs: Special function registers. Each of the four modules (TMRA01, TMRA23, TMRA45 and TMRA67) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter are as follows. 3.7.1 Block Diagrams 3.7.2 Operation of Each Circuit 3.7.3 SFRs 3.7.4 Operation in Each Mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (Programmable pulse generation) output mode (4) 8-bit PWM (Pulse width modulation) output mode (5) Settings for each mode Table 3.7.1 Registers and Pins for Each Module Module Input pin for External pin external clock Output pin for timer flip-flop Timer run register Timer register SFR (Address) Timer mode register Timer flip-flop control register TMRA01 TA0IN (shared with P70) TA1OUT (shared with P71) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TMRA23 None TA3OUT (shared with P72) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) TMRA45 TA4IN (shared with P73) TA5OUT (shared with P74) TA45RUN (0110H) TA4REG (0112H) TA5REG (0113H) TA45MOD (0114H) TA5FFCR (0115H) TMRA67 None TA7OUT (shared with P75) TA67RUN (0118H) TA6REG (011AH) TA7REG (011BH) TA67MOD (011CH) TA7FFCR (011DH) 91FY42-94 2006-11-08 3.7.1 Prescaler 2 T1 Timer Timer flip-flop output: TA1OUT flip-flop TA1FF Selector 8-bit up counter (UC0) 8-bit up counter (UC1) 2n Overflow Prescaler clock: T0 4 T4 T16 T256 8 16 32 64 128 256 512 Block Diagrams Run/clear TA01RUN TA01RUN External input clock: TA0IN TA1FFCR Figure 3.7.1 TMRA01 Block Diagram 91FY42-95 8-bit comparator (CP0) TA01MOD Match 8-bit comparator detect (CP1) 8-bit timer Internal bus TMRA1 interrupt output: INTTA1 TMP91FY42 2006-11-08 Prescaler 2 T1 T4 T16 T256 Timer flip-flop TA3FF Selector 8-bit up counter (UC2) 2 Overflow TA23MOD n Prescaler clock: T0 4 8 16 32 64 128 256 512 TA23RUN Run/clear TA23RUN TA23RUN Timer flip-flop output: TA3OUT Figure 3.7.2 TMRA23 Block Diagram 91FY42-96 8-bit comparator detect (CP2) Match TA2TRG TA23MOD Match 8-bit comparator detect (CP3) 8-bit timer register TA2REG 8-bit timer register TA3REG Register buffer 2 TA23RUN TMP91FY42 Internal bus TMRA2 interrupt output: INTTA2 TMRA2 match output: TA2TRG Internal bus TMRA3 interrup output: INTTA3 2006-11-08 Prescaler 2 T1 T4 T16 T256 Timer flip-flop TA5FF Selector 8-bit up counter (UC4) 2 Overflow TA45MOD n Prescaler clock: T0 4 8 16 32 64 128 256 512 TA45RUN Run/clear TA45RUN TA45RUN Timer flip-flop output: TA5OUT Figure 3.7.3 TMRA45 Block Diagram 91FY42-97 8-bit comparator detect (CP4) Match TA4TRG TA45MOD Match 8-bit comparator detect (CP5) 8-bit timer register TA4REG 8-bit timer register TA5REG Register buffer 2 TA45RUN Internal bus TMRA4 interrupt output: INTTA4 TMRA4 match output: TA4TRG Internal bus TMRA5 interrup output: INTTA5 TMP91FY42 2006-11-08 Prescaler 2 T1 T4 T16 T256 Timer flip-flop TA7FF Selector 8-bit up counter (UC6) 2 Overflow TA67MOD n Prescaler clock: T0 4 8 16 32 64 128 256 512 TA67RUN Run/clear TA67RUN TA67RUN |