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STA2058
Teseo GPS Platform high-sensitivity baseband
Data Brief
Features

Single chip baseband with embedded flash Complete embedded memory system: - FLASH 256K+16K bytes - RAM 64K bytes 66-MHz ARM7TDMI 32 bit processor High Performance GPS engine (HPGPS) SBAS (WAAS and EGNOS) supported Sensitivity (-146dBm Acquisition, -159dBm Tracking) Time to first Fix (1s reacquisition, 2.5s Hot Start, 34s Warm Start, 39s Cold Start) Accuracy (2m Autonomous) External Memory Interface (EMI) supporting up to 64Mbite of external SRAM, FLASH and ROM Extensive GPS Receiver Interfaces: 48 GPIOs, 4 UARTs, 2 SPIs, 2 I2Cs, 2 CANs 2.0, 1 USB 1.1,1 HDLC and 4 channels ADC ST proprietary Flash embedded technology LFBGA144 and LQFP64 lead-free package -40C to 85C operating temperature range
LFBGA144 LQFP64

Description
STA2058 is the high-sensitivity baseband of Teseo GPS Platform which include the STA5620 RF Front-End. The embedded flash memory enables the equipment manufacturer to load the entire GPS software (including tracking, acquisition, navigation and data output) after customizing its interfaces to his needs. A standard GPS library is available from ST. Teseo is the ideal solution for consumer, Handheld, PND (Portable Navigation), in vehicle Navigation and Telematics systems. SBAS (WAAS and EGNOS) feature are also supported.

Evaluation kits

STA2058 module reference design (25x25mm) Evaluation board hosting STA2058 module SDK board (for application SW development)
Table 1.
Device summary
Device selection features Description GPS Baseband GPS Baseband Package LFBGA144 LQFP64 Body size GPIOs CAN 2 1 EMI Available Not available 10x10mm 10x10mm 48 32
Order codes STA2058EX STA2058
June 2007
Rev 2
1/20
www.st.com 20
For further information contact your local STMicroelectronics sales office.
Contents
STA2058
Contents
1 2 Features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 3.2 3.3 Package LFBGA144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 4.2 4.3 4.5 4.6 4.7 4.8 4.9 DC electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 nRSTIN input filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ADC Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 GPS performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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STA2058
Features summary
1
Features summary

ARM7TDMI 16/32 bit RISC CPU based host microcontroller running at a frequency up to 66 MHz. Complete Embedded Memory System: - - FLASH 256K bytes + 16K bytes (100K erasing/programming cycles) RAM 64K bytes.

External memory interface provides glueless support for up to four banks of external SRAM, FLASH, ROM. High Performance GPS engine (HPGPS). ST Proprietary CMOS (0.18 m) Flash Embedded technology. SBAS (WAAS and EGNOS) supported -40C to 85C operating temperature range. 144-pin LFBGA package and 64-pin LQFP package Power Supply: - - - 3.0V to 3.6V operating supply range for Input/Output periphery 3.0V to 3.6V operating supply range for A/D Converter reference 1.8V operating supply range for core supply provided either by internal Voltage Regulator (with external stabilization capacitor) or by external supply voltage.
Reset and Clock Control Unit able to provide low power modes (WAIT, SLOW, STOP, STANDBY) and to generate the internal clock from the external reference through integrated PLL. 48 programmable General Purpose I/O, each pin programmable independently as digital input or digital output; 40 (30 in LQFP64) are multiplexed with peripheral functions; 16 can generate an interrupt on input level/transition. Real time clock module with 32khz low power oscillator and separate power supply to continue running during stand-by mode. 16-bit Watchdog Timer with 8 bits prescaler for system reliability and integrity. 2 CAN modules compliant with the CAN specification V2.0 part B (active) and bit rate can be programmed up to 1 MBaud.One additional CAN at 1Mbps (for STA2058 EM SIP version) Four 16-bit programmable Timers with 7 bit prescaler, up to two input capture/output compare, one pulse counter function, one PWM channel with selectable frequency each. 4 channels 12-bit sigma-delta Analog to Digital Converter, single channel or multi channel conversion modes, single-shot or continuous conversion modes, sample rate 1 KHz, conversion range 0-2.5V. Three Serial Communication Interfaces (UART) allow full duplex, asynchronous, communications with external devices, independently programmable TX and RX baud rates up to 625K baud. One UART adapted to suit Smart Card interface needs, for asynchronous SC as defined by ISO 7816-3. It includes SC clock generation. Two Serial Peripheral Interfaces (SPI) allow full duplex, synchronous communications with external devices, master or slave operation, max baud rate of 5.5Mb/s. One SPI may be used as Multimedia Card interface.

3/20
Features summary
STA2058
Two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 KHz), 7/10 bit addressing modes. One I2C Interface is multiplexed with one SPI, so either 2 x SPI + 1 x I2C or 1 x SPI + 2 x I2C may be used at a time. Enhanced Interrupt Controller supports 32 interrupt vectors, independently maskable, with interrupt vector table for faster response and 16 priority levels, software programmable for each source. Up to 2 maskable interrupts may be mapped on FIQ. Wake-up unit allows exiting from power down modes by detection of an event on two external pins (one is active high and other is active low) or on internal Real Time Clock alarm. USB unit V1.1 compliant, software configurable endpoint setting, USB Suspend/Resume support High Level Data Link Controller (HDLC) unit supports full duplex operating mode, NRZ, NRZI, FM0 and MANCHESTER modes, and internal 8-bit Baud Rate Generator.

4/20
STA2058
Pin description
2
2.1
Pin description
Logic symbol
Figure 1. STA2058 Teseo symbol
V18 (2) V33 (7) Power Pads VSS (10) AVSS AVDD V18BKP GPSCLK Clock & Reset CK CKOUT RSTINn A[23:0] D[15:0] WEn.[1:0] CSn.[3:0] RDn P0.[15:0] EMI Interface LFBGA144 ONLY
STA2058 TESEO
P1.[15:0] P2.[15:0] (LFBGA144 Only) nSTDBY_I nSTDBY_O RTCXTO RTCXTI WAKEUP nWAKEUP USBDN USBDP
GeneraI Purpose I/O
JTAG Port
JTDI JTCK JTMS JTRSTn JTDO
RTC & WKUP Pads
Debug
DBGRQS BOOTEN
USB Pads
GPSDAT[1] LFBGA144 Only GPSDAT[0]
5/20
System block diagram
STA2058
3
System block diagram
Figure 2. STA2058 Teseo block diagram
1 DP ARM7TDMI CPU 256K FLASH 64K RAM 5 DP STC(JTAG) ARM7 Native BUS
EMI
39 DP + 8 AF
APB BRIDGE3
HPGPS 16-ch. correlator + Emerald DSP
3 DP
APB BRIDGE1 APB BRIDGE2
3 DP 5 DP
VREG
RCCU
PLL
I2C0
2 AF
Interrupt Contr. 4 AF 12-bit A/D Converter
I2C1
2 AF
SPI0 APB BUS APB BUS
4 AF
SPI1
4 AF
TIMER0 TIMER1
UART0
2 AF
4 AF 2 AF 4 AF
TIMER2 TIMER3
UART1
2 AF
UART2
2 AF
RTC 2 DP 16 AF 2 AF OSCILL
UART3
2 AF
[USB] Wakeup [CAN0]
WATCHDOG
3 DP
2 AF
[CAN1] 48 IO Fully Prog. I/O
2 AF 3 AF
HDLC
6/20
STA2058 Figure 3. New HPGPS 16-ch including Emerald DSP 16-bit
System block diagram
PRAM
pbus
ybus
EMERALD
XBAR
ybus xbus
4
xbus
INT
XRAM
pbus
YRAM
Acquisition Output Data APB
INT Register Interface ISR AA DA RWA CSA AB DB RWB CSB 1023x32 RAM B1 1023x32 RAM A1
APB bus
3
ARM
HPGPS IP
HPGPS_EME top
2046x32bit RAM (*)
(*) Maximum memory size addressable by HPGPS. The real value depends on the device specs
1023x32 RAM B0
1023x32 RAM A0
INT
7/20
System block diagram
STA2058
3.1
Table 2.
A 1
P0.10/ U1.RX/ U1.TX VSS
Package LFBGA144
Ball out for LFBGA144 Package
B
P2.0/ CSn.0
C
P2.1/ CSn.1 P0.11/ U1.TX/ BOOT.1 P0.12/ SCCLK
D
VSS
E
P2.2/ CSn.2 P2.3/ CSn.3
F
P2.6/ A.22
G
BOOTEN
H
P2.12
J
P2.13
K
P2.15
L
JTDI
M
NC
2
RDN
V33 P0.13/ U2.RX/ T2.OCMP A
P2.8
P2.9/ CAN1_TX
JTMS
JTRSTn
GPSCLK GPSDAT1
V33REG_B KP
3
V33
P0.9/ U0.TX/ BOOT.0 P0.7/ S1.SSN WEn.1
P2.4/ A.20
NC
P2.10/ CAN1_RX
JTCK
GPSDAT0
V33
VSSREG
DBGRQS
4 5 6
P0.6/ S1.SCLK A.19 P0.3/ S0.SSN/ I1.SDA
P0.8/ P0.14/ U0.RX/U0. U2.TX/ TX T2.ICAPA WEn.0 P0.5/ S1.MOSI A.17
P2.5/ A.21 P2.7/ A.23 A.18
VSS
P2.11
JTDO
CK
CKOUT
VSS WAKEUP_ PA
VSS P0.15/ WAKEUP
VSS
P2.14
NC
RTCXTO
RTCXTI
A.15
A.16
V33
V18
V18
V18BKP
V18BKP
VSSBKP nSTDBY_IN
7
P0.2/ P0.1/ S0.SCLK/ S0.MOSI/ I1.SCL U3.RX A.9 A.10
P0.4/ S1.MISO
VSS
V18 P0.0/ S0.MISO/ U3.TX
A.14
D.12
D.1
D.0
nSTDBY_ O
VSS18
RSTINn
8
A.11
A.13
A.0
D.11
P1.12/ CANTX
AVSS
AVSS P1.0/ T3.OCMP B/ AIN.0
D.3
D.2
9
VSS18
V33
A.5
A.6
V33
D.15
D.10
P1.8/ PPS P1.7/ T1.OCMP B VSSIOPLL
D.9
NC
AVDD
10
A.8
V33
P1.15/ HTXD P1.14/ HRXD/ I0.SDA A.3
P1.13/ HCLK/ I0.SCL P1.10/ USBCLK P1.9/ PRN.11
VSS
D.14
USBDN
D.8
P1.1/ P1.5/ T3.ICAPA/ T1.ICAPB AIN.1 P1.3/ P1.4/ T3.ICAPB/ T1.ICAPA AIN.3 D.7 D.6
D.4
11
A.7
NC
A.2
D.13
USBDP
D.5
AVDD P1.2/ T3.OCMPA/ AIN.2
12
A.12
A.4
A.1
P1.11/ CANRX
NC
V33IO-PLL
P1.6/ T1.OCMPA
8/20
STA2058
System block diagram
3.2
LQFP64 package
Figure 4. LQFP64 Package Outline
P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD P0.10/U1.RX/U1.TX P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST GPSDAT GPSCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Teseo LQFP64
P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9/PRN.11 VSS P1.12/CANTX/USBDN P1.11/CANRX/USBDP P1.8/PPS P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2
V33REG_BKP VSSREG CK P0.15/WAKEUP RTCXTI RTCXTO nSTDBY_IN nRSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Remapped for bkp supply Double bond bw CAN & USB Pads
9/20
System block diagram
STA2058
3.3
Power supply pins
Table 3.
Symbol V33 VSS V33IO-PLL VSSIO-PLL V33REG_B
KP
Power supply pins
I/O Function Digital Supply Voltage for I/O circuitry (3.3 Volt) Digital Ground for I/O circuitry Digital Supply Voltage for I/O circuitry and for PLL reference (3.3V) Digital Ground for I/O circuitry and for PLL reference Digital Supply Voltage for backup block I/O circuitry and for Ballast I/O (3.3V) Digital Ground for Ballast I/O Digital Supply Voltage for core circuitry (1.8 Volt): When using the Internal Voltage Regulator, this pin shall not be driven by an external voltage supply, but a capacitance of at least 10F (Tantalum, low series resistance) + 33nF (ceramic) shall be connected between these pins and VSS18 to guarantee on-chip voltage stability. Digital Ground for core circuitry Digital Supply Voltage for Backup block (RTC, oscillator, Wake-up controller - 1.8 Volt): when using the Internal Voltage Regulator, this pin shall not be driven by an external voltage supply, but a capacitance of at least 1F shall be connected between this pin and VSSBKP to guarantee on-chip voltage stability. Digital Ground for Backup logic Analog Supply Voltage for the A/D Converter Analog Supply Ground for the A/D Converter LQFP 64 9, 51 4, 8, 44, 50, 59 38 39 17 18 LFBGA 144 D2,A3,K3,F6,B9 , E9,B10 D1,A2,F4,L4,M 4, F5, D7,E10 H12 H11 M2 L3
VSSREG
V18
-
27, 58
G6, H6,E7
VSS18
-
28, 57
A9,L7
V18BKP
-
26
J6,K6
VSSBKP AVDD AVSS
-
25 29 30
L6 M9, M11 J8,K8
Note:
V33 and V33IO-PLL are all internally connected. Same for VSS and VSSIO-PLL. All VSS, VSS18, VSSBKP, AVSS pins must be tied together to the common ground plane, taking care of noise filtering, especially on AVSS
10/20
STA2058
Electrical characteristic
4
4.1
Table 4.
Symbol
Electrical characteristic
DC electrical characteristic
V33 = 3.3V 10%, TA = -40 / 85 C unless otherwise specified. DC electrical characteristic
Value Parameter Input High Level CMOS VIH Input High Level Input Low Level CMOS VIL Input Low Level Input Hysteresis CMOS Schmitt Trigger VHYS Input Hysteresis Schmitt Trigger Output High Level High Current Pins VOH Output High Level Standard Current Pins Output Low Level Standard Current Pins Weak Pull-Up Resistor Weak Pull-Down Resistor P0.15 (WAKEUP) only Push Pull, IOH= 8mA Push Pull, IOH= 4mA Push Pull, IOH= 8mA Push Pull, IOH= 4mA Measured at 0.5V33 Measured at 0.5V33 100 100 Test conditions Min. With or w/o hysteresis P0.15 (WAKEUP) only With or w/o hysteresis P0.15 (WAKEUP) only 0.4 0.3 V33-0.8 V33-0.8 0.4 0.4 V V k k 0.8 0.5 0.7V33 1.8 0.3V33 0.7 1.2 Typ. Max. Unit V V V V V V
VOL RWPU RWPD
11/20
Electrical characteristic
STA2058
4.2
Table 5.
AC electrical characteristics
AC electrical characteristics V33 = 3.3V 10%, TA = 27 C unless otherwise specified.
Value Mode RUN mode WFI mode LPWFI mode STOP mode STANDBY_1 mode STANDBY_0 mode System Clock Min. IDDRUN IDDWFI IDDLP IDDSTP IDDSB1 IDDSB0 33MHz System Clock 1MHz System Clock 32khz System Clock Main VReg off, Flash in Power-Down LP VReg and 32kHz Osc on LP VReg, LVD, 32kHz Osc bypassed Typ. 60 5 300 200 15 3 30 10 Max. mA mA A A A A Unit
Symbol
Note:
IDDRUN is the consumption in applications exploiting the full performances of the core. A typical GPS application would run at 33MHz, at the maximum frequency (66MHz) the power consumption is IDDRUN = 150 mA (typ). In WFI mode the VReg and Flash are ON to guarantees the minimum interrupt response time.
Table 6.
AC electrical characteristics V33 = 3.3V 10%, TA = -40 / 85 C unless otherwise specified.
Value Mode CPU max frequency System Clock Min. Typ. Max. 66 60 MHz MHz Executing from RAM or EMI Unit
Symbol FCPU FMAX
Flash max frequency Executing from Flash
4.3
Table 7.
Symbol tFR tNFR
nRSTIN input filter characteristics
V33=3.3V 10%, TA = -40 / 85 C unless otherwise specified. nRSTIN input filter characteristics
Value Mode nRSTIN input filtered pulse nRSTIN input not filtered pulse 1.2 System Clock Min. Typ. Max. 100 ns s Unit
12/20
STA2058
Electrical characteristic
4.4
Table 8.
Symbol tPW tPDW tPB0 tPB1 tES tES tES tES tRPD tPSL tESL
Flash electrical characteristics
V33=3.3 10%, TA = -40 / 85 C unless otherwise specified.
Flash program/erase characteristics 1
Value Parameter Word program Double word program Bank 0 program (256K) Bank 1 program (16K) Sector erase (64K) Sector erase (8K) Bank 0 erase (256K) Bank 1 erase (16K) Recovery from power-down Program suspend latency Erase suspend latency Double Word Program Double Word Program Not preprogrammed Preprogrammed Not preprogrammed Preprogrammed Not preprogrammed Preprogrammed Not preprogrammed Preprogrammed Test Conditions Typ 40 60 1.6 130 2.3 1.9 0.7 0.6 8.0 6.6 0.9 0.8 2.1 170 4.0 3.3 1.1 1.0 13.7 11.2 1.5 1.3 4.3 300 4.9 4.1 1.36 1.26 17.2 14.0 1.87 1.66 20 10 300 Max (C0) Max (Cmax) s s s ms s s s s s s s Unit
Note:
C0: TA = 85 C after 0 cycles Cmax: TA = 85 C after max number of cycles Flash program/erase characteristics 2
Value Parameter Endurance Endurance (Bank1 sectors) Data retention Conditions Min 10 100 20 Min time from erase resume to next erase suspend 20 Typ Max Kcycles Kcycles Years ms Unit
Table 9.
Symbol
tESR
Erase suspend rate
13/20
Electrical characteristic
STA2058
4.5
Oscillator electrical characteristics
V33=3.3 10%, TA = -40 / 85 C unless otherwise specified. Figure 5. Crystal oscillator and resonator
RTCXTO
RS CL CL
Table 10.
Symbol gm tSTUP
Oscillator electrical characteristics
Value Parameter Oscillator transconductance Oscillator start-up time Stable VDD Test Conditions Min Typ 8 2.5 Max A/V s Unit
4.6
Table 11.
Symbol
ADC electrical characteristics
V33 = 3.3 10%, AVDD = 3.3V 10%, TA = -40 / 85 C unless otherwise specified. ADC electrical characteristics
Value Parameter Test Conditions Min Typ 12 0 2.5 2.1 FMod/40 96 4 0.1 56 60 63 74 Max bits V MHz kHz n dB dB dB Sinewave with VIN amplitude Unit
RES VIN FMod IBW Nch PBR SINAD THD
Resolution Input voltage range Modulator oversampling frequency Input bandwidth Number of input channels Passband ripple S/N and distortion Total harmonic distortion
14/20
RTCXTO
RTCXTI
RTCXTI
DEVICE
DEVICE
STA2058 Table 11.
Symbol ZIN CIN IADC ISTBY
Electrical characteristic ADC electrical characteristics (continued)
Value Parameter Input impedance Input capacitance Power consumption Standby power consumption TA=27 C TA=27 C 2.5 Test Conditions Min FMod = 2 MHz 1 5 3.0 1 Typ Max M pF mA A Unit
4.7
Table 12.
Symbol TPLL1 TPLL2 TPLL3
PLL electrical characteristics
V33=3.3 10%, V33IOPLL=3.3 10%, TA = -40 / 85 C unless otherwise specified. PLL electrical characteristics
Value Parameter PLL reference clock PLL reference clock PLL reference clock Test Conditions Min FREF_RANGE=0 FREF_RANGE=1 MX[1:0]='00' or `01' FREF_RANGE=1 MX[1:0]='10' or `11' FREF_RANGE=0 Stable Input Clock Stable V33IOPLL, V18 FREF_RANGE=1 Stable Input Clock Stable V33IOPLL, V18 TPLL = 4 MHz, MX[1:0]='11' Global Output division=32 (Output Clock=2 MHz) 0.7 1.5 3.0 3.0 Typ Max 3.0 8.25 6 MHz MHz MHz Unit
TLOCK
PLL lock time
300
s
TLOCK
PLL lock time
600
s
TJITTER PLL jitter (peak to peak)
2
ns
4.8
Table 13.
Symbol TLVD V
LVD electrical characteristics
V33=3.3 10%, TA = -40 / 85 C unless otherwise specified. LVD electrical characteristics
Value Parameter LVD Threshold VLPREG - TLVD Test Conditions Min Main and LP LVD's Main regulator off 50 Typ 1.3 Max V mV Unit
15/20
Electrical characteristic
STA2058
4.9
Table 14.
Symbol
GPS performances
V33=3.3 10%, TA = 27C, unless otherwise specified GPS performances
Value Parameter Reacquisition HOT Start Test Conditions Min Typ <1 50%, -130dBm, Fu 2ppm, Tu 2, Pu 30km <2.5 <34 <39 CEP 50%, 24hr static at 130dBm With external LNA Tracking -159 dBm 2 -146 Max s s s s m dBm Unit
TTFF Warm Start Cold Start Accuracy Autonomous Acquisition (Warm Start) Sensitivity
16/20
STA2058
Package information
5
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6. LQFP64 mechanical data and package dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K ccc 0.45 11.80 9.80 0.05 1.35 0.17 0.09 11.80 9.80 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 12.20 10.20 0.464 0.386 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.20 12.20 10.20 0.002 0.053 0.055 MIN. TYP. MAX. 0.063 0.006 0.057 inch
OUTLINE AND MECHANICAL DATA
0.0066 0.0086 0.0106 0.0035 0.464 0.386 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0177 0.0236 0.0295 0.0393 0.480 0.401 0.0079 0.480 0.401
0 (min.), 3.5 (min.), 7(max.) 0.080 0.0031
LQFP64 (10 x 10 x 1.4mm)
D D1 A D3 A1 48 49 33 32
0.08mm ccc Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
B
0051434 F
17/20
Package information Figure 7. LFBG144 mechanical data and package dimensions
mm DIM. MIN. A A1 A2 b D D1 E E1 e F ddd eee fff 9.85 0.35 9.85 1.21 0.21 1.12 0.40 10.0 8.80 10.0 8.80 0.80 0.60 0.10 0.15 0.08 0.45 TYP. MAX. 1.70 MIN. 0.0476 0.0083 0.0441 0.0138 0.0157 0.0177 TYP. MAX. 0.0669 inch
STA2058
OUTLINE AND MECHANICAL DATA
10.15 0.3878 0.3937 0.3996 0.3465 10.15 0.3878 0.3937 0.3996 0.3465 0.0315
Body: 10 x 10 x 1.7mm
0.0236 0.0039 0.0059 0.0031
LFBGA144 Low Profile Fine Pitch Ball Grid Array
7163385 D
18/20
STA2058
Revision history
6
Revision history
Table 15.
Date 23-Apr-2007 25-Jun-2007
Document revision history
Revision 1 2 Initial release. Added features summary, pin description, electrical characteristics and packages information. Changes
19/20
STA2058
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